Icom IC-F4021T User manual

SERVICE
MANUAL
UHF TRANSCEIVERS
S-14304HZ-C1
July 2006

This service manual describes the latest service information
for the IC-F4021T/S, IC-F4022T/S and IC-F4023T/S UHF
TRANSCEIVERS at the time of publication.
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit Icom parts numbers
2. Component name and informations
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
5030002760 LCD L3-0200HAY-3 IC-F4021T Main unit 5 pieces
8810009561 Screw PH BT M2 × 6 NI-ZK3 IC-F4021T Chassis 10 pieces
Addresses are provided on the inside back cover for your
convenience.
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 8 V. This will ruin the
transceiver.
DO NOT expose the transceiver to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when
connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100 mW)
to the antenna connector. This could damage the trans-
ceiver's front end.
To upgrade quality, any electrical or mechanical parts
and internal circuits are subject to change without
notice or obligation.
INTRODUCTION
CAUTION
ORDERING PARTS
1. Make sure a problem is internal before disassembling the transceiver.
2. DO NOT open the transceiver until the transceiver is disconnected from its power source.
3. DO NOT force any of the variable components. Turn them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insulated turning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the transceiver is defective.
6. DO NOT transmit power into a signal generator or a sweep generator.
7. ALWAYS connect a 40 dB to 50 dB attenuator between the transceiver and a deviation meter or spectrum analyzer when
using such test equipment.
8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.
Icom, Icom Inc. and logo are registered trademarks of Icom Incorporated (Japan) in the United States, the United
Kingdom, Germany, France, Spain, Russia and/or other countries.
REPAIR NOTES
MODEL Version Symbol Frequency Key Pad
IC-F4021T
U.S.A
[USA-02] 400–470 MHz 10-key
[USA-03] 450–520 MHz
IC-F4021S [USA-02] 400–470 MHz 4-key
[USA-03] 450–520 MHz
IC-F4022T EURO [EUR-02] 400–470 MHz 10-key
IC-F4022S [EUR-12] 4-key
IC-F4023T
GENERAL
[GEN-02] 400–470 MHz 10-key
[GEN-03] 450–520 MHz
IC-F4023S [GEN-02] 400–470 MHz 4-key
[GEN-03] 450–520 MHz

TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 DISASSEMBLY INSTRUCTIONS
SECTION 4 OPTIONAL UNIT INSTALLATION
SECTION 5 CIRCUIT DESCRIPITON
5-1 RECEIVER CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5-2 TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5-3 PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5-4 DIGITAL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5-5 POWER SUPPLY CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5-6 PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
SECTION 6 ADJUSTMENT PROCEDURES
6-1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6-2 FREQUENCY ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6-3 TRANSMIT ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6-4 RECEIVE ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
SECTION 7 PARTS LIST
SECTION 8 MECHANICAL PARTS AND DISASSEMBLY
SECTION 9 SEMICONDUCTOR INFORMATION
SECTION 10 BOARD LAYOUTS
SECTION 11 BLOCK DIAGRAM
SECTION 12 VOLTAGE DIAGRAM
SECTION 13 BC-160

1 - 1
SECTION 1 SPECIFICATIONS
[USA], [GEN] [EUR]
GENERAL
• Frequency coverage 400–470 MHz [USA], [GEN], [EUR]
450–512 MHz [USA]
450–520 MHz [GEN]
• Type of emission Wide 16K0F3E (25.0 kHz)
Middle – 14K0F3E (20.0 kHz)
Narrow 11K0F3E (12.5 kHz) 8K50F3E (12.5 kHz)
• Number of programable channels 128 channels (8 zones)
• Antenna impedance 50 Ω(nominal)
• Operating temperature range −22˚F to +140˚F –25˚C to +55˚C
• Power supply requirement Specified Icom’s battery packs only (Operatable voltage; 7.2 V DC negative ground)
• Current drain
(approx.) RX Stand-by 75 mA
Max.audio 300 mA
TX at 4 W 1.6 A
at 1 W 0.8 A
• Dimensions (projections not included) 2 3/32 (W) × 4 23/32 (H) × 1 9/32 (D) in 53.0 (W) × 120.0 (H) × 32.5 (D) mm
• Weight (with BP-231, approx.) 9.2 oz 280 g
TRANSMITTER
• Transmit output power 4 W (High), 2 W (Low2), 1 W (Low1)
• Modulation Variable reactance frequency modulation
• Max. permissible deviation Wide ±5.0 kHz
Middle – ±4.0 kHz
Narrow ±2.5 kHz
• Frequency error ±2.5 ppm ±1.5 kHz
• Spurious emission More than 70 dB 0.25 µW (≤1 GHz), 1.0 µW (>1 GHz)
• Adjacent channel power Wide More than 70 dB (75 dB typ.)
Middle – More than 70 dB (73 dB typ.)
Narrow More than 60 dB (68 dB typ.)
• Audio harmonic distortion 3% typ. (with 1 kHz AF 40% deviation)
• FM hum and noise
(without CCITT filter)
Wide More than 40 dB (46 dB typ.) –
Narrow More than 34 dB (40 dB typ.) –
• Residual modulation
(with CCITT filter)
Wide – More than 45 dB (55 dB typ.)
Middle – More than 43 dB (53 dB typ.)
Narrow – More than 40 dB (50 dB typ.)
• Limiting charact of modulation 60–100% of max. deviation
• Microphone impedance 2.2 kΩ
RECEIVER
• Receive system Double-conversion superheterodyne
• Intermediate frequencies 1st IF; 46.35 MHz, 2nd IF; 450 kHz
• Sensitivity 0.25 µV typ. at 12 dB SINAD −4 dBµV (EMF) typ. at 20 dB SINAD
• Squelch sensitivity (at threshold) 0.25 µV typ. −4 dBµV (EMF) typ.
• Adjacent Frequency
selectivity
Wide More than 70 dB (75 dB typ.)
Middle − More than 70 dB (73 dB typ.)
Narrow More than 60 dB (65 dB typ.)
• Spurious response More than 70 dB
• Intermodulation More than 70 dB (74 dB typ.) More than 65 dB (67 dB typ.)
• Audio output power 0.5 W typ. at 5% distortion with an 8 Ωload
• Audio output impedance 8 Ω
All stated specifications are subject to change without notice or obligation.
Measurements made in accordance with EIA-152/204D, TIA-603 ([USA], [GEN]) or EN 300 086 ([EUR]).

SECTION 2 INSIDE VIEWS
2 - 1
APC amplifier
(IC701: TA75S01F)
Power amplifier
(Q701: RD07MVS1)
Drive amplifier
(Q702: RD01MUS1)
Antenna switch
(D701: 1SV307)
LCD driver
(IC20: LC75834W)
+5 regulator
Q26: 2SB1580
Q27: XP6501
Q28: UNR9213J
CPU
(IC22: HD64F2238BTF13V)
EEPROM
(IC10: HN58X2464TI)
Reset IC
(IC8: BD5242G)
Analog switch
IC3:
CD4066BPWR
D/A converter
(IC12: M62364FP)
Crystal oscillator
15.3 MHz
(X2: CR-783)
VCO circuits
RX VCO
Q17: 2SC4226
D9, D11: HVC350B
TX VCO
Q16: 2SC4226
D10, D13: HVC350B
R5 regulator
Q25: 2SA1577
Q48: UNR9213J
S5 regulator
(Q23: 2SA1577)
T5 regulator
(Q24: 2SA1577)
Ceramic filter
450 KHz
(FI2: CFWM450F)
CPU5 regulator
(IC17: NJM2870)
PLL IC
(IC2: MB15A02PFV1)
AF amplifier
(IC15: TA7368FG)
IF amplifier
(Q7: 2SC5107)
IF IC
(IC9: TA31136FNG)
Pre-drive amplifier
(Q704: 2SC5006)
Pre-drive amplifier
(Q703: 2SC3356)
PA UNIT
MAIN UNIT
TOP VIEW BOTTOM VIEW
BOTTOM VIEW
TOP VIEW
()
1st mixer
(Q6: 3SK324)
()
()
()
()

SECTION 3 DISASSEMBLY INSTRUCTIONS
3 - 1
2 REMOVING THE MAIN UNIT
qRemove the main seal F.
wUnscrew VR nut G, and remove the top plate H.
3 REMOVING THE PA UNIT
qUnscrew 3 screws M.
wUnsolder 4 points N, and take off the PA UNIT in the
direction of the arrow.
1 REMOVING THE CHASSIS UNIT
qUnscrew ANT nut A, and remove knob B.
wUnscrew 2 screws C, and remove the jack panel.
eUnscrew 2 screws D, and unplug the connector Efrom
the chassis unit.
rTake off the chassis unit in the direction of the arrow from
the front panel.
eUnscrew 6 screws J.
rRemove the side plate I.
tUnsolder 8 points K, and remove the shield cover.
yUnsolder 8 points L, and take off the MAIN UNIT in the
direction of the arrow.
(Continued to right above)
CHASSIS UNIT
Jack panel Front panel
D
A
B
C
E
G
F
H
Shied cover
MAIN UNIT
K
K
J
L× 8
J
J
I
CHASSIS UNIT
M
N
N
PA UNIT

4 - 1
SECTION 4 OPTIONAL UNIT INSTALLATION
CAUTION! Optional unit installation should be done at authorized Icom servise center only.
Install the optional unit as follows.
qRotate [VOL] to turn the power OFF, and remove the
battery pack.
wRemove the unit cover as below. (The removed unit
cover can not be used again.)
UT-108R
UT-109R
UT-110R
NOTE: When uninstalling the unit
Be sure to re-solder the cut points as below when you
remove the unit. Otherwise, no transmit modulation or
receive AF output is available.
“DISC” “MIC”
eCut the pattern on the PC board at “MIC” and “DISC”
as below. (This modification is not necessary for
UT-108R installation.)
rInstall the unit as below.
Re-solder
tRemove the paper backing of the supplied unit cover,
and attach the unit cover and the battery pack, then
rotate [VOL] to turn the power ON.
ySet or modify the scrambler or decoder settings using
optional CS-F3020.

SECTION 5 CIRCUIT DESCRIPTION
5 - 1
5-1 RECEIVER CIRCUITS
5-1-1 ANTENNA SWITCHING CIRCUIT (PA UNIT)
The antenna switching circuit toggles the receive (RX) line and
transmit (TX) line.
The received signals from the antenna are passed through
the low-pass filter (ANT UNIT; L801, L802, C802–C806) and
antenna switch (D701, D704).
While transmitting, the voltage on the T5V line is applied
to D701 and D704, and these are ON. Thus the TX line is
connected to the antenna. Simultaneously, the RX line is
connected to the ground (GND) to prevent transmit signal
entering.
While receiving, no voltage is applied to the D701 and
D704, and these are OFF. Thus the TX line and the antenna
are disconnected to prevent received signals entering.
Simultaneously, the RX line is disconnected from the GND and
the received signals are passed through the low-pass filter
(L712, C750, C751). The filtered signals are applied to the RF
circuits.
5-1-2 RF CIRCUITS (MAIN UNIT)
RF circuits filter and amplify the received signals within the
frequency coverage.
The received signals from the antenna switching circuit are
passed though the two-staged bandpass filter (BPF; D19,
D25, L7, L8, C21–C23, C25, C27–C29) to filter-out unwanted
signals, and the filtered signals are applied to the RF amplifier
(Q5). The amplified received signals are then applied to the 1st
mixer (Q6) via another two-staged BPF (D14, D15, L11, C39–
C41, C44, C45).
5-1-3 1st IF CIRCUITS (MAIN UNIT)
The received signals are converted into the 1st IF signal,
filtered and amplified at the 1st IF circuits.
The received signals from the two-staged BPF (D14, D15,
L11, C39–C41, C44, C45) are applied to the 1st mixer (Q6)
and converted into the 46.35 MHz 1st IF signal by being mixed
with the local oscillator (LO) signal from the RX VCO (Q17, D9,
D11).
The converted 1st IF signal is passed through the 1st IF filter
(FI1) to filter-out adjacent signals, then applied to the 1st IF
amplifier (Q7). The amplified 1st IF signal is then applied to the
FM IF IC (IC9, pin 16).
5-1-4 2nd IF AND DEMODULATOR CIRCUITS
(MAIN UNIT)
The 1st IF signal is converted into the 2nd IF signal, and
demodulated.
The 1st IF signal from the 1st IF amplifier is applied to the 2nd
mixer in the FM IF IC (IC9, pin 16), and converted into the
450 kHz 2nd IF signal by being mixed with the 45.9 MHz 2nd
LO signal from the reference frequency oscillator (X2) via the
tripler (Q22) and BPF (L33, C163, C164, C166). The converted
2nd IF signal is output from pin 3, and passed through the 2nd
IF filters to remove sideband noise.
The 2nd IF signal is passed through the 2nd IF filter (FI2)
and applied to the FM IF IC (IC9, pin 5) again via the resistor
(R56).
The filtered 2nd IF signal is amplified at the limiter amplifier,
and FM-demodulated by the quadrature detector (IC9, pins 10,
11, X1). The demodulated AF signals are output from pin 9,
then applied to the AF amplifier circuits.
5-1-5 AF AMPLIFIER CIRCUITS (MAIN UNIT)
The demodulated AF signals from the FM IF IC are amplified
and filtered at AF circuits.
The demodulated AF signals from the FM IF IC (IC9, pin 9) are
passed through high-pass filter (HPF; IC5, pins 2, 1) to remove
tone signals. The filtered AF signals are passed through the
de-emphasis circuit (R142, C249) to obtain the 6 dB/oct of
frequency characteristic. The de-emphasized AF signals are
passed through the RX mute switch (Q32, Q33), AF switch
(Q36, Q37), HPF (IC5, pins 13, 14), analog switch (IC3, pins 1,
2), AF mixer (IC5, pins 6, 7) and analog switch (IC3, pins 10,
11) in sequence.
D/A converter
(IC12)
Mixer
RSSI
Quadrature
detector
24
23
1st IF signal from the 1st IF amplifier (Q7)
16
Noise
detector
R5V
X1
1110
FM IF IC (IC9)
Filter
amp.
Noise
amp.
Limiter
amp.
Demodulated signals
to the AF circuits
9
“NOIS” signal to the CPU (IC22: pin 75)
“RSSI” signal to the CPU (IC22: pin 50)
1312
Q22
X2
15.3 MHz
45.9 MHz BPF
2
3
8 7 35
FI2
R56
TCXO
• 2nd IF AND DEMODULATOR CIRCUITS

5 - 2
The AF signals from the analog switch (IC3, pin 11) are
applied to the volume buffer amplifier (IC6, pin 9). The buffer-
amplified AF signals are adjusted its level (= audio level)
by volume control pot (R315), then applied to the AF power
amplifier (IC15, pin 4) and amplified to the 0.5 W of audio
output power (max., at 8 Ωload).
The power-amplified AF signals are output from pin 10, then
applied to the internal speaker (CHASSIS; SP1) or an external
speaker via [SP] jack (J2).
5-1-6 SQUELCH CIRCUITS (MAIN UNIT)
5-1-6-1 NOISE SQUELCH
The squelch mutes the AF output signals when no RF signal
is received. By detecting noise components (around 30 kHz
signals) in the demodulated AF signals, the squelch circuit
toggles the mute switch and AF power amplifier ON and OFF.
A portion of the demodulated AF signals from the FM IF IC
(IC9, pin 9) is applied to the D/A converter (IC12, pin 24) for
level (= squelch threshold) adjustment. The level-adjusted
AF signals are output from pin 23 and passed through the
noise filter (IC9, pins 8, 7, R42, R44–R46, R382, C69, C70,
C413, C438). The filtered noise signals are amplified the noise
components only at the noise amplifier.
The amplified noise components are converted into the pulse-
type signal at the noise detector section, and output from pin
13 as the “NOIS” signal. The converted signal is applied to the
CPU (IC22, pin 75). Then the “RMUTE” signal from the CPU
(IC22, pin 96) to the RX mute switch (Q32) and analog switch
(IC3, pins 12, 13) becomes “Low” according to the “NOIS”
signal level to cut off the AF line.
At the same time, the “AFON” signal from the CPU (IC22,
pin 70) to the AF amplifier controller (Q41, Q42, D21, D23)
becomes “Low” and the controller turns the AF power amplifier
(IC15) OFF.
5-1-6-2 TONE SQUELCH
• CTCSS/DTCS
The tone squelch circuit detects tone signals and opens the
squelch only when receiving a signal containing a matched
sub audible tone. When the tone squelch is in use, and a
signal with a mismatched or no sub audible tone is received,
the tone squelch circuit mutes the AF signals even when the
noise squelch is open.
A portion of the demodulated AF signals is passed through the
active LPF (Q39) to filters CTCSS/DTCS signal. The filtered
signal is applied to the CPU (IC22, pin 46). The CPU compares
the applied signal and the set CTCSS/DTCS, then the CPU
controls the status (“Low” or “High”) of “RMUTE” and “AFON”
signals as same as “NOISE SQUELCH”.
• DTMF
DTMF signals in the demodulated AF signals are passed
through the LPF (IC6, pins 5, 7) to remove unwanted
components (voice signals), then applied to the CPU (IC22,
pin 45) and decoded.
5-2 TRANSMITTER CIRCUITS
5-2-1 MICROPHONE AMPLIFIER CIRCUITS
(MAIN UNIT)
The AF signals from the microphone (MIC signals) are filtered
and level-adjusted at microphone amplifier circuits.
• MIC SIGNALS
MIC signals from the microphone are applied to the A/D switch
(IC25, pins 7, 1), then applied to the D/A converter (IC12, pin
1).
The level-adjusted MIC signals are output from pin 2, and
passed through the MIC mute switch (Q31), HPF (IC5, pins
13, 14) and pre-emphasis circuit (R137, R138, C260), then
applied to the MIC amplifier (IC5, pin 9). The amplified MIC
signals are output from pin 8, and passed through the analog
switch (IC3, pins 4, 3), AF mixer (IC5, pins 6, 7) where the MIC
signals and tone signals are mixed with.
• TONE SIGNALS
The CTCSS/DTCS signals are generated by the CPU (IC22)
and output from pins 19–21. The output signals are passed
through the 3 resistors (R222–R224) to change its waveform.
The waveform changed CTCSS/DTCS signals are passed
through the LPF (IC7, pins 10, 8), tone filter switch (Q40) and
D/A converter (IC12, pins 12, 11) for level adjustment. The
level adjusted CTCSS/DTCS signals are then applied to the
AF mixer (IC5, pin 6).
DTMF signals are generated by the CPU (IC22) and output
from pin 43. The output DTMF signals are passed through two
LPFs (IC6, pins 3, 1 and pins 12, 14), then applied to the AF
mixer (IC5, pin 6).
The mixed AF signals are output from pin 7 of the AF mixer
(IC5) and passed through the analog switch (IC3, pins 9, 8),
then applied to the AF amplifier (IC7, pin 6). The amplified AF
signals are output from pin 7, and applied to the D/A converter
(IC12, pin 9) to be adjusted its level (= deviation). The level-
adjusted MIC signals are then applied to the modulation
circuits as the modulation signals.
5-2-2 MODULATION CIRCUITS
(MAIN UNIT)
The modulation circuits modulate the VCO oscillating signal
using the modulation signals.
The modulation signals from the D/A converter (IC12, pin 10)
are applied to the D12 at the TX VCO (Q16, D10, D13) to
modulate the VCO oscillating signal by changing the reactance
of D12.
The modulation signals are also applied to the reference
frequency oscillator (X2) via D/A converter (IC12, pins 16, 15)
and the buffer (IC7, pins 12, 14), to ensure the modulation of
lower frequency components of the modulation signals.
The modulated VCO output is buffer-amplified by Q15 and
Q29, then applied to the transmit amplifiers as the transmit
signal via TX/RX switches (D16 is ON, D17 is OFF).

5 - 3
5-2-3 TRANSMIT AMPLIFIERS (PA UNIT)
The transmit signal from the VCO is amplified to the transmit
output level by the transmit amplifiers.
The transmit signal from the TX/RX switches (MAIN UNIT; D16
is ON, D17 is OFF) is amplified by two pre-drive amplifiers
(Q704, Q703), drive amplifier (Q702) and power amplifier
(Q701) in sequence to obtain 0.5 W (approx.) of transmit
output power.
The power-amplified transmit signal is passed through the
antenna switch (D701), then applied to the antenna via the
LPF (ANT UNIT; L801, L802, C802–C806).
5-2-4 APC CIRCUIT (PA UNIT)
The APC (Automatic Power Control) circuit prevents the
transition of the transmit output power level which is caused by
load mismatching or heat effect, etc.
A portion of transmit signal is detected by the transmit power
detectors (D702, D703) to produce DC voltage corresponding
to the transmit output power level. The detected voltage is
applied to the APC amplifier (IC701, pin 3). The transmit power
setting voltage “T1” from the D/A converter (MAIN UNIT;
IC23, pin 1) is applied to another input terminal (pin 1) as the
reference voltage.
The APC amplifier compares the detected voltage and
reference voltage, and the difference of the voltage is output
from pin 4. The voltage controls the bias of the drive (Q702)
and power (Q701) amplifiers to reduce/increase the gain of
these amplifiers for stable transmit output power.
The transmit power muting is carried out by the TX mute switch
(MAIN UNIT; Q46), using the “TMUT” signal from the CPU
(MAIN UNIT; IC22, pin 35).
5-2-5 OVER CURRENT DETECTION CIRCUIT
(PA UNIT)
The driving current of the drive (Q702) and power (Q701)
amplifiers is detected at the current detector (Q705, Q706)
by detecting the difference of voltage between both terminals
of R729. The detected voltage “ISENS” is applied to the CPU
(MAIN UNIT; IC22, pin 47).
In case of the over current is detected, the CPU outputs “TMUT”
signal from pin 35 to TX mute switch (MAIN UNIT; Q46) to
stop the transmitting to protect the transmit amplifiers (Q701–
Q704).
Power
amp.
APC
amp.
Drive
amp.
+
1
3 4
–
VCC
MAIN UNIT PA UNIT
to the
antenna
T1
TMUT
Transmit signal
from the TX/RX
switches
(D16, D17)
T5V
Q702
Q703Q704
APC
P_DET
IC701
Q701
to the receiver circuits
LPF LPF
ANT
SW
D703
D702
D701
TX power
detectors
Q46
Pre-drive
amp.
Pre-drive
amp.
ANT UNIT
Current
detector
ISENS
Q705, Q706
• APC CIRCUIT

5 - 4
5-3 PLL CIRCUITS
5-3-1 VOLTAGE CONTROLLED OSCILLATORS
(VCOs; MAIN UNIT)
VCO is an oscillator whose oscillating frequency is controlled
by adding voltage (lock voltage).
This transceiver has 2 VCOs RX VCO (Q17, D9, D11) and
TX VCO (Q16, D10, D13). The RX VCO oscillates the 1st LO
signals, and the TX VCO oscillates the transmit signal.
• RX VCO
The output signals are amplified by the buffer amplifiers (Q15,
Q29), and applied to the 1st mixer (Q6) via TX/RX switches
(D16 is OFF, D17 is ON) and LPF (L46, C396, C397), to be
mixed with the received signals to produce the 46.35 MHz 1st
IF signal.
• TX VCO
The output signal is applied to the transmit amplifiers via the
buffer amplifiers (Q15, Q29) and TX/RX switches (D16 is ON,
D17 is OFF).
A portion of each VCO output is applied to the PLL IC (IC2, pin
8) via the buffer amplifier (Q15), doubler (Q14) and BPF (L32,
L34, C196, C197, C205).
5-3-2 PLL IC (MAIN UNIT)
The PLL circuit provides stable oscillation of the transmit
frequency and receive 1st LO frequency. The PLL output
frequency is controlled by the divided ratio (N-data) from the
CPU.
The VCO output signal from the BPF (L32, L34, C196, C197,
C205) is applied to the PLL IC (IC2, pin 8). The applied
signal is divided at the prescaler and programmable counter
according to the “SSO” signal from the CPU (IC22, pin 99).
The divided signal is phase-compared with the reference
frequency signal from the reference frequency oscillator (X2),
at the phase detector.
The phase difference is output from pin 5 as a pulse type
signal after being passed through the internal charge pump.
The output signal is converted into the DC voltage (lock
voltage) by passing through the loop filter (R94–R96, C16,
C17, C146). The lock voltage is applied to the varactors (D9
and D11 of RX VCO, D10 and D13 of TX VCO) and locked to
keep the VCO frequency constant.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the VCO oscillating frequency.
• PLL CIRCUITS
Loop
filter
Modulation signals
from the D/A converter
(IC12, pin10)
RX VCO
Q16, D10, D13
D12
Q17, D9, D11
TX VCO
PLL control signals from the CPU (IC22)
PLL unlock signal
to the CPU (IC22, pin 34)
15.3 MHz
reference frequency signal
Buffer
Buffer
×2
to the transmit amplifiers
to the1st IF circuits
D17
D16
BPF
PLST
SSO
SCK
5
7
8
1
9
10
11
PLL IC (IC2)
Shift register
Prescaler
Phase
detector
Charge
pump
Programmable
divider
Reference
counter
Q15
Q29
Q14
X2
TCXO


5 - 5
CPU5V
regurator
+5V
regurator
S5V
regurator
T5V
regurator
R5V
regurator
Power switch
R315
F701
(PA unit )
Q26–Q28
IC17
Q23
Q24
Q25, Q48
VCC
CPU5
CPU
+5V
S5V
“S5C”
“PWON”
Voltage line
Control signal
8
22
87
88
“T5C”
“R5C”
T5V
LED backlight driver (Q45),
LCD driver (IC20),
D/A converter (IC12), etc.
CPU (IC22),
EEPROM (IC10),
Reset IC (IC8), etc.
Drive amplifier (Q702),
Power amplifier (Q701), etc.
PLL IC (IC2),
VCO’s, etc.
Transmit circuits
Receive circuits R5V
(IC22)
Battery pack
5-4 POWER SUPPLY CIRCUITS
Voltage from the attached battery pack is routed to whole of the circuit in the transceiver via a switch and regulators.

5 - 6
5-5-1 CPU (IC22)
Pin
No.
Port
Name Description
1−3 KR1−
KR3 Input ports for dealer-programmable keys.
4−8 KS0−
KS4 Output ports for dealer-programmable keys.
9 BUSY Outputs “BUSY” signal to the DSP UNIT.
10 CCS Outputs chip-select signal to the DSP UNIT.
11 SCK Outputs serial clock signal to the PLL IC (IC2, pin 9)
and D/A converter (IC12, pin 7/IC23, pin 7).
19−
21
CENC0−
CENC2 Output ports for CTCSS/DTCS signal.
22 S5C
Outputs S5V line control signal to the S5V
regurator (Q23).
“Low”=While power save mode.
26 T5C
Outputs T5V line control signal to the T5V line
regurator (Q24, Q49).
“Low”=While transmitting.
27 R5C
Outputs R5V line control signal to the R5V line
regurator (Q25).
“Low”=While receiving.
31 PLST Outputs PLL strobe signal to the PLL IC (IC2, pin 11).
34 ULCK
Input port for PLL unlock detect signal from the
PLL IC (IC2, pin 7).
“Low”=While the PLL circuit is unlocked.
35 TMUT
Outputs transmit mute signal to the transmit mute
switch (Q46).
“High”=Transmitting is muted.
36 MONI Input port for [SIDE1] key (S5).
“Low”=While the key is pushed.
37 EMER Input port for top switch (S1).
“Low”=While the switch is pushed.
39 DSDA Outputs serial data to the D/A converter (IC23, pin 6).
43 SENC Outputs DTMF signals to the LPF (IC6, pin 3).
44 BEEP Outputs beep sounds to the D/A converter (IC12,
pin 21).
45 SDEC Input port for DTMF signals.
46 CDEC Input port for CTCSS/DTCS signals.
48 BATV Input port for remaining battery power.
49 LVIN Input port for VCO lock voltage.
50 RSSI Input port for receive signal strength level signal
from the FM IF IC (IC9, pin 12).
59 RES
Input port for CPU reset signal from the reset IC
(IC8, pin 1).
“Low”=When the CPU is reset.
69 CSFT Outputs CPU clock shift signal to the clock shift
switch (D6).
70 AFON
Outputs AF power amplifier (IC15) control signal to
the AF power amplifier controller (Q41, Q42, D21,
D23).
“High”=The AF power amplifier is ON.
71 DAST Outputs strobe signal to the D/A converter (IC12,
pin 6).
72 DUSE
Outputs CTCSS/DTCS select signal to the tone
filter switch (Q40).
“High”=While DTCS is in use.
75 NOIS Input port for noise signal from the FM IF IC (IC9,
pin 13).
82 ESDA Outputs serial data to the EEPROM (IC10, pin 5).
85 ESCL Outputs clock signal to the EEPROM (IC10, pin 6).
Pin
No.
Port
Name Description
89 DIGI
Outputs Analog/Digital select signal to the A/D
switch (D2, D3).
“High”=Digital mode is selected.
91 LSO Outputs serial data to the LCD driver (IC20, pin 48).
92 LSCK Outputs clock signal to the LCD driver (IC20, pin 47).
93 LCS Outputs chip-enable signal to the LCD driver (IC20,
pin 46).
94 LINH Outputs display inhibit signal to the LCD driver
(IC20, pin 45).
95 LIGT
Outputs LCD backlight control signal to the
backlight LED’s (DS1, DS2) driver (Q45).
“Low”=While the backlight is ON.
96 RMUTE
Outputs AF mute signal to the analog switch (IC3,
pins 12, 13).
“Low”=While the squelch is close or transmitting.
97 MMUTE
Outputs MIC signals mute signal to the analog
switch (IC3, pin 5) and MIC mute switch (Q31).
“Low”=While receiving.
99 SSO Outputs serial data to the PLL IC (IC2, 10) and D/A
converter (IC12, pin 8).
100 KR0 Input ports for dealer-programmable keys.
5-5-2 D/A CONVERTER (IC12)
Pin
No.
Port
Name Description
2MCGO
Outputs level-adjusted MIC signals to the MIC mute
switch (Q31).
10,
16 MOD Outputs modulation signal to the modulation circuits
(D2).
14 REF Outputs reference frequency control voltage to the
reference frequency oscillator buffer (IC7, pin 13).
15 BAL Outputs modulation balance control signal to the
reference frequency oscillator buffer (IC7, pin 12).
22 BEEPO Outputs beep sounds to the AF volume buffer (IC6,
pin 9).
23 SQLC Outputs level-adjusted AF signals to the noise filter
(IC9, pins 7, 8, R42, R44−R46, C69, C70, C413).
5-5-3 D/A CONVERTER (IC23)
Pin
No.
Port
Name Description
1T1
• While receiving
Outputs BPF tuning voltage to the tunable BPF
(D19, D25, L7, L8, C21−C23, C25, C27−C29).
• While transmitting (as “APC” signal)
Outputs transmit mute signal to the transmit mute
switch (Q46).
2T2
Outputs BPF tuning voltage to the tunable BPF
(D14, D15, L9, L11, C19, C36, C39−C41,
C44, C45).
3TXLVA
Outputs oscillating frequency adjust voltage to the
TX VCO (Q16, D10, D13).
4RXLVA
Outputs oscillating frequency adjust voltage to the
RX VCO (Q17, D9, D11).
5-5 PORT ALLOCATIONS

SECTION 6 ADJUSTMENT PROCEDURES
6-1 PREPARATION
When adjusting IC-F4020 series, CS-F3020 CLONING SOFTWARE, CS-F3020 ADJ ADJUSTMENT SOFTWARE (Rev. 1.0 or later),
OPC-478/U JIG CABLE (modified OPC-478/U CLONING CABLE; see the page 6-2) and the following test equipments are required.
EQUIPMENT GRADE AND RANGE EQUIPMENT GRADE AND RANGE
DC power supply Output voltage
Current capacity
: 7.2 V DC
: More than 2 A External speaker Input impedance
Capacity
: 8 Ω
: 1 W or more
FM deviation meter Frequency range
Measuring range
: DC–600 MHz
: 0 to ±10 kHz Attenuator Power attenuation Capacity
: 20 or 30 dB
: 6 W
Frequency counter
Frequency range
Frequency accuracy
Sensitivity
: 0.1–600 MHz
: ±1 ppm or better
: 100 mV or better
Standard signal
generator (SSG)
Frequency range
Output level
: 0.1–600 MHz
: 0.1 µV to 32 mV
(–127 to –17 dBm)
RF power meter
Measuring range
Frequency range
Impedance
SWR
: 0.1–6 W
: 100–600 MHz
: 50 Ω
: Better than 1.2 : 1
Oscilloscope Frequency rang
Measuring range
: DC–20 MHz
: 0.01–20 V
6 - 1
▄SYSTEM REQUIREMENTS (for the ADJUSTMENT SOFTWARE)
• Microsoft®Windows®98/98SE/Me/2000/XP • RS-232C serial port (D-sub 9 pin) or USB port
▄STARTING SOFTWARE ADJUSTMENT
qConnect the transceiver and PC with OPC-478/U JIG
CABLE.
wTurn the transceiver power ON.
eBoot up Windows, and click the program group ‘CS-F3020
ADJ’ in the ‘Programs’ folder of the [Start] menu, then
CS-F3020 ADJ’s window appears.
rClick ‘Connect’ on the CS-F3020 ADJ’s window, then the
window shows transceiver’s condition and adjustment
items as below.
tSet or modify adjustment data as specified.
▄ BEFORE STARTING SOFTWARE ADJUSTMENT
Clone the adjustment frequencies and settings into the
transceiver, and set the configuration using the CS-F3020
CLONING SOFTWARE before starting the software adjustment.
Otherwise, the software adjustment can not be started.
CAUTION!: BACK UP the originally programmed memory
data in the transceiver before programming the
adjustment frequencies. When program the
adjustment frequencies into the transceiver, the
transceiver’s memory data will be overwritten
and lose original memory data at the same time.
Microsoft and Windows are registered trademarks of Micro-
soft Corporation in the U.S.A. and other countries.
▄ ADJUSTMENT SOFTWARE INSTALLATION
qQuit all applications when Windows is running.
wInsert the CD into the appropriate CD drive.
eDoublelick the “Setup.exe” contained in the ‘CS-F3020
ADJ’ folder in the CD drive.
rThe “Welcome to the InstallShield Wizard for CS-F3020
ADJ” will appear. Click [Next>].
tThe “Choose Destination Location” will appear. Then click
[Next>] to install the software to the destination folder. (e.g.
C:\Program Files\Icom\CS-F3020 ADJ)
y
After the installation is completed, the “InstallShield Wiz-
ard Complete” will appear. Then click [Finish].
uEject the CD.
iProgram group ‘CS-F3020 ADJ’ appears in the ‘Programs’
folder of the start menu, and ‘CS-F3020 ADJ’ icon ap-
pears on the desk top screen.
• ADJUSTMENT FREQUENCY LIST
CH FREQUENCY (MHz) ADJUSTMENT ITEM
LOW BAND HIGH BAND
1 400.000 450.000 TX power
Mode
: Low1
: Wide
2 470.000 512.000 [USA]
520.000 [GEN]
TX power
Mode
: Low1
: Wide
3 435.000 485.000 TX power
Mode
: High
: Wide
4 435.000 485.000 TX power
Mode
: Low2
: Wide
5 435.000 485.000 TX power
Mode
: Low1
: Narrow
6 435.000 485.000
TX power
Mode
DTCS
: Low1
: Wide
: 007
7* 435.000 N/Available TX power
Mode
: Low1
: Middle
8 435.000 485.000
TX power
Mode
CTCSS
: Low1
: Wide
: 151.4 Hz
*; [EUR] only

6 - 2
IC-F4020 series
FM
deviation meter Osciiloscope
to the antenna connector
Attenuator
10 dB or 20 dB
RF power meter
0.1–5 W/50
Frequency
counter
Standard signal generator
0.1 µV to 32 mV
(–127 dBm to –17 dBm)
CAUTION!
DO NOT transmit while
the SSG is connected to
the antenna connector
SINAD meter
Speaker (8 )
To [SP] jack JIG cable 2
JIG cable 1
PC
to USB port
to RS-232C port
OPC-478 (RS-232C type)
OPC-478U (USB type)
Audio
generator
AC
millivoltmeter
To [MIC] jack
To MIC/GND
To SP /
+
–
• CONNECTION
• JIG CABLES
3-conductor 3.5(d) mm plug
(SP + )
(CLONE) OPC-478/U
(GND)
(SP) )
[JIG cable 2]
JIG cable
2-conductor 2.5 (d) mm plug
(MIC)
(GND)
33 kΩ
(to the audio generator “ + ”
)
[JIG cable 1]
)
PTT
“

6 - 3
Reference frequency
Receive sensitivity (Manually)
PLL lock voltage preset
S-meter
Reload data
PLL lock voltage (verify)
Squelch
*; [EUR] only
CTCSS/DTCS deviation
FM deviation (Narrow)
FM deviation (Middle*/Wide)
Modulation balance
Transmit output power (Hi)
Transmit output power (L2)
Transmit output power (L1)
Tq
PLL lock voltage
w
e
r
t
y
u
i
!1
!2
!0
q
w
e
r
t
y
u
i
!4
!5
!6
o
!3
o
!0
!1
!2
!3
!4
!5
Receive sensitivity (Automatically)
!6
• PC SCREEN EXSAMPLE

6 - 4
6-2 FREQUENCY ADJUSTMENT
Select an adjustment item using [↑] / [↓] keys, then set to the specified value using [←] / [→] keys on the connected PC’s keyboard.
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT OPERATION
PLL LOCK
VOLTAGE
[RX LVA]
1 • Channel
• Receiving
: CH 1 PC
screen
Click [Reload (F5)] button, then
check the “LVIN” item on the
CS-F3020 ADJ’s screen as below.
1.2 V
[TX LVA] 2 • Channel
• Transmitting
: CH 1
CONVENIENT: The “PLL LOCK VOLTAGE” can be adjusted automatically.
1: Set the Lock voltage preset ([RX LVA] and [TX LVA]) to “179 (3.15 V).”
2: Push the [ENTER] key on the connected PC’s keyboard.
1 • Channel
• Receiving
: CH 2 PC
screen
Click [Reload (F5)] button, then
check the “LVIN” item on the
CS-F3020 ADJ’s screen.
2.8–4.0 V
[Low band]
3.0–4.2 V
[High band]
(Verify)
2 • Channel
• Transmitting
: CH 2 3.0–4.2 V
[Low]/[High] bands
(Verify)
REFERENCE
FREQUENCY
[REF]
1 • Channel : CH 1 Top
panel
Loosely couple a frequency
counter to the antenna connector.
470.000 MHz
[Low band]
• Connect an RF power meter to the
antenna connector.
• Transmitting
512.000 MHz [USA]
520.000 MHz [GEN]
[High band]

6 - 5
6-3 TRANSMIT ADJUSTMENT
Select an adjustment item using [↑] / [↓] keys, then set to the specified value using [←] / [→] keys on the connected PC’s keyboard.
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT OPERATION
OUTPUT
POWER
[Power (Hi)]
1 • Channel
• Transmitting
: CH 3 Top
panel
Connect an RF power meter to
the antenna connector.
4.0 W
[Power (L2)] 2 • Channel
• Transmitting
: CH 4 2.0 W
[Power (L1)] 3 • Channel
• Transmitting
: CH 5 1.0 W
FM
DEVIATION
(NARROW)
[MOD N]
1 • Channel : CH 5 Top
panel
Connect the FM deviation me-
ter to the antenna connector
through an attenuator.
±2.05 to ±2.15 kHz
• Connect an audio generator to the JIG
cable and set as;
Frequency : 1.0 kHz
Level : 150 mV rms
• Set the FM deviation meter to same condi-
tion as “MODULATION BALANCE."
• Transmitting
(WIDE)
[MOD ratio]
2 • Channel
• Transmitting
: CH 6 ±4.05 to ±4.15 kHz
(MIDDLE)*
[MOD ratio]
3 • Channel
• Transmitting
: CH 7 ±3.15 to ±3.25 kHz
MODULATION
BALANCE
[BAL]
1 • Channel : CH 5 Top
panel
Connect the FM deviation me-
ter to the antenna connector
through an attenuator.
Set to square wave form
• No audio applied to the JIG cable.
• Set an FM deviation meter same as;
HPF
LPF
De-emphasis
Detector
: OFF
: 20 kHz
: OFF
: (P–P)/2
• Transmitting
CTCSS/DTCS
DEVIATION
[CTCS/DTCS]
1• Channel : CH 8 Top
panel
Connect an FM deviation meter to
the antenna connector through
an attenuator.
±0.68 to ±0.72 kHz
• No audio applied to the JIG cable.
• Set the FM deviation meter to same condi-
tion as “MODULATION BALANCE."
• Transmitting
*; [EUR] only.

6 - 6
6-4 RECEIVE ADJUSTMENT
Select an adjustment item using [↑] / [↓] keys, then set to the specified value using [←] / [→] keys on the connected PC’s keyboard.
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT LOCATION
RECEIVE
SENSITIVITY
[BPF (T1)]
[BPF (T2)]
NOTE: “RECEIVE SENSITIVITY” must be adjusted before “S-METER.” Otherwise, “S-METER” will not be
adjusted properly.
1• Channel : CH 1 [MIC/SP]
jack
Connect the SINAD meter
with an 8 Ωload to the JIG
cable.
Minimum distortion
level
• Connect the SSG to the antenna connector
and set as;
Frequency
Level
Modulation
Deviation
• Receiving
: 400.000 MHz [Low band]
450.000 MHz [High band]
: +20 dBµ†(–87 dBm)
: 1 kHz
: ±3.5 kHz
CONVENIENT:
The “RECEIVE SENSITIVITY” can be adjusted automatically.
1: Put the cursor on “BPF ALL” and push [ENTER] key.
2: The connected PC tunes BPF’s to peak levels automaticaly.
S-METER
[RSSI]
1• Channel : CH 1 Push the [ENTER] key on the connected PC’s keyboard to
set “S3” level.
• Connect the SSG to the antenna connector
and set as;
Frequency
Level
Modulation
Deviation
• Receiving
: 400.000 MHz [Low]
450.000 MHz [High]
: +23 dBµ† (–84 dBm)
: 1 kHz
: ±3.5 kHz
2• Set the SSG as;
Level
• Receiving
: –7 dBµ† (–114 dBm)
Push the [ENTER] key on the connected PC’s keyboard to
set “S1” level.
SQUELCH
[SQL]
1 • Channel : CH 4 External
speaker
Connect an 8 Ω speaker to
the JIG cable.
Set the [SQL] to the
value that the audio
signals just appears.
• Close the squelch by adjusting the value of
[SQL] item on the CS-F3020 ADJ’s screen.
• Connect the SSG to the antenna connector
and set as;
Frequency
Level
Modulation
Deviation
• Receiving
: 435.000 MHz [Low]
485.000 MHz [High]
: –14 dBµ† (–121 dBm)
: 1 kHz
: ±3.5 kHz
†; The output level of the standard signal generator (SSG) is indicated as the SSG’s open circuit.

7 - 1
SECTION 7 PARTS LIST
M.=Mounted side (T: Mounted on the Top side, B: Mounted on the BoTom side)
[MAIN-A UNIT] (for Low band)
REF ORDER DESCRIPTION M. H/V
NO. NO.
LOCATION
IC2 1140005991 S.IC MB15A02PFV1-G-BND-ERE1 T 81.2/34.5
IC3 1130011770 S.IC CD4066BPWR B 40.4/22
IC5 1110005320 S.IC NJM13403V-TE1 B 40.4/12.8
IC6 1110006350 S.IC LM2902PWR B 55.4/28.7
IC7 1110005340 S.IC NJM12902V-TE1 B 40.4/40.8
IC8 1110006260 S.IC BD5242G-TR B 21.3/42
IC9 1110003201 S.IC TA31136FNG (EL) T 81.6/17
IC10 1140008650 S.IC HN58X2464TI B 4.4/37.1
IC12 1190001350 S.IC M62364FP 600D B 40.4/30.6
IC15 1110001811 S.IC TA7368FG (5,ER) T 98.9/18.3
IC17 1110005350 S.IC NJM2870F05-TE1 B 95.2/17
IC20 1130009090 S.IC LC75834W-TLM-E T 57.3/20.3
IC22 1140011511 S.IC HD64F2238BTF13V B 16.4/24.4
IC23 1190001340 S.IC M62334FP 600C T 99.9/42.5
IC24 1110005310 S.IC AN6123MS B 30/12.4
IC25 1130009981 S.IC TC7W53FK (TE85L F) B 28.4/4.8
Q5 1580000731 S.FET 3SK293 (TE85L F) B 91.6/38.2
Q6 1580000800 S.FET 3SK324UG-TL-E B 88.6/22.8
Q7 1530003311 S.TR 2SC5107-O (TE85R F) T 88.4/12.5
Q8 1530002601 S.TR 2SC4215-O (TE85R F) T 76/10.9
Q9 1590001330 S.TR DTA114EUA T106 B 60.2/20.4
Q14 1530003980 S.TR 2SC5700WB-TR-E B 79.9/31.3
Q15 1530003260 S.TR 2SC5006-T1 B 73.1/29.9
Q16 1530002920 S.TR 2SC4226-T1 R25 B 75.7/25.5
Q17 1530002920 S.TR 2SC4226-T1 R25 B 74.7/32.3
Q18 1590001400 S.TR XP1214 (TX) T 71.3/31.7
Q19 1590003290 S.TR UNR9213J-(TX) T 71.4/29.3
Q20 1530002851 S.TR 2SC4116-BL (TE85R F) B 98.6/25.3
Q21 1560000541 S.FET 2SK880-Y (T5RICOM F) T 76.5/26.8
Q22 1530003260 S.TR 2SC5006-T1 T 80.7/24
Q23 1510001110 S.TR 2SA1577T106R B 51/6.3
Q24 1510001110 S.TR 2SA1577T106R B 50.4/19.3
Q25 1510001110 S.TR 2SA1577T106R B 85.7/12.3
Q26 1520000850 S.TR 2SB1580T100 B 101.6/17.9
Q27 1590001190 S.TR XP6501-(TX) .AB B 101.7/22.7
Q28 1590003290 S.TR UNR9213J-(TX) B 99.4/20.6
Q29 1530003980 S.TR 2SC5700WB-TR-E B 78.2/25.1
Q31 1560001360 S.FET 2SK3019 TL B 41.9/6.8
Q32 1560001360 S.FET 2SK3019 TL B 37.7/6.8
Q33 1590003290 S.TR UNR9213J-(TX) B 35.1/6.8
Q34 1560001360 S.FET 2SK3019 TL B 46.6/12.8
Q35 1590003290 S.TR UNR9213J-(TX) B 46.6/15.2
Q36 1560001360 S.FET 2SK3019 TL B 37.7/4.6
Q37 1590003290 S.TR UNR9213J-(TX) B 40/4.6
Q39 1590001650 S.TR XP4601 (TX) B 55.2/10.4
Q40 1590003290 S.TR UNR9213J-(TX) B 40.5/37
Q41 1590001190 S.TR XP6501-(TX) .AB T 96.4/24.6
Q42 1520000460 S.TR 2SB1132 T100 R T 100.4/24.5
Q43 1590003380 S.TR UNR9111J-(TX) T 78.4/7.2
Q44 1590003270 S.TR UNR9210J-(TX) B 28.3/20
Q45 1590003230 S.TR UNR9113J-(TX) T 53.9/4.8
Q46 1590003290 S.TR UNR9213J-(TX) T 98.8/32.9
Q47 1590003290 S.TR UNR9213J-(TX) B 84.5/15.7
Q48 1590003290 S.TR UNR9213J-(TX) B 86.6/14.9
D2 1750001070 S.DIO DAN235ETL T 69.3/16.8
D3 1750001070 S.DIO DAN235ETL T 72.2/16.8
D4 1790001250 S.DIO MA2S111-(TX) T 84/28.9
D6 1790001260 S.DIO MA2S077-(TX) B 27.7/30.7
D8 1790001250 S.DIO MA2S111-(TX) B 98.6/23.3
D9 1750000711 S.VCP HVC350BTRF-E B 68.6/29.3
D10 1750000711 S.VCP HVC350BTRF-E B 70/27.9
D11 1750000711 S.VCP HVC350BTRF-E B 68.3/31.8
D12 1720000570 S.VCP MA368 (TX) B 68.5/26.4
D13 1750000711 S.VCP HVC350BTRF-E B 71.4/25.6
D14 1750000711 S.VCP HVC350BTRF-E B 86/35.1
D15 1750000711 S.VCP HVC350BTRF-E B 86/36.4
D16 1750000581 S.DIO 1SV307 (TPH3 F) B 88.6/13.8
D17 1790001260 S.DIO MA2S077-(TX) B 87.4/17.8
D19 1750000711 S.VCP HVC350BTRF-E B 94.9/40.1
D20 1750000711 S.VCP HVC350BTRF-E B 96.2/40.1
D21 1750000520 S.DIO DAN222TL B 31.9/21.3
D23 1790001250 S.DIO MA2S111-(TX) B 31.8/23
D24 1750000711 S.VCP HVC350BTRF-E B 100/39.1
D25 1750000711 S.VCP HVC350BTRF-E B 101.3/39.1
D28 1790001670 S.DIO RB706F-40T106 B 28/17.7
D29 1750000711 S.VCP HVC350BTRF-E B 86/33.8
FI1 2030000150 S.MLH FL-335 (46.350 MHz) T 89.9/19.9
FI2 2020001530 CER CFWLB450KFFA-B0
FI3 2020002220 S.CER SFPKA450KH1A-R1 B 61.3/13.7
S.=Surface mount
[MAIN-A UNIT] (for Low band)
REF ORDER DESCRIPTION M. H/V
NO. NO.
LOCATION
X1 6070000191 S.DCR CDBKB450KCAY24-R0 B 80/16.9
X2 6050011940 S.XTL CR-783 (15.3 MHz)
[F4021], [F4023] only B 61.6/38.9
6050012380 S.XTL CR-826 (15.3 MHz) B 61.6/38.9
X6 6050011830 S.XTL CR-774 (12.288 MHz) B 31.2/31
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R23 7030005110 S.RES ERJ2GEJ 224 X (220 k) B 88.2/33.2
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R27 7030005310 S.RES ERJ2GEJ 124 X (120 k) B 86.4/23.4
R28 7030005080 S.RES ERJ2GEJ 823 X (82 k) B 84.7/23.4
R29 7030004980 S.RES ERJ2GEJ 101 X (100) B 90.9/20.6
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R33 7030010040 S.RES ERJ2GEJ-JPW T 89.1/14.6
R34 7030008300 S.RES ERJ2GEJ 184 X (180 k) T 87.3/14.6
R35 7030007290 S.RES ERJ2GEJ 222 X (2.2 k) T 86.4/14.6
R36 7030007300 S.RES ERJ2GEJ 332 X (3.3 k) B 81.4/12.6
R38 7030005090 S.RES ERJ2GEJ 104 X (100 k) T 81.7/12.2
R39 7030004970 S.RES ERJ2GEJ 470 X (47) B 81.4/11.6
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R42 7030005120 S.RES ERJ2GEJ 102 X (1 k) T 74.4/20.7
R43 7030005000 S.RES ERJ2GEJ 471 X (470) T 78/13.5
R44 7030005700 S.RES ERJ2GEJ 274 X (270 k) T 78/20.7
R45 7030008290 S.RES ERJ2GEJ 183 X (18 k) T 76.3/20.7
R46 7030005030 S.RES ERJ2GEJ 152 X (1.5 k) T 76.3/21.6
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R52 7030009290 S.RES ERJ2GEJ 562 X (5.6 k) T 67.7/16.9
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R62 7030005050 S.RES ERJ2GEJ 103 X (10 k) T 74/12.6
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R69 7030005040 S.RES ERJ2GEJ 472 X (4.7 k) B 87.9/16.1
R70 7030005530 S.RES ERJ2GEJ 100 X (10) B 80.2/24.9
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R72 7030005050 S.RES ERJ2GEJ 103 X (10 k) B 48.8/26.4
R75 7030005220 S.RES ERJ2GEJ 223 X (22 k) B 78.6/29.5
R76 7030005530 S.RES ERJ2GEJ 100 X (10) B 78.6/27.9
R77 7030004980 S.RES ERJ2GEJ 101 X (100) B 76.5/29.1