Icom IC-F80DS User manual
SERVICE
MANUAL
UHF TRANSCEIVERS
Icom, Icom Inc. and logo are registered trademarks of Icom Incorporated (Japan) in the United States, the United
Kingdom, Germany, France, Spain, Russia and/or other countries.
INTRODUCTION
This service manual describes the latest service information
for the IC-F80DT/DS and IC-F80T/S UHF TRANSCEIVERS
at the time of publication.
DANGER
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 7.2 V. Such a connection
could cause a fire or electric hazard.
DO NOT expose the transceiver to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when
connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100 mW)
to the antenna connector. This could damage the trans-
ceiver's front end.
ORDERING PARTS
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
1130010100 S.IC LMX2352TM IC-F80DS Main unit 5 pieces
8810010121 Screw
PH B0 M2×8 SUS SSBC
IC-F80DS Chassis 10 pieces
Addresses are provided on the inside back cover for your
convenience.
REPAIR NOTES
1. Make sure a problem is internal before disassembling the transceiver.
2. DO NOT open the transceiver until the transceiver is disconnected from its power source.
3. DO NOT force any of the variable components. Turn them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insulated turning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the transceiver is defective.
6. DO NOT transmit power into a signal generator or a sweep generator.
7. ALWAYS connect a 30 dB to 40 dB attenuator between the transceiver and a deviation meter or spectrum analyzer
when using such test equipment.
8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.
To upgrade quality, all electrical or mechanical parts and internal
circuits are subject to change without notice or obligation.
MODEL VERSION SYMBOL APCO25 10-KEYPAD
IC-F80DS
USA-02 [L] Compatible
No
USA-03 [H]
USA-04 [L] Not compatible
USA-05 [H]
IC-F80S USA-06 [L] FM only
USA-07 [H]
IC-F80DT
USA-02 [L] Compatible
Ye s
USA-03 [H]
USA-04 [L] Not compatible
USA-05 [H]
IC-F80T USA-06 [L] FM only
USA-07 [H]
IC-F80DS/S
TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 DISASSEMBLY INSTRUCTIONS
SECTION 4 CIRCUIT DESCRIPTION
4 - 1 RECEIVE CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 1
4 - 2 TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 3
4 - 3 PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 4
4 - 4 POWER SUPPLY CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 4
4 - 5 DIGITAL CIRCUIT (IC-F80DT/DS only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 5
4 - 6 PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 5
SECTION 5 ADJUSTMENT PROCEDURES
5 - 1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 - 1
5 - 2 SOFTWARE ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 - 4
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS AND DISASSEMBLY
SECTION 8 SEMICONDUCTOR INFORMATION
SECTION 9 BOARD LAYOUTS
9 - 1 FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 1
9 - 2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 3
9 - 3 FUSE BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 3
9 - 4 ANT BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 3
9 - 5 DSP UNIT (IC-F80DT/DS only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 5
9 - 6 VR BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 5
SECTION 10 BLOCK DIAGRAM
SECTION 11 VOLTAGE DIAGRAMS
11 - 1 FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 - 1
11 - 2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 - 2
11 - 3 DSP UNIT (IC-F80DT/DS only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 - 4
1 - 1
SECTION 1 SPECIFICATIONS
MGENERAL
• Frequency coverage : 400–470 MHz
450–520 MHz
• Type of emission : 11K0F3E/8K10F1E (Narrow)
16K0F3E (Wide)
• Number of conventional channels : 256 channels (Max.)
• Antenna impedance : 50 Ω(Nominal)
• Operating temperature range : −22°F to 140°F
• Power supply requirement : Specified Icom's battery pack only
(Operatable voltage; 7.2 V DC negative ground)
• Current drain (At 7.2 V DC ; approx.) :RECEIVING TRANSMITTING (at 4 W)
Stand-by Max.audio 2.4 A
150 mA 600 mA
• Dimensions (Projections not included) : 2 5/16 (W)× 5 31/32 (H)× 1 1/2(D) in
• Weight (Except anntena, battery pack) : 9 5/32 oz (Approx.)
MTRANSMITTER
• Output power (At 7.2 V DC) : 4 W
• Modulation : Variable reactance frequency modulation
• Maximum permissible deviation : ±2.5 kHz (Narrow)
±5.0 kHz (Wide)
• Frequency error : ±2.0 ppm
• Spurious emissions : 70 dB typ.
• Adjacent channel power : 60 dB (Narrow)
70 dB (Wide)
• Audio harmonic distortion : Less than 3%
• Limiting charactor of modulator : 60–100% of max. deviation
• FM hum and noise : 35 dB typ. (Narrow)
40 dB typ. (Wide)
• Audio frequency response : +2 dB to −8 dB of 6 dB/octave from 300 Hz to 2550 Hz (Narrow)
+2 dB to −8 dB of 6 dB/octave from 300 Hz to 3000 Hz (Wide)
• Microphone impedance : 600 Ω
MRECEIVER
• Receive system : Double conversion superheterodyne system
• Intermediate frequencies : 1st IF; 46.35 MHz, 2nd IF; 450 kHz
• Sensitivity : 0.32 µV typ. at 12 dB SINAD
• Squelch sensitivity (At threshold) : 0.32 µV typ.
• Adjacent channel selectivity : 68 dB (Narrow)
73 dB (Wide)
• Spurious response : 73 dB
• Intermodulation rejection ratio : 65 dB (Narrow)
73 dB (Wide)
• Hum and Noise : 35 dB (Narrow)
40 dB (Wide)
• Audio output power : 0.35 W typ. at 5% distortion with an 8 Ωload
• Output impedance (Audio) : 8 Ω
Specifications are measured in accordance with EIA-152-C/204D, TIA-603.
All stated specifications are subject to change without notice or obligation.
SECTION 2 INSIDE VIEWS
• FRONT UNIT
• MAIN UNIT
2 - 1
AF muting
(IC205: TC4S66F)
AF amplifier
(IC201: TA7368F)
Expander
(IC1, IC2: M62320FP)
3.0V regulator
(IC101: S-812C30AMC-C2K)
Mic switch
(IC204: TC4S66F)
Mic amplifier
(IC203: NJM12902V)
AF MUTE
Q209, Q210:
RSR025N03
AF mute switch
(IC205: TC4S66F)
AF amplifier
(IC201: TA7368F)
Expanders
(IC1, IC2: M62320FP)
3.0V regulator
(IC101: S-812C30AMC-C2K)
MIC switch
(IC204: TC4S66F)
MIC amplifier
(IC203: NJM12902V)
Microphone
(MC201: EM-140)
LCD
(DS2: M4-0078TAY-2)
TOP VIEW BOTTOM VIEW
Power amplifier
(Q13: RD07MVS1) APC amplifier
(IC5: TA75S01F)
RF amplifier
(Q18: 3SK293)
D/A converter
(IC310: M62334FP)
VCO circuit
D/A converter
(IC303: M62364FP)
DSP unit
[IC-F70DS/DT] only
Power amplifier
(Q203: RD07MVS1) APC amplifier
(IC200: TC75S51F)
RF amplifier
(Q502: 3SK293)
D/A converter
(IC310: M62334FP)
VCO circuit
AF volume
(IC303: M62364FP)
DSP unit
[IC-F80DT/DS] only
TOP VIEW BOTTOM VIEW
CPU5V regulator
(IC311: TK11250CM)
YGR amplifier
(Q11: 2SC5110-O)
PLL IC
(IC1: LMX2352TM)
IF IC
(IC3: TA31136FN)
Audio processor
(IC301: AK2346)
Digital/Analog switch
(IC302: BU4053BCFV)
CPU
(IC307: HD64F2268TF)
Decode IC
(IC300: LC73872M)
EEPROM
(IC308: HN58X24128FPI)
Antenna switch
(D203: 1SV307)
CPU5V regulator
(IC311: TK11250CM)
Pre-drive amplifier
(Q201: 2SC3357)
PLL IC
(IC1: LMX2352TM)
FM IF IC
(IC3: TA31136FN)
Audio processor
(IC301: AK2346)
Mic switch
(IC302: BU4053BCFV)
CPU
(IC307: HD64F2268TF)
Mixer
(IC500: SPM5001)
DTMF DECODE
(IC300: LC73872M)
EEPROM
(IC308: HN58X24128FPI)
Digital/Analog switch
(IC305: BU4053BCFV)
SECTION 3 DISASSEMBLY INSTRUCTIONS
• REMOVING THE CHASSIS UNIT
1Unscrew the ANT nut Aand remove the ANT washer B.
2Unscrew the screw C, and remove the rear panel Din
the direction of the arrow.
3Unscrew 4 screws Eand 2 screws F.
• REMOVING THE MAIN UNIT
1Disconnect the cable Hfrom J3.
2Remove the DSP unit from J2.
3Unsolder 13 points Iand remove the shield plate J.
4Unscrew 10 screws Kand remove the MAIN unit from the
CHASSIS.
• REMOVING THE FRONT UNIT
1Disconnect the speaker cable Lfrom J201.
2Disconnect the cable Mfrom J2.
3
Unscrew 5 screws Nand remove the FRONT unit from the
front panel.
3 - 1
5Disconnect the cable Gfrom J1 and remove the
CHASSIS
unit from the front panel.
C
E
E
E
A
B
D
F
*O-ring
* Be careful not to
lost the O-rings.
ANT
G
CHASSIS unit
Front panel
J1
K
K
K
K
J
J2
MAIN unit
DSP unit
J3
I
I
H
I
×2
×3
×8
L
J201
J2
FRONT unit
Front panel
M
N
4 - 1
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT (MAIN UNIT)
The antenna switching circuit toggles the receive line and
the transmit line. This circuit does not allow transmit signals
to enter the receiver circuits.
Received signals from the antenna connector (CHASSIS
UNIT; J1) are passed through a two-stage low-pass filter
(LPF; L522, L523, C565–C569) and applied to the λ/4type
antenna switching circuit (D203, D510).
While receiving, no voltage is applied to D203 and D510.
Thus, the receive line and the ground are disconnected and
L520 and C564 function as an LPF which leads received
signals to the RF circuits via the limiter (D509).
4-1-2 RF CIRCUITS (MAIN UNIT)
The RF circuits amplify received signals within the range of
frequency coverage and filters off out-of-band signals.
The signals from the antenna switching circuit are passed
through the two-stage tunable bandpass filters (BPF; D506,
D507, L516, L517, C551, C552, C554–C556) to suppress
unwanted signals. The filtered signals are amplified at the
RF amplifier (Q502).
The amplified signals are passed through another two-
stage tunable BPF (D502, D504, D505, L510, C520, C522,
C523, C527, C530, C536, C538) to suppress unwanted
signals again. The filtered signals are then applied to the
1st IF circuit.
4-1-3 1st IF CIRCUITS (MAIN UNIT)
The 1st IF circuits contain the 1st mixer, IF amplifier and
the 1st IF filter circuits, and the 1st IF mixer converts the
received signals into a fixed frequency of the 1st intermedi-
ate frequency (IF) signal. The converted 1st IF signal is fil-
tered at the 1st IF filter, then amplified at the 1st IF amplifier.
The signals from the two-stage tunable BPF are converted
into the 46.35 MHz 1st IF signal at the double-balanced
type 1st mixer (IC500, L503, L504, L506) by being mixed
with the 1st LO signal generated at the RX VCOs (Q600,
D604, D605 for 400–434 MHz, Q601, D606, D607 for 435–
470 MHz).
The 1st IF signal from the 1st mixer is passed through the
crystal filter (FI500) to suppress unwanted signals, and
then amplified at the 1st IF amplifier (Q500). The amplified
1st IF signal is applied to the FM IF IC (IC3, pin 16).
4-1-4 2nd IF AND FM DEMODULATOR CIRCUITS
(MAIN UNIT)
The 1st IF signal is converted into the 2nd IF signal and
demodulated at the detector section in the FM IF IC. The
FM IF IC contains 2nd mixer, limiter amplifier, quadrature
detector, etc. in its package.
The 1st IF signal from the 1st IF amplifier (Q500) is applied
to the mixer section in FM IF IC (IC3, pin 16). The applied
1st IF signal is mixed with the 45.9 MHz 2nd LO signal gen-
erated by tripling the 15.3 MHz PLL reference frequency to
be converted into the 450 kHz 2nd IF signal.
The 2nd IF signal from the mixer section is output from pin 3
and passed through the N/W switches (D13, D14) and a
ceramic filter (FI1 or FI2) to suppress the heterodyne noise.
The N/W switches (D13, D14) toggle the receive mode
wide and narrow according to “NWC” signal from the CPU
(IC307, pin 19). FI1 is used for wide, and FI2 is used for
narrow mode operation.
The filtered signal is applied to IC3 (pin 5) again, and
amplified at the limiter amplifier section and demodulated
by the quadrature detector.
The quadrature detector is a detection method which uses
a ceramic discriminator (X2).
Mixer
RSSI
Quadrature
detector
1st IF from the IF amplifier (Q500)
16
Noise
detector
5V
X2
1110
IC3
TA31136FN
Filter
amp.
Limiter
amp.
“DET” signal
to the D/A convertor (IC303; pin 1)
“SQL” signal
from the D/A convertor (IC303; pin 2)
• 2ND IF AND DEMODULATOR CIRCUITS
9
“NOIS” signal to the CPU (IC307: pin 37)
“RSSI” signal to the CPU (IC307: pin 50)
“DFIL” signal to the digital IF filter (FI1: DSP UNIT)
1312
Q14
X1
15.3 MHz
45.9 MHz BPF
2
3
Q303
D-IF
8735
FI2
FI1
N/W
SW
N/W
SW
D14 D13
4 - 2
The demodulated AF signals are output from pin 9, and
applied to the AF cricuits.
4-1-5 AF CIRCUITS (MAIN AND FRONT UNITS)
The demodulated AF signals from the FM IF IC are ampli-
fied and filtered at AF circuit. This transceiver employs the
base band IC for audio signal processing for both transmit
and receive. The base band IC is an audio processor and
composed of pre-amplifier, compressor, expander, scram-
bler, etc. in its package.
The AF signals from FM IF IC (IC3, pin 9) are applied to the
base band IC (IC301, pin 23) via the digital/analog switch
(IC302, pins 12, 14).
The applied AF signals are amplified at the amplifier section
and level adjusted at the volume control section, and then
suppressed unwanted 3 kHz and higher audio signals at
LPF section. The filtered AF signals are applied or bypassed
the TX/RX HPF, de-scrambler, de-emphasis and expander
sections in sequence, then applied to another volume con-
troller.
The TX/RX HPF filters out 250 Hz and lower audio signals,
and the de-emphasis obtains –6 dB/oct of audio character-
istics. The expander expands the compressed audio signals
and also noise reduction function is provided.
The AF signals are level adjusted at the volume controller
and amplified at the amplifier section. The amplified AF sig-
nals are output from pin 20 and applied to the D/A coverter
(IC303, pin 16) to be adjusted its level. The level adjusted
AF signals are then output from pin pin 15, and then applied
to the FRONT UNIT via J3 (pin 28).
The level controlled AF signals from the MAIN UNIT are
passed through the mute switch (FRONT UNIT; IC205,
pins 1, 2) and applied to the AF power amplifier (FRONT
UNIT; IC201, pin 4) to obtain 350 mW of AF output power.
The power amplified AF signals are applied to the internal
speaker (CHASSIS UNIT; SP1).
4-1-6 SQUELCH CIRCUITS (MAIN AND FRONT UNITS)
• NOISE SQUELCH
Noise squelch circuit mutes AF output signals when no RF
signals are received. By detecting noise components in the
demodulated AF signals, the squelch circuit switches the
AF mute swithch and AF power amplifier controller ON and
OFF.
A portion of the demodulated AF signals from the FM IF IC
(IC3, pin 9) are applied to the converter (IC303, pin 1) to
be adjusted its level. The level controlled signals are output
from pin 2 and applied to the active filter (IC3, pins 7, 8;
R74, R75, R77, R78, C137–C139). The filtered signals are
applied to the filter amplifier section to amplify the noise
components only.
The amplified noise components are converted into the
pulse-type signal at the noise detector section, and output
from pin 13 as the “NOIS” signal and applied to the CPU
(IC307, pin 37). Then the CPU outputs “AFON” signal from
pin 18 according to the “NOIS” signal level to toggle the AF
mute circuit (FRONT UNIT; IC205) and AF amplifier control-
ler (FRONT UNIT; Q202, Q203) ON/OFF.
• CTCSS AND DTCS
The tone squelch circuit detects tone signals and opens the
squelch only when receiving a signal containing a matched
sub audible tone (CTCSS or DTCS). When the tone squelch
is in use, and a signal with a mismatched or no sub audible
tone is received, the tone squelch circuit mutes the AF sig-
nals even when the noise squelch is open.
A portion of the demodulated AF signals from the FM IF
IC are passed through the LPF (IC2, pins 12, 14) to filter
CTCSS/DTCS signal. The filtered signal is applied to the
CPU (IC307, pin 46) after being amplified at the buffer
amplifier (IC2, pins 1, 3).
The CPU compares the applied signal and the set CTCSS/
DTCS, then output the "AFON" signal to the AF mute switch
(FRONT UNIT; IC205) and AF amplifier controller (FRONT
UNIT; Q202, Q203) control signal from pin 18.
Scrambler/
De-scrambler
TX/RX
HPF
Pre-
emphasis Limiter Splatter VR2
Expander VR4
RXA2
SMF
De-
emphasis
Com-
pressor
VR1
(HPF)
RX
LPF
VR3
(HPF)
7 MOD
18
19
20 SIGNAL
3TXIN
• BASE BAND IC BLOCK DIAGRAM
23RXIN
21SDEC
10
14MDIR
9
MTDT
MTCK
13MSCK
11MDIO
12MRDF
MSK
Modulator
MSK
Demodulator
MSK
BPF
Control
Register
TXA1
RXA1
IC301 AK2346
4 - 3
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT
(FRONT AND MAIN UNITS)
The microphone amplifier circuit amplifies the audio signals
from microphone within +6 dB/oct pre-emphasis characteris-
tic. The microphone signals are processed in the base band
IC which contains microphone amplifier, compressor, scram-
bler, limiter, splatter filter, etc. in its package.
The audio signals from the microphone (FRONT UNIT;
MC201) are passed through the microphone mute switch
(FRONT UNIT; IC204 pins 1, 2). The switched signals are
amplified at the microphone amplifiers (FRONT UNIT;
IC203, pins 1, 2, 13, 14) to obtain within +6 dB/oct pre-
emphasis characteristics. The amplified signals are applied
to the MAIN UNIT via J1 (pin 2).
The amplified MIC signals from the FRONT UNIT are
applied to the base band IC (IC301, pin 3). The applied
MIC signals are amplified at the amplifier section, and level
adjusted at the volume control section. The level adjusted
MIC signals are applied or bypassed the compressor, pre-
emphasis, TX/RX HPF, scrambler, limiter and splatter sec-
tions in sequence, then applied to another volume controller.
The compressor compresses the MIC signals to provide
high S/N ratio for receive side, and the pre-emphasis obtains
+6 dB/oct audio characteristics. The TX/RX HPF filters out
250 Hz and lower audio signals, the limiter limits its level
and the splatter filters out 3 kHz and higher audio signals.
The filtered MIC signals are level adjusted at another vol-
ume control section and amplified at the amplifier section,
and then output from pin 7 via smoothing section (SMF).
4-2-2 MODULATION CIRCUIT (MAIN UNIT)
The modulation circuit modulates the VCO oscillating signal
with the audio signals from the microphone.
MIC signals from the base band IC (IC301) are passed
through the MIC switch (IC302, pins 4, 5), PM filter (C338,
R327), FM/PM switch (IC302, pins 1, 15), and then applied
to the AF mixer (IC12, pin 2) to be mixed with CTCSS/DTCS
signals.
The mixed MIC signals are output from pin 1 and then
applied to the D/A converter (IC303, pin 4) to be adjusted
its level. The level adjusted AF signals are output from pin 3
and applied to the modulation circuit (D611) to modulate the
VCO oscillating signal by changing the reactance of D611 at
the TX VCO (Q602, D608, D609).
The CTCSS/DTCS signals are generated by the CPU (IC307)
and output from pins 89–91 (“CENC0,” “CENC1,” ”CENC2”).
The CTCSS/DTCS signals are passed through 3 regis-
ters (R374–R376) to change its wave form. The wave form
changed CTCSS/DTCS signals are then passed through the
LPF (IC12, pins 8, 10) and applied to the converter (IC303,
pin 9) to be adjusted its level, and output from pin 10.
The level adjusted CTCSS/DTCS signals are applied to
the AF mixer (IC12, pin 2) to be mixed with MIC signals.
The mixed CTCSS/DTCS signals are output from pin 1 and
applied to the D/A converter (IC303, pin 4) to be adjusted
its level again, then output from pin 3. The CTCSS/DTCS
signals from the D/A converter are applied to the both of
reference frequency oscillator (X1) and modulation circuit
(D611) to modulate the reference frequency signal and VCO
oscillating signal.
The modulated VCO output signal is amplified at the buffer
amplifiers (Q605, Q606, Q609) and is then applied to the
pre-drive amplifier (Q201) via the TX/RX switch (D200).
4-2-3 TRANSMIT AMPLIFIERS (MAIN UNIT)
The VCO output signal is amplified to transmit output power
level by the transmit amplifiers .
The buffer-amplified signal from the TX/RX switch (D200)
is applied to the pre-drive (Q201), drive (Q202), and power
(Q203) amplifiers to be amplified to the transmit output power
level.The power amplified transmit signal is passed through
the power detector (D202, D204), antenna switch (D203),
and two-stage LPFs (L522, L523, C565–C569), and then
applied to the antenna connector (CHASSIS UNIT; J1).
4-2-4 APC CIRCUIT (MAIN UNIT)
The APC (Automatic Power Control) circuit stabilizes trans-
mit output power and controls transmit output power High or
Low.
The power detector circuits (D202, D204) detect the transmit
output signal level and converts it into DC voltage.
The detected voltage is applied to the APC amplifier (IC200,
pin 3). The “T2” signal from the D/A converter (IC310, pin
2), controlled by the CPU (IC307), is applied to the another
input (pin 1) for reference, and the "T2" signal also controls
transmit output power (4 W, 2 W or 1 W).
The output voltage from the APC amplifier controls the bias
of the drive amplifier (Q202) and power amplifier (Q203) to
control the output power by comparing the detected voltage
and the reference voltage. Thus the APC circuit maintains a
constant transmit output power.
Power
amp.
APC
amp.
Drive
amp.
+
–
VCC
• APC CIRCUIT
to the anntena
T2
TMUT
TMUT
from TX/RX switch
(D200, D501)
T5V
Q202
Buffer
amp. Pre-drive
amp.
Q201Q200
IC200
Q203
LPF ANT
SW
Q204
D205
D202
Power detector
D204
D203
4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT (MAIN UNIT)
The PLL circuit provides stable oscillation of the transmit
frequency and receive 1st LO frequency. The PLL circuit
compares the phase of the divided VCO frequency with the
reference frequency. The PLL output frequency is controlled
by the divided ratio (N-data) of the programmable divider.
The PLL circuit contains the two RX VCOs (Q600, D604,
D605 for 400–434 MHz, Q601, D606, D607 for 435–470
MHz) and one TX VCO (Q602, D608, D609). The oscillated
signal is amplified at the buffer amplifiers (Q605, Q606,
Q608) and applied to the PLL IC (IC1, pin 6) after being
passed through the LPF (L2, L3, C22, C25, C27, C28, C37).
The applied signal is divided at the prescaler and program-
mable divider section by the N-data ratio from the CPU
(IC307). The divided signal is phase-compared with the devided
reference frequency at the phase detector. The phase dif-
ference is output from pin 4 as a pulse signal after being
passed through the charge pump section. The output signal
is passed through the loop filter (R16, R17, C17, C24, C29,
C31) to converted into the DC voltage, and is then applied
to the VCO circuits as the lock voltage.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
4-3-2 VCO CIRCUITS (MAIN UNIT)
The VCO circuits contain separate two RX VCOs (Q600, D604,
D605 for 400–434 MHz, Q601, D606, D607 for 435–470
MHz) and one TX VCO (Q602, D608, D609). The oscillated
signal is amplified at the buffer amplifiers (Q605, Q606,
Q609) and is then applied to the TX/RX switch (D200,
D501). Then the receive 1st LO (RX) signal is applied to the
1st mixer (IC500, L503, L504, L506), and the transmit (TX)
signal is applied to the buffer amplifier (Q200).
A portion of the signal from the buffer amplifier (Q605,
Q606) is fed back to the PLL IC (IC1, pin 6) as the compari-
son signal via the buffer amplifier (Q608) and the LPF (L2,
L3, C22, C25, C27, C28, C37).
4 - 4
Loop
filter
PLST
SSO
SCK
4
Q601, D606, D607
RX VCO (435–470 MHz)
Q600, D604, D605
RX VCO (400–434 MHz)
TX VCO
Q602, D608, 609
6
10
14
15
16 PLL control signals from CPU (IC307)
15.3 MHz reference signal
from reference frequency osciilator (X1)
IC1 LMX2352TM
• PLL CIRCUIT
Shift register
Prescaler
Phase
detector
Divided
ratio
adjustment
Charge
pump
Programmable
divider
Reference
divider
Buffer
Q605,
Q606
Buffer
Q609
Buffer
Q608
to transmitter circuit
to 1st mixer circuit
D501
D200
LPF
LINE DESCRIPTION
VCC The voltage from the attached battery pack passed
through the power switch (Q309).
CPU5V Common 5 V for the CPU (IC307) converted from the
VCC line at the CPU5V regulator (IC311).
5V Common 5 V line converted from the VCC line at the
+5V regulator (Q307, Q308).
T5V
5 V for the transmit circuits regulated from the 5V line
by the T5V switch (Q305).
The switch is controlled by the "T5C" signal from the
CPU (IC307, pin 16).
S5V
5 V for the power save line regulated from the 5V line
by the S5V switch (Q304).
The switch is controlled by the "S5C" signal from the
CPU (IC307, pin 27).
R5V
5 V for the receive circuits regulated from the 5V line
by the R5V switch (Q306).
The regulator is controlled by the "R5C" signal from
the CPU (IC307, pin 26).
4-4 POWER SUPPLY CIRCUITS
4-4-1 VOLTAGE LINES (MAIN UNIT)
LINE DESCRIPTION
DVDD3.3V
3.3 V for the CPU (IC12; DSP UNIT), DSP IC (IC7)
and EEPROM (IC17) regulated from the 5V line by the
+3VC regulator (IC1).
CVDD1.5V 1.5 V for the DSP IC (IC7) converted from the +5V
line at the +1.5VA regulator (IC2).
+3VD 3.3 V for the A/D converter (IC8) and LINER CODEC
IC (IC9) from the 5V line at the +3VD regulator (IC3).
4-4-2 VOLTAGE LINES (DSP UNIT)
4 - 5
BPF
From FM IF IC
(IC3, pin 11) To AF volume
From
MIC amplifier
(IC203; FRONT UNIT)
To FM/PM SW
(IC302, pin 5)
• DIGITAL MODE BLOCK DIAGRAM
DSP UNIT
AMP AMP
Q303
IC302
RECEIVED SIGNAL
FI1 IC5 IC8
IC7
IC9
IC9IC4
IC302
IC301
A/D LINER
CODEC
IC
LINER
CODEC
IC
BASE
BAND
IC
DIG/ANA
SW
DSP
IC
MIC SW LPF
TRANSMIT SIGNAL
The 2nd IF signal from the MAIN UNIT is passed through
the ceramic BPF (DSP UNIT; FI1) to suppress heterodyne
noise, and amplified again at the digital IF amplifier (DSP
UNIT; IC5, pin 4). The amplified 2nd IF signal is applied to
the A/D converter (DSP UNIT; IC8, pin 3) to be converted
into digital IF data, then applied to the DSP IC (DSP UNIT;
IC7). The DSP IC converts the digital IF into the digital audio
signal.
The digital audio signal from the DSP IC are converted into
analog audio signals at the LINER CODEC IC (IC9) and out-
put from pin 16. The audio signals from the LINER CODEC
IC are applied to the MAIN UNIT via J1 (pin 22).
The audio signals from the DSP UNIT are applied to the
base band IC (MAIN UNIT; IC301, pin 20) after being
passed through the digital/analog switch (MAIN UNIT; IC302 ).
• WHILE TRANSMITTING
The microphone signals from the base band IC (IC301, pin 7)
are applied to the DSP UNIT via J2 (pin 4).
The microphone signals from the MAIN UNIT are applied
to the LINER CODEC IC (DSP UNIT; IC9, pin 2) to convert
into the digital audio signal.
The converted digital audio signal is processed by the DSP
IC (DSP UNIT; IC7), and applied to the LINER CODEC IC
(DSP UNIT; IC9) again. The signal from the LINER CODEC
IC (IC9, pin 15) is passed through the LPFs (DSP UNIT;
IC4, pins 3, 4, 5, 7) and applied to the MAIN UNIT via J1,
and then passed through the microphone switch (MAIN
UNIT; IC302, pins 3, 4), FM filter (R328, C335), FM/PM
switch (IC302, pins 2, 15).
4-6 PORT ALLOCATIONS
4-6-1 CPU (IC307)
Pin
number
Port
name Description
4–7 R1, R2,
R4, R8
Input ports for rotary selector (VR
UNIT; S1).
10 SSO Outputs serial data to the PLL IC (IC1,
pin 15) and D/A converter (IC303, pin 8).
11 SCK Outputs clock signal to the PLL IC (IC1 pin
14) and D/A converter (IC303, pin 7), etc.
13 PLST Outputs strobe signals to the PLL IC
(IC1, pin 16).
15 DASW
Outputs control signal to the digital
/analog switch (IC302).
Low: While analog mode is selected.
16 TXC
Outputs the T5V switch (Q305) con-
trol signal.
Low: During transmit.
17 TMUT
• Outputs the APC amplifier (IC200)
control signal.
• Outputs the TX switch (Q204, D205)
control signal.
Low: During receive.
18 AFON
Outputs control signal for AF mute
circuit (FRONT UNIT; IC205) and AF
power amplifier (FRONT UNIT; IC201).
High: AF amplifier (IC201) is activated.
19 NWC
Outputs wide/narrow switch (D13,
D14) control signal.
High: When narrow mode is selected.
Pin
number
Port
name Description
20 DDSD Input port for serial data from the
DTMF decoder IC (IC300, pin 9).
21 DDAC Outputs clock signals to the DTMF
decoder IC (IC300, pin 10).
26 R5C Outputs R5V switch (Q306) control signal.
High:While receiving.
27 S5C
Outputs S5V switch (Q304) control
signal.
High:In power save mode..
29 PTTO Input port for optional unit.
Low: Switch ON.
30 EM
Input port for the emegency switch
(FRONT UNIT; S117).
Low: While emegency switch is
pushed.
32 RMUT
Input port for the AF mute signal from
the optional unit via J1 or J2.
Low: While RX audio is muted.
33 MMUT
Input port for the microphone mute sig-
nal from the optional unit via J1 or J2.
Low: While microphone audio is
muted.
34–36 OPT1–
OPT3
I/O ports for the connected optional
unit to J1.
37 NOIS Input port for the noise signal from
the FM IF IC (IC3, pin 13).
4-5 DIGITAL CIRCUIT (IC-F80DT/DS only)
• WHILE RECEIVING
A portion of the 2nd IF sigal from the limiter amplifier section
in the FM IF IC (IC3) is output from pin 11 and is applied to
the 2nd IF amplifier (Q303). The amplified 2nd IF signal is
applied to the DSP UNIT via J2 (pin 11).
4 - 6
Pin
number
Port
name Description
38 PWRSW
Input port for the [VOL] control (VR
UNIT; R1).
Low: While power is ON.
39 DDST
Input port for the decodedDTMF sig-
nals from the DTMF decoder IC (IC300,
pin 11).
40 CIRQ
Inputs offering signal from the optional
unit and DSP unit.
Low: Offering signal is output.
41 PWRO
Outputs control signal for the power
switch circuit (Q309, Q310).
High: Power ON.
43 SENC Outputs single tone encode signal.
44 BEEP Outputs beep audio signals.
45 SDEC
Input port for single tone decode sig-
nal from the base band IC (IC301,
pin 1).
46 CDEC Input port for CTCSS/DTCS signal
from the LPF (IC12, pin 7).
47 ULCK Input port for the PLL unlock signal.
Low: The PLL circuit is unlocked.
48 BATV
Input port for the connected battery pack
for the low battery voltage detection.
Low: The battery voltage is low.
49 LVIN Input port for the PLL lock voltage.
50 RSSI Input port for the "RSSI" signal from
the FM IF IC (IC3, pin 12).
51 TEMP/
OPTV
• Input port for the transceiver’s internal
temperature detecting signal.
High: Internal temperature is high.
• Input port for the optional unit detecting
signal.
High: While connecting optional unit
to the multiconnector.
55 SIDE1 Input port for [UP] switch (MAIN UNIT; S1).
Low: While [UP] switch is pushed.
68 DAST Outputs strobe signals to the D/A
converter (IC303, pin 6).
69 DSDA I/O port for data signal to the D/A con-
verter (IC310, pin 6).
72 SPCON Outputs "SPCON" signal.
Low: Audio output.
78 MTCK
Input port for transmitting MSK clock
signal from the base band IC (IC301,
pin 9).
79 KR
Input port for key matrix.
Low: While any of key on the 10-keypad
(including [P0]–[P3]) is pushed.
80 FSDA I/O port for the serial data signal for
the expander (FRONT UNIT; IC2).
81 FSCL Outputs clock signal to the expander
(FRONT UNIT; IC2).
88 SIDE2
Input port for [DOWN] switch (MAIN UNIT;
S2).
Low: While [DOWN] switch is pushed.
89–91 CENC0–
CENC2 Output the CTCSS/DTCS signals.
Pin
number
Port
name Description
92 SIDE3
Input port for [MONITOR] switch (MAIN
UNIT; S4).
Low: While [MONITOR] switch is pushed.
93 MTDT Outputs the MSK data to the base
band IC (IC301, pin 10).
94 MDIR Outputs serial data control signal to
the base band IC (IC301, pin 14 ).
95 MDIO
I/O port for the serial data signals
from/to the base band IC (IC301,
pin 11).
96 MSCK Outputs clock signal for the base
band IC (IC301, pin 13).
97 PMFM
Outputs the the FM/PM switch (IC302,
pin 11) control signal.
High:While PM is selected.
98 ESDA I/O port for data signals from/to the
EEPROM (IC308, pin 5).
99 ESCL Outputs clock signal to the EEPROM
(IC308, pin 6).
100 CODE8 Output port for "CODE8" signal.
4-6-2 D/A CONVERTER (MAIN UNIT; IC303)
Pin
number
Port
name Description
2 SQL Outputs AF signals to the squelch cir-
cuit (IC3, pin 8).
3 MOD Outputs modulation signals to the
modulation circuit (D8).
10 TENC Outputs CTCSS/DTCS signals.
11 BAL Outputs deviation balance control signal.
14 BEPV
Outputs beep audio signals to the
speaker via the AF amplifier (FRONT
UNIT; IC201).
15 SIGNAL Outputs AF signals to the speaker via
the AF amplifiers (FRONT UNIT; IC201).
22 TONE Outputs single tone signal.
23 REF Outputs reference oscillator control signal.
4-6-3 D/A CONVERTER (MAIN UNIT; IC310)
Pin
number
Port
name Description
1T1
Outputs the bandpass filters (D18,
D19) tuning signal.
2T2
• While receiving:
Outputs the bandpass filters (D15, D16)
tuning signal.
• While transmitting:
Outputs the TX power control signal
which selects TX output power of HIGH
or LOW. The output signal is applied to
the ALC amplifier (IC5, pin 1).
3 TXLVA Outputs TX VCO lock voltage.
4 RXLVA Outputs RX VCO lock voltage.
4-6-1 CPU (continued)
▄ REQUIRED TEST EQUIPMENTS
EQUIPMENT GRADE AND RANGE EQUIPMENT GRADE AND RANGE
DC power supply Output voltage
Current capacity
: 7.2 V DC
: 3 A or more Audio generator Frequency range
Measuring range
: 300–3000 Hz
: 1–500 mV
FM deviation meter Frequency range
Measuring range
: DC–600 MHz
: 0 to ±10 kHz Attenuator Power attenuation
Capacity
: 50 or 60 dB
: 10 W
Frequency counter
Frequency range
Frequency accuracy
Sensitivity
: 0.1–600 MHz
: ±1 ppm or better
: 100 mV or better
Standard signal
generator (SSG)
Frequency range
Output level
: 0.1–600 MHz
: 0.1 µV to 32 mV
(–127 to –17 dBm)
Digital multimeter Input impedance : 10 MΩ/V DC or more AC millivoltmeter Measuring range : 10 mV to 10 V
RF power meter
Measuring range
Frequency range
Impedance
SWR
: 1–10 W
: 100–600 MHz
: 50 Ω
: Better than 1.2 : 1
Oscilloscope Frequency rang
Measuring range
: DC–20 MHz
: 0.01–20 V
External speaker Input impedance
Capacity
: 8 Ω
: 1 W or more
SECTION 5 ADJUSTMENT PROCEDURES
5 - 1
5-1 PREPARATION
When adjusting IC-F80DT/DS/D/S, the optional CS-F70/F1700 ADJ ADJUSTMENT SOFTWARE (Rev. 1.1 or later), OPC-966 JIG
CABLE (modified OPC-966 CLONING CABLE; see illustration page 5-2) are required.
▄SYSTEM REQUIREMENTS
• Microsoft®Windows®98/98SE/Me/2000/XP
• RS-232C serial port (D-sub 9 pin)
▄ ADJUSTMENYT SOFTWARE INSTALLATION
qQuit all applications when Windows is running.
wInsert the CD into the appropriate CD drive.
eDouble-click the “Setup.exe” contained in the ‘CS-F70/
F1700 ADJ’ folder in the CD drive.
rThe “Welcome to the InstallShield Wizard for CS-F70/
F1700 ADJ” will appear. Click [Next>].
tThe “Choose Destination Location” will appear. Then click
[Next>] to install the software to the destination folder. (e.g.
C:\Program Files\Icom\CS-F70/F1700 ADJ)
y
After the installation is completed, the “InstallShield Wiz-
ard Complete” will appear. Then click [Finish].
uEject the CD.
iProgram group ‘CS-F70/F1700 ADJ’ appears in the ‘Pro-
grams’ folder of the start menu, and ‘CS-F70/F1700 ADJ’
icon appears on the desk top screen.
▄ BEFORE STARTING SOFTWARE ADJUSTMENT
Clone the adjustment frequencies into the transceiver, and-
set the configuration using with the CS-F70/F1700 CLONING
SOFTWARE before starting the software adjustment. Other-
wise, the transceiver can not start software adjustment.
CAUTION!: BACK UP the originally programmed mem-
ory data in the transceiver before program-
ming the adjustment frequencies.
When program the adjustment frequencies into
the transceiver, the transceiver’s memory data
will be overwritten and lose original memory
data at the same time.
Microsoft and Windows are registered trademarks of
Microsoft Corporation in the U.S.A. and other countries.
▄STARTING SOFTWARE ADJUSTMENT
qConnect the transceiver and PC with OPC-966 JIG CABLE.
wTurn the transceiver power ON.
eBoot up Windows, and click the program group ‘CS-F70/
F1700 ADJ’ in the ‘Programs’ folder of the [Start] menu,
then CS-F70/F1700 ADJ’s window appears.
rClick ‘Connect’ on the CS-F70/F1700 ADJ’s window, then
appears transceiver’s up-to-date condition.
tSet or modify adjustment data as desired.
• ADJUSTMENT FREQUENCY LIST
CH FREQUENCY (MHz) ADJUSTMENT ITEM
[L] [H]
1 400.000 450.000 TX power
Mode : Low1
: Narrow
2 435.000 485.000 TX power
Mode : Low1
: Narrow
3 470.000 520.000 TX power
Mode : Low1
: Narrow
4 435.000 485.000 TX power
Mode : Low1
: Wide
5 400.000 450.000 TX power
Mode : Low1
: Wide
6 435.000 485.000 TX power
Mode : High
: Wide
7 435.000 485.000 TX power
Mode : Low2
: Wide
8 470.000 520.000 TX power
Mode : Low1
: Wide
9* 435.000 485.000 TX power
Mode
Preamble Length†
: Low1
: Digital
: 270
10* 400.000 450.000 TX power
Mode
Preamble Length†
: Low1
: Digital
: 270
11* 470.000 520.000 TX power
Mode
Preamble Length†
: Low1
: Digital
: 270
12 435.000 485.000
TX power
Mode
CTCSS
DTCS
: Low1
: Wide
: 151.4 Hz
: 007
†; [USA-02], [USA-03], [USA-21], [USA-22] only
*; IC-F80DT/DS only
3).!$METER
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&-
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5 - 2
• CONNECTION
!DDAJUMPERWIREHERE
%LECTROLYTICCAPACITOR
§&
/0#
#LONINGCABLE
!UDIOGENERATOR
(ZTOK(Z
!#
MILLIVOLTMETER
044
044%
-)#
-)#%
30n
30
n
• JIG cable
5 - 3
• PC SCREEN EXAMPLE
r
t
y
e
u
q
w
i
!0
!2
@5
@6 @7
!5
!6
!7
o
!8 !9
@1
@0
@2
@3
@4
!1
!3
!4
q: Reload adjustment data
w: Transceiver's connection state
e: Connected DC voltage measurement
r: PLL lock voltage measurement
t: RF output power
y: FM modulation balance
u: FM modulation preset
i: CTCSS/DTCS deviation
o: Squelch level
!0: Reference frequency
!1: Receive sensitivity for center (automatic)
!2: Receive sensitivity for center (manual)
!3: Receive sensitivity for low edge (automatic)
!4: Receive sensitivity for low edge (manual)
!5: Receive sensitivity for high edge (automatic)
!6: Receive sensitivity for high edge (manual)
!7: PLL lock voltage preset for RX (automatic)
!8: PLL lock voltage preset for TX (automatic)
!9: S-meter (FM)
@0: S-meter (digital)
@1: Deviation (narrow)
@2: Deviation (wide)
@3: Deviation (digital)
@4: DSP reference frequency
@5: Base band center voltage
@6: Digital mode
@7: 2/5 TONE, DTMF deviation
NOTE: The above values for settings are example only.
Each transceiver has its own specific values for each setting.
5 - 4
5-2 SOFT WARE ADJUSTMENT
Select an operation using [↑] / [↓] keys, then set specified value using [←] / [→] keys on the connected computer keyboard
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT OPERATION
PLL LOCK
VOLTAGE
1 • Operating CH.
• Receiving
: CH 1 PC
screen
Click [Reload (F5)] button, then
check the "LVIN" item on the
CS-F70/F1700 ADJ's screen.
0.75–1.45 V
(Verify)
2 • Operating CH.
• Receiving
: CH 2 0.55–1.35 V
(Verify)
3 • Operating CH. : CH 3 0.55–1.15 V
(Verify)
• Connect an RF power meter or 50 Ω
dummy load to the antenna connector.
• Transmitting
REFERENCE
FREQUENCY
[REF]
• Operating CH. : CH 3 Top
panel
Loosely couple a frequency
counter to the antenna connec-
tor.
470.000000 MHz [L]
520.000000 MHz [H]
±100 Hz
• Connect an RF power meter or 50 Ω
dummy load to the antenna connector.
• Transmitting
DSP
REFERENCE
FREQUENCY*
[Dig REF]
• Operating CH. : CH 8 DSP
unit
Connect a frequency counter
to the pin 4 of IC13 on the DSP
unit through a 1000 pF capacitor.
(see the illust below)
12.288000 MHz
• Receiving
BASE BAND
CENTER
VOLTAGE*
[Dig DA]
• Operating CH.
• Receiving
: CH 8 PC
screen
Set the "Dig DA" item to 70.
*; IC-F80DT/DS only
DSP REFERENCE FREQUENCY
CHECK POINT (IC-13, pin 4)
DSP UNIT
MAIN UNIT
5 - 5
SOFTWARE ADJUSTMENT (Continued)
Select an operation using [↑] / [↓] keys, then set specified value using [←] / [→] keys on the connected computer keyboard
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT OPERATION
OUTPUT
POWER
[Power (Hi)]
1 • Operating CH.
• Transmitting
: CH 6 Top
panel
Connect an RF power meter to
the antenna connector.
4.0 W
[Power (L2)] 2 • Operating CH.
• Transmitting
: CH 7 2.0 W
[Power (L1)] 3 • Operating CH.
• Transmitting
: CH 2 1.0 W
MODULATION
BALANCE
[BAL]
1 • Operating CH.
• Preset [MOD N]
: CH 4
: 30
Top
panel
Connect an FM deviation meter
with an oscilloscope to the
antenna connector through an
attenuator.
Set to square wave
form
• No audio applied to the JIG cable.
• Set an FM deviation meter as;
HPF
LPF
De-emphasis
Detector
: OFF
: 20 kHz
: OFF
: (P–P)/2
• Push [P0] while transmitting.
FM
DEVIATION
(NARROW)
[MOD N C]
1• Operating CH. : CH 2 Top
panel
Connect an FM deviation meter to
the antenna connector through
an attenuator.
±2.00 to ±2.10 kHz
• Connect an audio generator to the JIG
cable and set as;
: 1.0 kHz/150 mV rms
• Set an FM deviation meter as;
HPF
LPF
De- emphasis
Detector
• Transmitting
: OFF
: 20 kHz
: OFF
: (P–P)/2
(NARROW)
[MOD N L]
2• Operating CH.
• Transmitting
: CH 1
(NARROW)
[MOD N H]
3• Operating CH.
• Transmitting
: CH 3
(WIDE)
[MOD W C]
4• Operating CH.
• Transmitting
: CH 4 ±4.00 to ±4.20 kHz
(WIDE)
[MOD W L]
5• Operating CH.
• Transmitting
: CH 5
(WIDE)
[MOD W H]
6• Operating CH.
• Transmitting
: CH 8
5 - 6
SOFTWARE ADJUSTMENT (Continued)
Select an operation using [↑] / [↓] keys, then set specified value using [←] / [→] keys on the connected computer keyboard
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT OPERATION
DIGITAL
DEVIATION*
[MOD Dig C]
1• Preset [Dig Mode] : 7 Top
panel
Connect an FM deviation meter to
the antenna connector through
an attenuator.
±2.80 to ±2.90 kHz
2• Operating CH. : CH 9
• Set an FM deviation meter as;
HPF
LPF
De- emphasis
Detector
• Transmitting
: OFF
: 20 kHz
: OFF
: (P–P)/2
[MOD Dig L] 3 • Operating CH.
• Transmitting
: CH 10
[MOD Dig H] 4 • Operating CH.
• Transmitting
: CH 11
DIGITAL
DEVIATION*
[MOD Dig C]
1• Preset [Dig Mode] : 6 Top
panel
Connect an FM deviation meter to
the antenna connector through
an attenuator.
±0.91 to ±1.01 kHz
(Verify)
2• Operating CH.
• Transmitting
: CH 9
[MOD Dig L] 3 • Operating CH.
• Transmitting
: CH 10
[MOD Dig H] 4 • Operating CH.
• Transmitting
: CH 11
CTCSS/DTCS
DEVIATION
[CTCSS/DTCS]
1• Operating CH. : CH 12 Top
panel
Connect an FM deviation meter to
the antenna connector through
an attenuator.
±0.60 to ±0.70 kHz
• No audio applied to the JIG cable.
• Set an FM deviation meter as;
HPF
LPF
De- emphasis
Detector
• Transmitting
: OFF
: 20 kHz
: OFF
: (P–P)/2
2/5 TONE
/DTMF
DEVIATION
[S.Tone]
1• Operating CH. : CH 2 Top
panel
Connect an FM deviation meter to
the antenna connector through
an attenuator.
±1.50 kHz
• No audio applied to the JIG cable.
• Set an FM deviation meter as;
HPF
LPF
De- emphasis
Detector
: OFF
: 20 kHz
: OFF
: (P–P)/2
• Push [P3] while transmitting.
*; [IC-F80DT/DS] only
5 - 7
SOFTWARE ADJUSTMENT (continued)
• Select an operation using [↑] / [↓]keys, then set specified value using [←] / [→] keys on the connected computer keyboard
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT LOCATION
RX
SENSITIVITY
[BPF T1],
[BPF T2]
NOTE:
Need to adjust "S-METER ADJUSTMENT" after "RX SENSITIVITY ADJUSTMENT" is adjusted.
Otherwise, "S-METER ADJUSTMENT" will not be adjusted properly.
1• Operating CH : CH 4 PC
screen
Connect the SINAD meter with
an 8 Ωload to the JIG cable.
Minimum distortion
level
• Connect the SSG to the antenna connec-
tor and set as;
Frequency
Level
Modulation
Deviation
• Receiving
: 435.000 MHz [L]
485.000 MHz [H]
: +20 dBµ†(–87 dBm)
: 1 kHz
: ±3.0 kHz
[BPF T1 L],
[BPF T2 L]
2• Operating CH
Frequency
• Receiving
: CH 5
: 400.000 MHz [L]
450.000 MHz [H]
[BPF T1 H],
[BPF T2 H]
3• Operating CH
Frequency
• Receiving
: CH 8
: 470.000 MHz [L]
520.000 MHz [H]
CONVENIENT:
The BPF C/L/H can be adjustment automatically.
q-1: Put the cursor on "BPF C/L/H ALL" and then push [ENTER] key.
q-2: The connected PC tunes BPF C/L/H to peak levels.
or
w-1: Put the cursor on the one of "BPF C/L/H" as desired.
w-2: Push [ENTER] key to start tuning.
w-3: Repeat w-1 and w-2 to perform additional BPF tuning.
Digital RSSI*
[Dig RSSI]
1• Operating CH. : CH 9 Put the cursor on "Dig RSSI" and push the [ENTER] key to
set the Digial RSSI level.
• Connect the SSG to the antenna connec-
tor and set as;
Frequency
Level
Modulation
• Receiving
: 435.000 MHz [L]
485.000 MHz [H]
: –20 dBµ† (–127 dBm)
: No modulation
S-METER
[RSSI]
1• Operating CH. : CH 4 Push the [ENTER] key on the connected computer's keyboard
to set "S3" level.
• Connect the SSG to the antenna connec-
tor and set as;
Frequency
Level
Modulation
Deviation
• Receiving
: 435.000 MHz [L]
485.000 MHz [H]
: +23 dBµ† (–84 dBm)
: 1 kHz
: ±3.0 kHz
2• Set the SSG as;
Level
• Receiving
: –7dBµ† (–114 dBm)
Push the [ENTER] key on the connected computer's keyboard
to set "S1" level.
SQUELCH
LEVEL
[SQL]
1 • Operating CH. : CH 4 Top
panel
Connect speaker to the JIG
cable.
Set the SQL level to
close squelch.
Then set SQL level
at the point where
the audio signals
just appears.
• Connect the SSG to the antenna connec-
tor and set as;
Frequency
Level
Modulation
Deviation
• Receiving
: 435.000 MHz [L]
485.000 MHz [H]
: –14dBµ† (–121 dBm)
: 1 kHz
: ±3.0 kHz
†; The output level of the standard signal generator (SSG) is indicated as the SSG's open circuit.
*; [IC-F80DT/DS] only
6 - 1
SECTION 6 PARTS LIST
M.=Mounted side (T: Mounted on the Top side, B: Mounted on the Bottom side)
REF ORDER DESCRIPTION M. H/V
NO. NO.
LOCATION
[FRONT UNIT]
IC1 1110006440 S.IC M62320FP DF5J B 20.7/73.6
IC2 1110006440 S.IC M62320FP DF5J B 20.7/62.5
IC101 1180002400 S.REG S-812C30AMC-C2K-T2 B 9.4/80.8
IC201 1110001810 S.IC TA7368F (ER) B 28.5/47.4
IC203 1110005340 S.IC NJM12902V-TE1 B 8.2/68
IC204 1130004200 S.IC TC4S66F (TE85R) B 7.6/75.9
IC205 1130004200 S.IC TC4S66F (TE85R) B 34/56.1
Q1 1590000980 S.TR DTB123EK T146 B 34.6/94.7
Q2 1590000980 S.TR DTB123EK T146 B 34.4/98.3
Q102 1590001940 S.TR DTC144EE TL B 26.2/72.9
Q103 1590000980 S.TR DTB123EK T146 B 12.7/76.7
Q104 1590000980 S.TR DTB123EK T146 B 28.2/35.7
Q201 1590002230 S.TR UMG2N TL B 14/55
Q202 1520000450 S.TR 2SB1132 T100 Q B 35.4/37.3
Q203 1590001190 S.TR XP6501-(TX) AB B 29.9/42.1
Q206 1590002430 S.TR DTA144EE TL B 14/50.9
Q207 1590000430 S.TR DTC144EUA T106 B 37.1/96.5
Q208 1530002840 S.TR 2SC4116-Y (TE85R) B 41.4/113
Q209 1560001330 S.FET RSR025N03 B 41.1/109.5
Q210 1560001330 S.FET RSR025N03 B 41.1/105.4
D1 1730002530 S.ZEN NNCD6.2G-T1 B 25.2/81.6
D101 1160000140 S.DIO DAP222 TL B 15.3/47.1
D102 1160000140 S.DIO DAP222 TL B 15.3/45
D201 1790001250 S.DIO MA2S111-(TX) B 17.2/49
D202 1790001250 S.DIO MA2S111-(TX) B 10.9/71.5
D203 1790001250 S.DIO MA2S111-(TX) B 36.2/54.2
D204 1790001250 S.DIO MA2S111-(TX) B 12.3/50.9
D205 1790001250 S.DIO MA2S111-(TX) B 14.9/52.7
L1 6200004720 S.COL MLF1608D R10K-T B 30.3/87.8
L2 6200004720 S.COL MLF1608D R10K-T B 28.9/88.5
L3 6200004720 S.COL MLF1608D R10K-T B 26.3/87.1
L4 6200004720 S.COL MLF1608D R10K-T B 21.6/89.7
L5 6200004720 S.COL MLF1608D R10K-T B 25.1/88.1
L6 6200004720 S.COL MLF1608D R10K-T B 31.2/90.2
L7 6200004720 S.COL MLF1608D R10K-T B 23.9/86.1
R1 7030005000 S.RES ERJ2GEJ 471 X (470 Ω) T 34.8/127
R2 7030007280 S.RES ERJ2GEJ 331 X (330 Ω) T 34.8/126.1
R3 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 36.5/93.5
R4 7030004980 S.RES ERJ2GEJ 101 X (100 Ω) B 26.1/77
R5 7030004980 S.RES ERJ2GEJ 101 X (100 Ω) B 26.1/75.8
R6 7030004980 S.RES ERJ2GEJ 101 X (100 Ω) B 25.7/67
R7 7030004980 S.RES ERJ2GEJ 101 X (100 Ω) B 25.8/65.1
R11 7030005120 S.RES ERJ2GEJ 102 X (1 kΩ) B 21.3/86.2
R12 7030001090 S.RES MCR50JZHJ 47
Ω(470) B 33.7/83.9
R13 7030003440 S.RES ERJ3GEYJ 102 V (1 kΩ) B 27.5/87.1
R15 7030004970 S.RES ERJ2GEJ 470 X (47 Ω) B 22.8/86.3
R16 7030004970 S.RES ERJ2GEJ 470 X (47 Ω) B 28.2/85
R30 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 40.7/74.4
R31 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 40.7/75.3
R32 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 40.7/76.2
R33 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 40.5/77.1
R34 7030005120 S.RES ERJ2GEJ 102 X (1 kΩ) B 17.2/89.4
R35 7030005120 S.RES ERJ2GEJ 102 X (1 kΩ) B 18.1/89.3
R36 7030005120 S.RES ERJ2GEJ 102 X (1 kΩ) B 19/89.3
R37 7030005120 S.RES ERJ2GEJ 102 X (1 kΩ) B 19.9/89.3
R38 7030005050 S.RES ERJ2GEJ 103 X (10 kΩ) B 40.7/65.6
R40 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 40.7/72.5
R50 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ)
[F80DT/T] only B 16.4/79.1
R51 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ)
[F80DS/S] only B 17/80.6
R101 7030007270 S.RES ERJ2GEJ 151 X (150 Ω) B 12.6/78.9
R102 7030008370 S.RES ERJ2GEJ 561 X (560 Ω) B 11.1/78.3
R103 7030004980 S.RES ERJ2GEJ 101 X (100 Ω) B 18.2/33.6
R104 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 15.4/57.1
R105 7030007250 S.RES ERJ2GEJ 220 X (22 Ω) B 9.1/93.2
R106 7030007250 S.RES ERJ2GEJ 220 X (22 Ω) B 10/93.2
R107 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 14.1/57.9
R108 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 14.8/60.7
R109 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 15.2/62.5
R110 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 26.6/58.8
R111 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 26.6/59.7
R112 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 26.6/60.6
R113 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 26.6/61.5
R115 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 12.8/94.2
R116 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 40/67.7
R201 7030005050 S.RES ERJ2GEJ 103 X (10 kΩ) B 17.6/55
R202 7030005050 S.RES ERJ2GEJ 103 X (10 kΩ) B 16.3/54.2
R203 7030003830 S.RES ERJ3GEYJ 185 V (1.8 MΩ) B 26.8/71.1
R204 7030005120 S.RES ERJ2GEJ 102 X (1 kΩ) B 15.5/48.9
R205 7030005050 S.RES ERJ2GEJ 103 X (10 kΩ) B 14.5/49.2
R207 7030005600 S.RES ERJ2GEJ 273 X (27 kΩ) B 11.8/63.6
R208 7030007060 S.RES ERJ2GEJ 684X (680 kΩ) B 12.6/69.7
R209 7030005230 S.RES ERJ2GEJ 334 X (330 kΩ) B 13.8/68.6
R210 7030007340 S.RES ERJ2GEJ 153 X (15 kΩ) B 13.8/66.8
R211 7030005240 S.RES ERJ2GEJ 473 X (47 kΩ) B 13.8/69.5
R212 7030007300 S.RES ERJ2GEJ 332 X (3.3 kΩ) B Mar-69
R213 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 31.5/57.4
R214 7030005070 S.RES ERJ2GEJ 683 X (68 kΩ) B 36.2/56.3
R215 7030005120 S.RES ERJ2GEJ 102 X (1 kΩ) B 27.2/42.1
R216 7030005120 S.RES ERJ2GEJ 102 X (1 kΩ) B 13.6/49.2
R217 7030007340 S.RES ERJ2GEJ 153 X (15 kΩ) B 10.2/64.5
R219 7030003860 S.RES ERJ3GE JPW V B 7.3/64.3
R221 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 6.4/63.2
R222 7030005080 S.RES ERJ2GEJ 823 X (82 kΩ) B 34.5/51
R223 7030005600 S.RES ERJ2GEJ 273 X (27 kΩ) B 3/69.9
R224 7030007290 S.RES ERJ2GEJ 222 X (2.2 kΩ) B 2.8/67.1
R225 7030009140 S.RES ERJ2GEJ 272 X (2.7 kΩ) B 30.2/43.9
R226 7030007300 S.RES ERJ2GEJ 332 X (3.3 kΩ) B 27.2/43.9
R227 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 16.7/51.2
R228 7030005700 S.RES ERJ2GEJ 274 X (270 kΩ) B 5.1/64.9
R229 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 9.3/72.6
R231 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 3/68.1
R232 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 7.6/72.6
R235 7030007260 S.RES ERJ2GEJ 330 X (33 Ω) B 27.6/51.9
R236 7030005530 S.RES ERJ2GEJ 100 X (10 Ω) B 27.6/51
R237 7030005220 S.RES ERJ2GEJ 223 X (22 kΩ) B 5.6/78.2
R238 7030005060 S.RES ERJ2GEJ 333 X (33 kΩ) B 6/79.4
R239 7030005170 S.RES ERJ2GEJ 474 X (470 kΩ) B 36.5/99.3
R240 7030005170 S.RES ERJ2GEJ 474 X (470 kΩ) B 38.5/98.7
R241 7030005090 S.RES ERJ2GEJ 104 X (100 kΩ) B 36.9/98.4
R242 7030005050 S.RES ERJ2GEJ 103 X (10 kΩ) B 41.9/114.9
R250 7030003860 S.RES ERJ3GE JPW V B 27.2/68.1
R251 7030003860 S.RES ERJ3GE JPW V B 40.2/78.8
R259 7030004970 S.RES ERJ2GEJ 470 X (47 Ω) B 16.6/87.8
R260 7030004970 S.RES ERJ2GEJ 470 X (47 Ω) B 15.7/87.8
R261 7030003860 S.RES ERJ3GE JPW V B 41.3/71.5
R262 7030005050 S.RES ERJ2GEJ 103 X (10 kΩ) B 16.7/53
R263 7030010040 S.RES ERJ2GE-JPW B 40.5/46
R264 7030010040 S.RES ERJ2GE-JPW B 40.5/40
R265 7030010040 S.RES ERJ2GE-JPW B 40.5/34
R266 7030010040 S.RES ERJ2GE-JPW B 40.5/28
R267 7030010040 S.RES ERJ2GE-JPW B 40.5/22
R268 7030010040 S.RES ERJ2GE-JPW B 40.5/15.9
R269 7030010040 S.RES ERJ2GE-JPW B 40.5/10
R270 7030010040 S.RES ERJ2GE-JPW B 40.5/4
R271 7030010040 S.RES ERJ2GE-JPW B 5.4/46
R272 7030010040 S.RES ERJ2GE-JPW B 5.4/40
R273 7030010040 S.RES ERJ2GE-JPW B 5.4/34
R274 7030010040 S.RES ERJ2GE-JPW B 5.5/28
R275 7030010040 S.RES ERJ2GE-JPW B 5.5/16
R276 7030010040 S.RES ERJ2GE-JPW B 5.5/4
R277 7030010040 S.RES ERJ2GE-JPW B 5.5/10
R278 7030010040 S.RES ERJ2GE-JPW B 5.5/22
C2 4030016790 S.CER ECJ0EB1C103K B 21.3/87.6
C3 4030017460 S.CER ECJ0EB1E102K B 17.1/86.6
C4 4030016930 S.CER ECJ0EB1A104K B 15.3/75.2
C5 4030016930 S.CER ECJ0EB1A104K B 15.2/64.3
C6 4030017460 S.CER ECJ0EB1E102K B 15.3/74.3
C7 4030017460 S.CER ECJ0EB1E102K B 15.2/63.4
C8 4030017430 S.CER ECJ0EC1H101J B 22.7/83.3
C9 4030017430 S.CER ECJ0EC1H101J B 19.4/86.3
C10 4030017430 S.CER ECJ0EC1H101J B 19/87.8
C11 4030017460 S.CER ECJ0EB1E102K B 26.1/84.8
C12 4030017430 S.CER ECJ0EC1H101J B 24.2/84.1
C13 4030017430 S.CER ECJ0EC1H101J B 41.1/73.4
C15 4030017430 S.CER ECJ0EC1H101J B 17.5/87.8
C16 4030016790 S.CER ECJ0EB1C103K B 22.2/85.1
C17 4030009580 S.CER C1608 JB 1H 681K-T B 26.9/38.1
C18 4030009580 S.CER C1608 JB 1H 681K-T B 30.8/36.1
C19 4030009580 S.CER C1608 JB 1H 681K-T B 35.5/40.9
C101 4550006300 S.TAN ECST1AY475R B 13.8/80.6
C102 4030016930 S.CER ECJ0EB1A104K B 12.3/82.1
C103 4030016930 S.CER ECJ0EB1A104K B 16.4/32.6
C104 4030017420 S.CER ECJ0EC1H470J B 41.3/67.6
C105 4550006150 S.TAN ECST1CY105R B 7.2/90.4
C106 4550006620 S.TAN ECST0JY226R B 11.6/83.8
C107 4030016790 S.CER ECJ0EB1C103K B 10.8/85.4
C108 4030009580 S.CER C1608 JB 1H 681K-T B 15.4/43.3
C109 4030016930 S.CER ECJ0EB1A104K B 9/91.5
S.=Surface mount
REF ORDER DESCRIPTION M. H/V
NO. NO.
LOCATION
[FRONT UNIT]
[L]=Low band, [H]=High band
This manual suits for next models
3
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