Infineon TLE4997 User manual

Sense & Control
User’s Manual
v01_01, 2019-08
TLE4997
Configuration and Calibration of Linear Hall Sensor

Edition 2019-08
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2019 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

TLE4997
User’s Manual
Table of Contents
User’s Manual 3 v01_01, 2019-08
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 TLE4997 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 TLE4997 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Programmer Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.1 Communication Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Command Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3.1 Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3.2 Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6 Programming Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6.1 Setting the TEST register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.2 Readout of the EEPROM Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.3 Setting the EEPROM Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.4 Calculation of Bits to Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.5 Calculation of Bits to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.6 Margin Voltage Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.7 DATA access example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.8 Temporary overwrite of EEPROM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.9 DAC setup example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Configuration & Calibration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 Magnetic Field Range - R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2 Gain Setting - G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 Offset Setting - OS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4 Low-Pass Filter - LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.5 DAC Input Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6 Clamping - CH, CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.7 Temperature Compensation - TL, TQ & TT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Calibration of TLE4997 Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 Integrated Temperature Polynomial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 Application Sensitivity Polynomial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 Determination of Sensitivity Polynomial from Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4 Calculation of Final Temperature Compensation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.4.1 Algorithm for Finding the Optimum Temperature Coefficient Set . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.4.2 Example Implementation Code for Temperature Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.5 Usage of Infineon’s Temperature Calibration Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6 Calibration of TLE4997 Output Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1 Two-Point Calibration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2 Two-Point Calibration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.1 Calibration with Application Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2.2 Calibration without Application Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table of Contents

TLE4997
User’s Manual
Scope
User’s Manual 4 v01_01, 2019-08
1Scope
This document is valid for all TLE4997 variants and derivates. It gives a detailed description of the configuration
and calibration procedure, which is recommended to configure the TLE4997 for optimum accuracy in a sensing
application.
2 TLE4997 Signal Processing
The TLE4997 uses a fully digital signal processing concept. Analog values from the Hall probe are directly
converted to raw digital signals by the Hall ADC and then compensated and processed in the digital signal
processing unit (DSP) using configuration parameters stored in the EEPROM and the temperature data acquired
by an integrated temperature sensor. A configurable second-order temperature polynomial is implemented to
compensate the thermal reduction of the remanent magnetic flux of a permanent magnet used in a position
sensing application. Additionally, an application-specific output characteristic can be set by configuring the
EEPROM parameters of Gain and Offset.
Figure 2-1 Signal Flow Diagram of the TLE4997
Figure 2-1 shows the signal flow diagram for temperature compensation and output characteristic in the DSP, and
the influence of the relevant configuration parameters stored in the EEPROM. The Hall signal is processed in the
following sequence of steps:
1. The analog Hall signal is converted by the Hall ADC, which operates at the configured magnetic range setting.
2. The digital value is filtered by a digital low-pass filter, which operates at a configurable filter frequency given
by the “LP filter”-setting. The output of the filter is stored in the HADC register.
3. The HADC value is multiplied by the temperature compensation polynomial and stored in the HCAL register.
The first order (TL) and second order (TQ) coefficients of the polynomial are configurable. The third order
coefficient (TT) is fixed.
4. The HCAL value is multiplied by the configured gain value.
5. The configured offset value is added to the HCAL value.
6. The digital Hall value is clamped according to the configured upper and lower clamping limits. The output value
of the clamping stage is converted from digital to analog.
7. An output voltage is transmitted on the OUT pin and is proportional to the supply voltage (ratiometric DAC).
Stored in
EEPROM
Memory
+
A
D
Hall
Sensor
Limiter
(Clamp)
Out
X
Range LP
Offset
Gain
x
Clamping Low
Clamping High
A
D
TADC TCAL
Temperature
Sensor
Norm-
alize T-Polynomial
TL
TT
TQ
HADC
HCAL
VOUT
D
A
VDAC

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3 TLE4997 Programming
3.1 Programmer Connection
Figure 3-1 shows the connection of the TLE4997 to a programmer. The pins VDD and OUT of the sensor IC are
used for the digital programming interface as described in Table 3-1 (See datasheet of corresponding TLE4997
type for pinout).
Figure 3-1 Connection of TLE4997 to Programmer
Table 3-1 Pin Functions for Programming Interface
Pin Programming Function
VDD Programming interface clock
GND Ground
OUT Programming interface data I/O
optional
VDD
I/O 1
I/O2
GND
47nF
47nF
47nF
47nF
PROGRAMMER
TLE
4997x
out
V
DD
GND
TLE
4997x
out
V
DD
GND
application module

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3.2 Programming Interface
3.2.1 Communication Scheme
The digital programming interface uses specific frames, which can have one of the two following functions:
• Command frames contain a specific task (e.g. read/write data, select EEPROM programming etc.) and a
corresponding address
• Data frames contain a 16 bit data value sent to or received from the device - these frames can only follow a
proper command frame for reading or writing data
A valid frame has the following properties:
• A frame consists of 21 bits in total
• A bit is shifted in or out via the output line with a rising clock edge on the supply line
• A frame always starts and ends with a '1' (frame bits)
• The LSB of a frame transmitted to the sensor is shifted in first
• The LSB of a frame replied by the sensor is shifted out first
• The whole frame sent to the device, including frame bits, is protected with an even positional and an odd
positional parity bit
The first frame sent has to be a valid command to activate the interface mode and it has to be sent within 19ms
after power up. As an additional protection, the device does not deactivate its output stage during this transmission
(using 21 clock pulses) as shown in Figure 3-2. This means that the interface driver of the programmer needs to
overrule the open drain output stage of the sensor during this initial transmission.
Figure 3-2 First Frame Transmission to the Sensor
Attention: Overruling Vout requires a strong driver on the programmer, since the OUT line must be driven
to low levels close to GND for any “0”-bit and close to VDD for any “1”-bit in order to ensure a
proper communication with the sensor.
After the first frame, to avoid additional power consumption in the output stage of the device, the internal driver is
deactivated in programming mode while the sensor is receiving a frame. It is activated again after completion of
the transmission. This is illustrated in Figure 3-3.
Figure 3-3 Further Frame Transmisson from the Programmer to the Sensor (Write Access)
VDD
Vout
LSB MSB
during first transmission , the output stage is still switched on
power up interface
activated
internal buffer on
VDD
Vout
LSB MSB
during transmission the buffer is switched off internal buffer on
interface
active
interface
active
Z
protocol
output
leading driver
off pulse
protocol
output

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In case of a wrong command or data frame, the interface is immediately locked and the device falls back to its
normal application mode. The read access to the device is triggered by clock pulses on the supply line as shown
in Figure 3-4. The timing of read and write accesses is described in Chapter 3.3.2.
Figure 3-4 Frame Transmisson from the Sensor to the Programmer (Read Access)
3.3 Command Frame
The structure of a command frame is shown in Figure 3-5. Available commands are given in Table 3-2. The parity
bits PE (bit 17) and PO (bit 18) have to be set in the follwing way (bit 0 is the LSB, bit 20 is the MSB):
bit0 XOR bit2 XOR bit4 XOR …. XOR bit20 = 0
bit1 XOR bit3 XOR bit5 XOR …. XOR bit19 = 0
Figure 3-5 Command Frame Structure
Table 3-2 List of Available Commands
Command Bits (MSB...LSB) Function
0H000000 Leave programming mode1)
1) not to be followed by any data frame
1H000001 Single data readout from given address without increment (sensor
response: one data frame)
3H000011 Data readout from given address with increment (readout finishes
when address “xxx111B” is reached)
9H001001 Single data write to given address without increment (followed by
one data frame)
BH001011 Data write to given address with increment (followed by multiple data
frames; finishes at address “xxx111B” or by sending another
command frame)
CH001100 Enable EEPROM write mode (programs “1”-bits)1)2)
2) followed by application of a programming pulse
DH001101 Enable EEPROM erase mode (programs “0”-bits)1)2)
EH001110 Enable EEPROM margin check mode (programs level check)1)3)
3) followed by application of a margin voltage level before the last clock pulse falling edge
FH001111 EEPROM refresh (update EEPROM registers)1)
VDD
Vout
LSB MSB
digital data readout, buffer in I /O mode
internal buffer on internal buffer on
tailing driver on
pulse
1 1 P
O
P
E0 0 ADDR (6bit) 1 0 CMD (6bit) 1
MSB (bit 20) LSB (bit 0)

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3.3.1 Data Frame
The structure of a data frame sent to the device is shown in Figure 3-6. The parity bits PE (bit 17) and PO (bit 18)
have to be set in the same way as for the command frame (bit 0 is the LSB, bit 20 is the MSB):
bit0 XOR bit2 XOR bit4 XOR …. XOR bit20 = 0
bit1 XOR bit3 XOR bit5 XOR …. XOR bit19 = 0
Figure 3-6 Data Frame to Sensor
Figure 3-7 shows a the structure data frame received from the sensor. Instead of a zero bit followed by two parity
bits, the least significant 3 bits of the address used for the readout are transmitted together with the data. This is
to check the plausibility of the received data.
Figure 3-7 Data Frame from Sensor
3.3.2 Interface Specification
Table 3-3 specifies the operating conditions of the programming interface, which must be met in order to ensure
correct operation of the TLE4997 during programming. All specified parameters refer to these operating
conditions, unless otherwise noted.
The specification for timings and electrical levels of the programming interface is shown in Table 3-4. The meaning
of the timing parameters is illustrated in Figure 3-8.
Table 3-3 Operating Range of the Programming Interface
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Supply voltage VDD 4.5 – 5.5 V –
Supply buffer capacitance CS47 – 1000 nF VDD to GND
Load capacitance CL0.01)
1) >47nF soldered to the device required in case that connectivity failures can influence the programming voltage.
– 210 nF OUT to GND
Ambient temperature TPRG 10 – 60 °C during programming
Number of programming
cycles
NPRG 10 Cycles Programming is allowed only at
start of lifetime
Programming time tPRG – 100 – ms For complete memory
Programming start time tPRG_START – – 19 ms To start programming mode, a
first read command shall be sent
within this time window after
power-up
1 0 P
O
P
EDATA (16bit) 1
MSB (bit 20) LSB (bit 0)
1ADR (3 LSBs) DATA (16bit) 1
MSB (bit 20) LSB (bit 0)

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Figure 3-8 Frame Timing
Table 3-4 Electrical and Timing Specification of the Programming Interface
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
VDD clock high level VDD,CLKHI 8.8 9.4 10 V specification of VDD operating
range does not apply to clock
VDD clock low level VDD,CLKLOW 4.8 5 5.2 V
OUT data out high level VO,OHIGH VDD - 2 – VDD,CLKHI V OUT follows VDD if ‘high’
OUT data out low level VO,OLOW 0–2.0 V
OUT data in high level VO,IHIGH 3.0 VDD VDD + 0.1 V
OUT data in low level VO,ILOW -0.2 0.0 0.1 V
OUT data input current IO-50 – 50 mA 1)
1) capacity of external driver, especially during initial interface access (to overwrite ratiometric device output).
VDD clock high time tCH 2.4 50 100 µs 5k...250kBit/s
VDD clock low time tCL 1.6 4.0 100 µs 5k...250kBit/s
Data in setup time tSU 1.5 2.0 – µs to rising VDD
Data in hold time tHLD 2.3 3.0 – µs after rising VDD
Data out settling time tSET – 1.0 1.7 µs after rising VDD
Time between frames tMIN 10.0 – – µs
Buffer off delay tDEL 10.0 25.0 – µs 2)
2) to reduce collisions with the ext. driver, it must be switched on slower than tDEL min. and switched off faster than tHLM max.;
charge/discharge behaviour on VOUT depends also on capacitive output load.
Buffer on delay tHLM – 5.0 10.0 µs 2)3)
3) to reach again a valid and stable ratiometric VOUT signal state, please check the power-on time in the data sheet.
VDD
Vout
LSB MSB
tcl tch
tsu thldtdel thlm
LSB
tset tset
tmin
init
frame
data read
frame

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In order to permanently store a programmed parameter set to the EEPROM, the “EEPROM erase” and “EEPROM
write” commands shall be sent, followed by a programming pulse. Figure 3-9 shows the timing of the programming
pulse.
Figure 3-9 Programming Pulse Timing
After programming, a margin check is necessary to test the stability of the programmed data. The margin check
is initiated by an “EEPROM margin check” command followed by a margin voltage.
Figure 3-10 Margin Check Timing
The margin voltage is varied during subsequent steps within the threshold margin level range. A too low margin
voltage value indicates a too short programming pulse duration or a too low programming voltage. A too high
margin voltage value indicates a too long programming pulse duration or a too high programming voltage.
Table 3-5 gives the electrical and timing specifications of the programming pulse and the margin voltage check
procedure.
Table 3-5 Electrical and Timing Specification of the Programming Pulse and Margin Voltage
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
OUT data input current IO0 – 20 mA during application of
programming pulse or margin
voltage
OUT margin level VO,MARG -0.1 – 7 V
Threshold margin level VTH 2.23 – 4.5
0.4
V
V
check “1”
check “0”
Margin setup time tMARG 200 – – µs
VDD slope for margin VDD/t 5 10 150 V/µs
OUT program level VO,PROG 19.2 19.3 19.4 V
VDD
Vout
MSB
t
HLD
LSB
t
MIN
next command
frame
t
MIN
erase or write
command frame
(buffer stays off)
V
prog
pulse
V
O,PROG
/t
(rise)
V
O,PROG
/t
(fall)
t
PROG,WR
or t
PROG,ER
t
HLD
VDD
Vout
MSB LSB
t
MARG
next command
frame
t
min
margin
command frame
(buffer stays off)
V
dd
/t
(fall)
t
hld
apply V
O,MARG
and
capture EEPROM data
t
min

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3.4 Register Map
Table 3-6 shows the internal registers of the TLE4997 (compare also Figure 2-1).
Note: To access the registers (except STATUS, HADC, TADC, VADC, DAC_SET and TEST), the digital signal
processing unit (DSPU) has to be disabled first via the TEST register.
HCAL
This register contains the temperature compensated magnetic measurement as a 16bit signed value. This value
is in the range of +/- 30000.
TCAL
This register contains a 16 bit signed value and delivers the current junction temperature of the device. The
junction temperature in °C is calculated from the register value by: TJ= (TCAL/16+48) [°C].
VDAC
This register contains a 12 bit unsigned decimal result applied to the internal DAC for the ratiometric output stage.
The value range is from 0 to 4095 and corresponds to 0% to 100% of VDD.
HADC
This register contains a 16bit signed value that corresponds to the raw Hall cell measurement value. This value is
in the range of +/- 20000.
OUT program slope
(rise)1)
VO,PROG/t – – 2 V/µs time to reach VO,PROG shall not
exceed 50 µs
OUT program slope
(fall)1)
VO,PROG/t -10 – – V/µs time to reach 1v max. shall not
exceed 50 µs
OUT write time tPROG,WR 9.9 10.0 10.1 ms
OUT erase time tPROG,ER 79.2 80.0 80.8 ms
1) faster slope may lead to permanent damage of the EEPROM.
Table 3-6 TLE4997 Register Map
Address Symbol Function R/W
05HHCAL Calibrated Hall value read only
06HTCAL Calibrated temperature value, including reference temperature T0read only
07HVDAC Calculated DAC value, incl. clampling read only
0AHHADC Uncalibrated Hall ADC value read only
0BHTADC Uncalibrated temperature ADC value read only
0FHSTATUS Status register read only
10H...19HEEPROM EEPROM registers (see Chapter 3.5) read/write
20HDAC_SET Direct setup of DAC value read/write
21HTEST Test mode register read/write
Table 3-5 Electrical and Timing Specification of the Programming Pulse and Margin Voltage (cont’d)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.

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TADC
This register contains a 15bit unsigned raw temperature value.
STATUS
The content of the status register is shown in Figure 3-11.
Figure 3-11 Status Register
• CRC ok has to be “1”, otherwise the DSP built-in self-test was failed and the device is defective
• LOCKED must be ’0’ as long as the lockbits are not programmed. After setting the lockbits the lock can be
verified by refreshing the EEPROM content and checking this bit before the supply of the device is removed
or the interface is closed.
• perr_adr has to be on address FH (“1111B”), otherwise it shows the first EEPROM address where the internal
parity check failed.
• perr_more must be “0”, otherwise more than one EEPROM address has a parity error.
• perr_col must be “0”, otherwise one or more EEPROM columns have a parity error.
• HWver contains the actual silicon revision starting with 0 (=”000”). The latest version from 8’ manufacturing line
is version 3 (=”011”, availability from mid 2006 and released for productive use).
• ROMSIG has to be 1FH, otherwise the DSP ROM is not valid and the device is defective.
DAC_SET
This register contains a 12 bit unsigned decimal value. When the DAC test bit is set, the value of this register is
used on the ratiometric output.
TEST
The content of the test register is shown in Figure 3-12. All bits are “0” after reset. All bits not described or used
shall be kept at “0”.
Figure 3-12 Test Register
• “Margin zero on” is used to select the margin test mode. It is set to ‘1’ for testing the EEPROM threshold
voltages of cells programmed to ‘0’, and it is set to ‘0’ for testing the EEPROM threshold voltages of cells
programmed to ‘1’.
• “FEC off” switches off the error correction of the EEPROM. This bit has to be set when reading the EEPROM
content.
• “REF off” switches off the automatic (cyclic) refresh performed by the DSP to actualize the EEPROM registers
from the EEPROM cells. This bit has to be set when writing new values to the EEPROM registers.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSB
ROMSIG4 perr_more
LOCKED
perr_adr0
CRC ok
perr_adr1 perr_adr2 perr_adr3
HWver0
ROMSIG3 ROMSIG2 ROMSIG1 ROMSIG0
HWver1 HWver2
perr_col
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSB
FEC off
DAC test DSP stop REF off DSP off
0
0
0 0
0
0 0 0 0 0 0
MSB

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• “DSP off” switches off the signal processing unit (DSP). This bit has to be set prior to accessing the internal
register values via the interface (HCAL, TCAL, SCAL and EEPROM).
• “DSP stop” has to be set prior to switching the DSP off (as a separate command) before reading out the
calculated data HCAL, TCAL, and/or SCAL. This allows the DSP to finish the calculation of the current sample
and all values in the RAM are consistent.
• “DAC test” switches from the DSP DAC value to the DAC_SET value. This allows setting any DAC value
directly to measure the output voltage for a given DAC value for calibration proposes.
3.5 EEPROM Map
Figure 3-13 shows the content of the EEPROM registers.
Figure 3-13 EEPROM Map of TLE4997 (all types).
The fields marked in red are configuration parameters for the sensor hardware. Those marked in yellow are used
by the DSP algorithms for signal processing. The purple fields are used to determine the condition of the
parameters by an external programming software (user defined) and the blue and cyan fields are parity bits for the
corresponding lines and columns used by the internal forward error correction (FEC). All parameters are unsigned
integer values. The reserved fields marked in white shall not be changed.
The functional description of the configuration and calibration parameters in the EEPROM map is given in
Chapter 4.
Parity Bits
The parity Pc of each column (including the precalibration ranges) is even for even bit positions (bit0=LSB, bit2,
bit4, ... bit14) and the parity PI for all odd columns (bit1, bit3, ... bit15=MSB) is odd. The parity Pl of every EEPROM
line (address 0x10 ... 0x19) needs to be calculated so that the sum of its bits is always odd.
Note: Before accessing the EEPROM, the forward error correction (FEC) shall be disabled via the TEST register.
ADDR Description 15141312111009080706050403020100
10
H
Parity of each column P
l
P
c
P
c
P
c
P
c
P
c
P
c
P
c
P
c
P
c
P
c
P
c
P
c
P
c
P
c
P
c
11
H
IC lock high, USER,
clamping low P
l
LH USER CL - Clamping low (bit 11...0)
12
H
Clamping high value P
l
Reserved CH - Clamping high (bit 11...0)
13
H
Gain P
l
G - Gain (bit 14...0)
14
H
Offset P
l
OS - Offset (bit 14...0)
15
H
TQ value, TT value P
l
TQ - quadratic temperature
coefficient (bit 7...0)
precal area - do not modify
TT - register (bit 6 … 0)
16
H
LP value, Range, TL
Value, IC lock low P
l
LP -
low pass
(bit 0,2,1)
R-
Range
(bit 1,0)
TL - linear temperature coefficient (bit
8…0) LL
17
H
Reserved P
l
Reserved - do not modify
18
H
Reserved P
l
Reserved - do not modify
19
H
Reserved P
l
Reserved - do not modify

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User Bits
The two USER bits are free bits which can be used by the system integrator, for example to track calibration steps.
Lock Bits
LH and LL are lock bits (LH locked if '1', LL locked if '0'). If either LH, LL or both are set to locked state, the
programming interface cannot be accessed anymore.
3.6 Programming Flow
The programming flow diagram in Figure 3-14 shows the procedural steps to setup the EEPROM content and to
program new values (EEP_NEW). EEP_PROG means the intermediate values stored in the EEPROM register
and EEP_OLD means the initial (old) EEPROM content.
Flowchart description:
1. Switch on the device.
2. Send an initial command (status register readout):
Check that the status is valid (Status register = F93DH or FB3DH, compare Chapter 3.4), if not, do not continue
and check the failure.
3. Set the register bits FECoff = 1, DSPoff = 1, REFoff = 1 (allows EEPROM access).
4. Read out the EEPROM content to an array EEP_OLD (store also for reference purpose and traceability)
In parallel: Prepare the data that shall be programmed as an array EEP_NEW.
5. Calculate the bits to be cleared from EEP_OLD to EEP_NEW as EEP_PROG array.
6. Write the EEPROM content from the EEP_PROG array to the EEPROM registers
7. Send the EEPROM erase command
Apply an erase programming pulse on the output pin (see Chapter 3.3.2).
8. Calculate the bits to be set from EEP_OLD to EEP_NEW as EEP_PROG array.
9. Write the EEPROM content from the EEP_PROG array to the EEPROM registers.
10. Send the EEPROM write command
Apply a write programming pulse on the output pin (see Chapter 3.3.2).
11. Send the EEPROM margin command
During the falling edge of the margin pulse on VDD, apply VO,MARG on the output (see Chapter 3.3.2).
12. Read out the EEPROM content to the array EEP_PROG.
13. Verify the EEP_PROG data against EEP_NEW to check the programming (no bits flipped)
Optionally, steps 11 to 13 can be looped to find the exact margin threshold voltage.
If the margin threshold voltage is too low, do not continue and check the failure.
14. Check the status register again.

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Figure 3-14 Programming Flow
The following chapters give a more detailed description of individual steps of the programming flow:
EEP_OLD
EEP_NEW
EEP_PROG
EEP_OLD
EEP_NEW
EEP_PROG
For each line I from 0x10 to 0x19:
EEP_PROG[i] = (EEP_OLD[i] XOR EEP_NEW[i]) AND EEP_NEW[i]
(as precal areas must not be changed, the bits in this areas must remain ‚0')
Readout could be looped for several
margin voltages (starting from a very
high voltage e.g. 5V) to find the margin
level of the EEPROM
see above (like complete
readout procedure for
EEP_OLD)
EEPROM
programming
INIT-CMD:
cmd=0x01
adr=0x0F
READ DATA
V
dd
= 5V
Is
0xF93D or
0xFB3D ?
ILLEGAL
STATUS:
analyse
problem
NO
CMD (write):
cmd=0x09
adr=0x21
DAT: 0x0640
(DSP, FEC,
REF off)
CMD (b read)
cmd=0x03
adc=0x10
RD. B-DATA
CMD (read)
cmd=0x01
adc=0x18
READ DATA
CMD (read)
cmd=0x01
adc=0x19
READ DATA
10x 16bit
> EEP_OLD <
Store this initial
dataset (allows
later restore)
> EEP_NEW <
Given by TC
setup and/or 2P
algorithms etc.
User input, TC
setup algorithm or
2P calibration
algorithm setup
Create erase
pattern for
programming
2x 10x 16bit
CMD (bwrite)
cmd=0x0b
adc=0x10
WR. B-DATA
CMD (write)
cmd=0x09
adc=0x18
WR. DATA
CMD (write)
cmd=0x09
adc=0x19
WR. DATA
CMD (erase):
cmd=0x0D
adr=0x00
V
prog
PULSE
Create write
pattern for
programming
2x 10x 16bit
CMD (write):
cmd=0x0C
adr=0x00
V
prog
PULSE
CMD(marg.):
cmd=0x0E
adr=0x00
V
mar g
+V
dd
-ramp
CMDs (read)
cmd=0x03/01
adr=0x10/8/9
READ DATA
content =
EEP_NEW ?
ILLEGAL
MARGIN
READ:
analyse
problem
NO
FINISHED
margin higher
required limit ?
NO
V
dd
= 0V (off)
For each line I from 0x10 to 0x19:
EEP_PROG[i] = INVERT ((EEP_OLD[i] XOR EEP_NEW[i]) AND EEP_OLD[i])
(as precal areas must not be changed, the bits in this areas must remain ‚1')
Optionally do a last status
readout (adr. 0x0F) to check
the IF mode is still active
and the device is ok.

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3.6.1 Setting the TEST register
The following steps are used to set the TEST register:
1. Send a write command (TEST register set: Command 09H, Adress: 21H).
2. Send a new data word for the register.
3.6.2 Readout of the EEPROM Content
The following steps are used to readout the EEPROM and store the content in an array:
1. Send a block read command (EEPROM data readout: Command 03H, Address: 10H).
2. Read the first 8 data words of the EEPROM and store it in an array.
3. Send a read command (EEPROM data readout: Command 01H, Address: 18H).
4. Read the 9th data word of the EEPROM and store it in an array.
5. Send a read command (EEPROM data readout: Command 01H, Address: 19H).
6. Read the 10th data word of the EEPROM and store it in an array.
3.6.3 Setting the EEPROM Content
The following steps are used to set the EEPROM content with data from an array:
1. Send a block write command (EEPROM data write: Command 0BH, Address: 10H).
2. Send the first 8 data words from the array to the EEPROM.
3. Send a write command (EEPROM data write: Command 09H, Address: 18H).
4. Send the 9th data word from the array to the EEPROM.
5. Send a write command (EEPROM data write: Command 09H, Address: 19H).
6. Send the 10th data word from the array to the EEPROM
3.6.4 Calculation of Bits to Erase
The EEP_PROG array for the erase procedure is calculated from the old EEPROM content EEP_OLD and the
new EEPROM content EEP_NEW in the following way:
For each data word i: EEP_PROG[i] = INVERT ((EEP_OLD[i] XOR EEP_NEW[i]) AND EEP_OLD[i])
Table 3-7 shows an example of a calculated erase mask.
3.6.5 Calculation of Bits to Write
The EEP_PROG array for the write procedure is calculated from the old EEPROM content EEP_OLD and the new
EEPROM content EEP_NEW in the following way:
For each data word i: EEP_PROG[i] = (EEP_OLD[i] XOR EEP_NEW[i]) AND EEP_NEW[i]
Table 3-7 shows an example of a calculated erase mask.
Table 3-7 Erase Array Example
EEP_OLD 0101010101010101
EEP_NEW 0101110001010101
EEP_PROG 1111111011111111
Table 3-8 Write Array Example
EEP_OLD 0101010101010101
EEP_NEW 0101110001010101
EEP_PROG 0000100000000000

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3.6.6 Margin Voltage Check
The threshold voltage of EEPROM cells is dependent on the programming voltage and programming pulse length.
For reliable programming the programming pulse has to be kept within the specification (Table 3-5) at the sensor
interface. The margin command can be used to check the threshold voltages of the programmed cells:
To check the cells programmed to '1', a voltage VO,MARG is applied after the margin check command (Command
EH). For EEPROM cells with a threshold voltage smaller than the applied VO,MARG, a '0' will be stored to the
EEPROM registers, for those with a higher threshold voltage, a '1' will be written. By sweeping the applied VO,MARG,
the actual threshold voltages of each EEPROM cell can be identified.
In order to check the threshold voltages of EEPROM cells programmed to ‘0’, it is necessary to activate the “Margin
zero on” bit in the TEST register before sending the margin check command. Also for the ‘0’ cells, the actual
threshold voltages of each EEPROM cell can be identified, by sweeping the applied VO,MARG.
3.6.7 DATA access example
Following steps are required to readout other internal data like the calibrated temperature and Hall value (as
shown below in Table 3-15). This routines can also be used for an EEPROM access (in that case also FECoff
should be set to ’1’).
Figure 3-15 Basic data access flow
Flowchart description:
1. Switch on the device
2. Send an inital command (status register readout)
3. Read the status data,check that the device is valid and the EEPROM content is valid
4. Set the test register: DSP stop=1 (see previous chapter)
5. Set the test register: DSP stop=1 DSP off=1 (see previous chapter)
6. Send a read command (HCAL)
– Read the data word
EEPROM
programming
INIT-CMD:
cmd=0x01
adr=0x0F
READ DATA
V
dd
= 5V
Is
0xF93D or
0xFB3D ?
ILLEGAL
STATUS:
analyse
problem
NO
CMD (write):
cmd=0x09
adr=0x21
DAT: 0x0800
(DSP stop)
FINISHED
V
dd
= 0V (off)
Optionally do a last status
readout (adr. 0x0F) to check
the IF mode is still active
and the device is ok.
CMD (read)
cmd=0x01
adr=0x05
READ DATA
CMD (write):
cmd=0x09
adr=0x21
DAT: 0x0C00
(DSP stop,
DSP off)
Like reading out H_CAL,
also all other RAM and
EEPROM registers can
be read out here in a loop.

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– This readout might be looped for reading out also other parameters (like TCAL)
7. Check the status register again
Note: This routine can be merged with other (exemplary shown) routines. In that case only one initial frame (the
very first interface access) is required after power-on.
3.6.8 Temporary overwrite of EEPROM data
Following steps are required to readout other internal data like the calibrated temperature and Hall value (as
shown below Table 3-16). As the error correction stays disabled, it is not necessary to use correct parity values
for this temporary setup. In case the parity is always corrected (and it is desired to check the complete behavior
and correct EEPROM array calculation), the “FECoff” bit could be switched off again after the temporary EEPROM
write.
Figure 3-16 Basic EEPROM register overwrite flow
Flowchart description:
1. Switch on the device
2. Send an inital command (status register readout)
3. Read the status data,check that the device is valid and the EEPROM content is valid
4. Set the test register: DSP off=1 FEC off=1 REF off=1 (see previous chapter)
5. Send a write command (for any EEPROM register)
Send the data words (in 16bit format, MSBs containing the parity may be kept ’0’)
6. Set the test register: FEC off=1 REF off=1 (see previous chapter)
- The device is now temporarily working with the new EEPROM setting.
7. Check the status register again
EEPROM
programming
INIT-CMD:
cmd=0x01
adr=0x0F
READ DATA
V
dd
= 5V
Is
0xF93D or
0xFB3D ?
ILLEGAL
STATUS:
analyse
problem
NO
CMD (write):
cmd=0x09
adr=0x21
DAT: 0x0640
(DSP, FEC,
REF off)
FINISHED
V
dd
= 0V (off)
Optionally do a last status
readout (adr. 0x0F) to check
the IF mode is still active
and the device is ok.
All o t h e r EEPROM
registers can be
written here in a loop
(as requi red ).
CMD (write)
cmd=0x09
adr=0x10..19
WR. DATA
CMD (write):
cmd=0x09
adr=0x21
DAT: 0x0250
(FEC, REF
off)
Here the output should
show (temporarily) the
desired result (before
switching off the
supply, of course).

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3.6.9 DAC setup example
To find the exact DAC value for a desired output voltage (e.g. to set up the clamping low/high registers with the
best available accuracy), it is possible to set the DAC value directly and to measure the result on the output pin.
Figure 3-17 Basic DAC setup flow
Flowchart description:
1. Switch on the device
2. Send an inital command (status data readout)
3. Read the status data,check that the device is valid and the EEPROM content is valid
4. Set the test register: “DAC Test”=1 (see previous chapter)
- The output immediately shows the content given by the DAC_SET register.
5. Send a write command (DAC_SET register)
- Send the data word for the desired 12bit DAC value (in 16bit format, MSBs are ’0’)
- The output changes accordingly to the new DAC value in DAC_SET
6. After 10ms (max. output setup time), measure Vout
- Repeat writing a new DAC value (continue at step 5) until the response of all desired DAC values are measured
7. Check the status register again
EEPROM
programming
INIT-CMD:
cmd=0x01
adr=0x0F
READ DATA
V
dd
= 5V
Is
0xF93D or
0xFB3D ?
ILLEGAL
STATUS:
analyse
problem
NO
CMD (write):
cmd=0x09
adr=0x21
DAT: 0x4000
(DAC test)
FINISHED
V
dd
= 0V (off)
Optionally do a last status
readout (adr. 0x0F) to check
the IF mode is still active
and the device is ok.
Set all required DAC
values in a loop
CMD (write)
cmd=0x09
adr=0x20
WR. DATA
Wait 10ms and
evaluate the
response on
the V
out
-pin

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User’s Manual
Configuration & Calibration Parameters
User’s Manual 20 v01_01, 2019-08
4 Configuration & Calibration Parameters
This chapter describes the configuration and calibration parameters that can be set in the EEPROM of the
TLE4997 (see EEPROM map, Chapter 3.5)
4.1 Magnetic Field Range - R
4.2 Gain Setting - G
The overall sensitivity is defined by the range and the gain setting. The output of the ADC is multiplied by the Gain
value. The Gain value is given by:
(4.1)
4.3 Offset Setting - OS
The offset value corresponds to an output voltage with zero field at the sensor. The offset value can be calculated
by:
(4.2)
Table 4-1 Range Setting
Parameter R Range Nominal Range in mT1)
1) Absolute accuracy of range values is not specified.
3Low ±50
12)
2) Setting R = 2 is not used, internally changed to R = 1.
Mid ±100
0 High ±200
Table 4-2 Gain
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Gain range Gain - 4.0 – 3.9998 – 1)2)
1) For Gain values between -0.5 and +0.5, the numerical accuracy decreases.
To obtain a flatter output curve, it is recommended to select a higher range setting.
2) In 100 mT range, a gain value of +1.0 corresponds to typically 40mV/mT. Infineon pre-calibrates the samples to 60mV/mT..
It is recommended to do a final 2-point calibration of each IC within the application.
Gain quantization steps ΔGain – 244.14 – ppm Corresponds to 1/4096
Gain G 16384–()
4096
------------------------------
=
VOS
OS 16384–()
4096
--------------------------------- V×
DD
=