Infineon CoolGaN User manual

Application Note Please read the Important Notice and Warnings at the end of this document V 1.1
www.infineon.com/eval-1edf-g1b-hb-gan page 1 of 23 2020-11-09
AN_1811_PL52_1811_234307
CoolGaN™ 600 V half-bridge evaluation
platform featuring GaN EiceDRIVER™
About this document
Authors: Eric Persson, Yalcin Haksoz
Ordering code: EVAL_1EDF_G1B_HB_GAN
Scope and purpose
This application note explains how to setup and use the CoolGaN™ 600 V half-bridge evaluation board. The
board features a half-bridge of 70 mΩ GaN power transistors, a pair of EiceDRIVER™ GaN gate drivers, and
isolated power supplies for the gate drivers along with input logic that provides adjustable deadtime. Using an
external inductor, the board can be configured for buck or boost-mode, double-pulse testing or continuous
PWM operation, hard or soft-switching at power levels to several kW and frequencies up to MHz range.
Intended audience
This document is intended for power electronic engineers and designers who are already familiar with MOSFET
or IGBT-based converters, inverters and gate drivers, who are interested in looking at the similarities and
differences of GaN power transistors compared to their silicon counterparts.
Figure 1 Front and back view of the CoolGaN™ half-bridge evaluation platform

Application Note 2 of 23 V 1.1
2020-11-09
CoolGaN™ 600 V half-bridge evaluation platform featuring GaN
EiceDRIVER™
Table of contents
Table of contents
About this document....................................................................................................................... 1
Table of contents............................................................................................................................ 2
1Introduction .......................................................................................................................... 3
1.1 Evaluation board specifications .............................................................................................................3
2Functional description............................................................................................................ 4
3Circuit description.................................................................................................................. 5
3.1 Input Logic and deadtime generator......................................................................................................5
3.2 Isolated gate driver power supply..........................................................................................................6
3.2.1 Gate driver power supply transformer..............................................................................................6
3.3 Gate drive circuit .....................................................................................................................................7
3.4 Half-bridge output circuit .......................................................................................................................8
4Setup and use ........................................................................................................................ 9
4.1 Test equipment needed..........................................................................................................................9
4.2 Connections to the terminal block .........................................................................................................9
4.2.1 Connections for double-pulse testing.............................................................................................10
4.2.2 Connections for buck topology .......................................................................................................10
4.2.3 Connections for boost topology......................................................................................................12
4.3 Input PWM generator connections and settings..................................................................................13
4.4 Measurement points .............................................................................................................................13
4.5 Power-up and power-down sequencing..............................................................................................13
4.6 Verifying and adjusting deadtime.........................................................................................................14
4.7 Test inductor recommendation............................................................................................................15
4.8 Initial checkout......................................................................................................................................16
4.9 Operation at high power levels.............................................................................................................17
5Complete schematic ..............................................................................................................18
6PCB layout............................................................................................................................19
7Bill of materials.....................................................................................................................21
8Revision history ....................................................................................................................22

Application Note 3 of 23 V 1.1
2020-11-09
CoolGaN™ 600 V half-bridge evaluation platform featuring GaN
EiceDRIVER™
Introduction
1Introduction
This 600 V gallium nitride (GaN) half-bridge evaluation board enables easy, rapid setup and test of CoolGaN™
transistors along with the dedicated GaN EiceDRIVER™ isolated gate driver IC. The generic topology is
configurable for boost or buck operation, pulse testing or continuous full-power operation. Test points provide
easy access to connect signals to an oscilloscope for measuring the switching performance of CoolGaN™
transistors and gate driver. This board saves the user the time to design their own gate driver and power circuit
to evaluate GaN power transistors.
The half-bridge circuit board has a single PWM input intended for connection to a 50 Ω pulse or signal
generator. Board power comes from a single 5 V supply input, which powers everything including the isolated
gate driver power supplies. Deadtime between the high and low-side is pre-set to 100 ns, but is adjustable via
trimpots. An external (user-supplied) inductor connects to the supplied pluggable terminal-block connector.
The output and bus voltage can range up to 450 V, limited by the capacitor rating. This half-bridge can switch
continuous currents of 12 A, and peak currents of 35 A, hard or soft-switching. Operating frequency can be up to
several MHz, depending on transistor dissipation (limited to about 15W per device with appropriate heatsink
and airflow).
1.1 Evaluation board specifications
Table 1 Evaluation board specifications and limits
Parameter
Values
Unit
Note
Min.
Typ.
Max.
Vcc input voltage
4.8
5.0
5.2
V
Vcc input current
50
100
250
mA
Highest current at maximum frequency
PWM logic input levels
0
5
V
Standard 5 V TTL levels, 50 Ω terminated
Vin+ to Vin-
0
390
450
V
Limited by capacitor voltage ratings
VOto Vin-
0
450
V
(There may be ±30 V spikes appearing on Vo)
Transistor current, DC
12
A
Keep case temp below 125 °C
Transistor current, pulse
35
A
Keep case temp below 125 °C
Transistor power dissipation
15
W
With heatsink, airflow to keep Tcase<125 °C
Operating frequency
(DC)
3
MHz
Within dissipation, temperature limits
PWM pulse width
130
∞
ns
With 100 ns deadtime setting
VSW transition time
5
ns
8 A load, 10-90 percent rise, fall times
Gate drive voltage levels
-8
4
V
These are not limits, typical –and + values
Deadtime adjustment range
0
180
ns
Default setting is 100 ns. If longer deadtime
is necessary, C11, 21 can be increased,
thereby extending the adjustment range.
Note: The PCB dimensions are 76x76 mm.

Application Note 4 of 23 V 1.1
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CoolGaN™ 600 V half-bridge evaluation platform featuring GaN
EiceDRIVER™
Functional description
2Functional description
A typical block diagram is shown in Figure 2 for a double-pulse test application setup. A 5 V power supply
provides the circuit power, and a 0-400 V power supply provides the DC bus voltage. The input PWM signal is
provided by a lab pulse generator. A test inductor is then connected from the DC bus to the switch-node
output. An oscilloscope is used to measure the inductor current (with a current probe), switch-node voltage or
any other signal on the board. The available test points are described in Table 2.
+5V
Vsw
Isolated Gate
Driver Circuit
Isolated Gate
Driver Circuit
Deadtime
Circuit
Deadtime
Circuit
Isolated Gate
Drive Power
Vin+
Vo
Vin-
PWM
0V
Evaluation Board
0-400 V DC
Laboratory
Power Supply
Test
Inductor +
-
5 V DC
Laboratory
Power Supply
50ΩPulse
Generator
Figure 2 Evaluation board typical application example (double-pulse test)
Note that the inductor can be connected to either the positive DC bus as shown in Figure 2, or the negative bus
(Vin-) for inverted double-pulse where the high-side is the active switch, and the low-side is the freewheeling
synchronous rectifier (Figure 3).
The evaluation board can also be easily configured as a buck or boost topology. See section 4.2 for further
details.
+5V
Vsw
Isolated Gate
Driver Circuit
Isolated Gate
Driver Circuit
Deadtime
Circuit
Deadtime
Circuit
Isolated Gate
Drive Power
Vin+
Vo
Vin-
PWM
0V
Evaluation Board
0-400 V DC
Laboratory
Power Supply
Test
Inductor
+
-
5 V DC
Laboratory
Power Supply
50ΩPulse
Generator
Figure 3 Evaluation board connected for inverted double-pulse test

Application Note 5 of 23 V 1.1
2020-11-09
CoolGaN™ 600 V half-bridge evaluation platform featuring GaN
EiceDRIVER™
Circuit description
3Circuit description
The following sections explain each portion of the circuit in detail
3.1 Input Logic and deadtime generator
Logic level PWM input connects to J1 (MMCX connector) which is terminated by 50 Ω (the parallel combination
of R32-35). The input is buffered by noninverting buffer U11 for the high-side, and inverting buffer U21 for the
low-side. These buffers are expecting standard logic-level input voltage from the PWM source, low ≤0.8 V and
high 2-5 V. When the PWM input is low, the switch node VSW is low (the low side GaN transistor turns on).
Conversely, when the PWM input is high, the VSW node is driven high as the high-side GaN transistor turns on.
Figure 4 Input logic and deadtime generator
The purpose of the deadtime circuit is to make sure that the high and low-side GaN transistors are never on
simultaneously. The deadtime should be set long enough that the high-side always fully turns off before the
low-side turn-on (with some margin), and vice-versa. A simple adjustable RCD delay circuit generates the
deadtime. Whenever U11 or U21 outputs a positive (turn-on) edge, the Rx1-Cx1 lowpass filter delays the signal
by the RC time constant to the Schmitt-trigger PWM input of the respective gate driver IC. But the turn-off edge
is not delayed because the Schottky diodes Dx1 bypass the resistor. Thus, each driver IC input has a delayed
turn-on edge, and a non-delayed turn-off edge. Even though the gate driver is capable of recognizing and
delivering an input pulse as short as 18 ns, the deadtime circuit will cause such a short pulse to be ignored.
The practical minimum output pulse width at VSW is about 30 ns. This would occur with an input PWM pulse
width of 130 ns (minus the 100 ns deadtime as described above). Any input pulse width shorter than this is not
recommended, as the resulting output pulse is so small it is really no longer effective. For extremely short
output pulse widths, contact your local Infineon applications support team to discuss gate drive circuit
optimization for the specific requirement.