Infineon OPTIREG TLS412 Series User manual

OPTIREG™ switcher TLS412xD0EPVxx demoboard
Z8F68163134
Preface
Scope and purpose
This document describes the usage of the OPTIREG™ switcher TLS412xD0EPVxx demoboard for the OPTIREG™
switcher TLS412xD0EPVxx family from Infineon Technologies AG. Please also refer to the corresponding
datasheets.
Intended audience
This document is intended for engineers who develop applications.
Table of contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.2 OPTIREG™ switcher TLS412xD0EPVxx features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2 Demoboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.1 EN selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.3.2 RT selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.3 FREQ selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.4 RO and SSON pull-up resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.5 Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.6 Signal adaption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Schematic and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
User manual Please read the Important Notice and Warnings at the end of this document Rev. 1.1
www.infineon.com/OPTIREG-switcher 2020-06-30

1 Introduction
1.1 General description
The OPTIREG™ switcher TLS412xD0EPVxx is a family of synchronous step down regulators especially designed
for automotive applications.
The devices reduce the required amount of external components and thus system cost and board space due to:
• integrated power stages
•so-start feature
• integrated compensation networks
The wide input voltage range and a 100% duty cycle operation mode make the devices suitable for battery
cranking scenarios in automotive applications. The wide switching frequency range allows the selection of
appropriate coils and capacitors. The switching frequency can be synchronized to an external clock signal.
Spread spectrum frequency modulation can be activated to improve the EMI performance in PWM operation.
The devices oer low current consumption in PFM mode at light loads to optimize eiciency. The OPTIREG™
switcher TLS412xD0EPVxx can detect undervoltage and overvoltage conditions of the output voltage and
indicate this via the reset output signal. Overcurrent and overload protection avoid excessive current to protect
the device in short circuit condition at the buck converter output. The integrated thermal shutdown feature
protects the device from overheating. The enhanced PG-TSDSO-14 exposed pad package oers advantageous
thermal performance in the application.
This demoboard supports all members of the OPTIREG™ switcher TLS412xD0EPVxx family, see Table 1. For each
product of the family, the demoboard is available in two dierent configurations. One configuration is
populated with passive components to support the low switching frequency (LF) region of the device, while the
other configuration supports the high switching frequency (HF) region.
Table 1 OPTIREG™ switcher TLS412xD0EPVxx family overview
Sales name Output current Output voltage
TLS4120D0EPV33 2 A 3.3 V
TLS4120D0EPV50 2 A 5.0 V
TLS4120D0EP 2 A adjustable (3 V to 10 V)
TLS4125D0EPV33 2.5 A 3.3 V
TLS4125D0EPV50 2.5 A 3.3 V
TLS4125D0EP 2.5 A adjustable (3 V to 10 V)
OPTIREG™ switcher TLS412xD0EPVxx demoboard
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1.2 OPTIREG™ switcher TLS412xD0EPVxx features
• Input voltage from 3.7 V to 35 V
• Current capability up to 2.5 A
• ±1.5% feedback voltage accuracy in PWM mode
• Ultra low current consumption: typically 31 μA
• Integrated high side and low side power MOSFETs
• Peak current mode PWM regulation
• Light load PFM mode with improved eiciency
• Switching frequency range: 320 kHz to 560 kHz or 1.6 MHz to 2.8 MHz
• 100% duty cycle operation
• Synchronization input
• Spread spectrum frequency modulation for improved EMI performance
•So-start feature
• Integrated compensation network
• Output discharge function in disabled state
• Ultra low current consumption in disabled state: typically 1 µA
• Undervoltage monitoring
• Overvoltage monitoring
• Overcurrent protection and overload protection
• Input undervoltage shutdown
• Wide temperature range Tj = -40°C to 150°C
• Green Product (RoHS compliant)
OPTIREG™ switcher TLS412xD0EPVxx demoboard
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Introduction
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1.3 Block diagrams
Oscillator
FB
SW
SSON
EN
VS
Reset
AGND
PGND
Spread
spectrum
FREQ
Soft-start
ramp
generator
RO
RT
SYNC
VS
Over-
temperature
shutdown
Enable
Internal
supply
UVLO
Bandgap
reference
Control loop
+ driver
Figure 1 Block diagram fixed output voltage variants
OPTIREG™ switcher TLS412xD0EPVxx demoboard
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Introduction
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Oscillator
FB
SW
SSON
EN
VS
Reset
PGND
Spread
spectrum
FREQ
Soft-start
ramp
generator
RO
RT
SYNC
VS
Over-
temperature
shutdown
Enable
Internal
supply
UVLO
Bandgap
reference
Control loop
+ driver
AGND
Figure 2 Block diagram adjustable variants
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Introduction
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2 Demoboard
2.1 Assembly
There are two dierent demoboard assemblies available. One for the fixed output voltage variants and one for
the adjustable variants. They dier only by the resistor configuration around the FB pin. In addition to these two
assemblies, there exist two configurations for each product. One is supporting the low switching frequency (LF)
range, while the other supports the high switching frequency range (HF). The dierence between these
configurations can be seen in the Bill of material.
Figure 3 Assembly fixed output voltage variant in HF configuration
OPTIREG™ switcher TLS412xD0EPVxx demoboard
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Figure 4 Assembly adjustable output voltage variant in HF configuration
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Figure 5 Assembly fixed output voltage variant in LF configuration
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Figure 6 Assembly adjustable output voltage variant in LF configuration
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2.2 Operating conditions
To avoid electrical damage of the demoboard, the values in Table 2 must be maintained.
Table 2 Limit values for operation1)
Parameter Symbol Values Unit Note or condition
Min. Typ. Max.
Board supply voltage VIN 0 – 35 V –
Output voltage VCC(OUT) -0.3 – VIN + 0.3 V 2)
Output current ICC(OUT) 0 – 2.5 A TLS4125D0EPV and
TLS4125D0EPVxx variants only
Output current ICC(OUT) 0 – 2 A TLS4120D0EPV and
TLS4120D0EPVxx variants only
Enable VEN 0 – 35 V Can be connected to VIN via jumper
Reset, Sync VRO,
VSync
0 – 5.2 V TLS412xD0EPV50 and TLS412xD0EP
variants only
Reset, Sync VRO,
VSync
0 – 3.5 V TLS412xD0EPV33 variants only
Ground voltage VGND 0 – 0 V –
1TA = 25°C.
2Absolute maximum ratings
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2.3 Configuration
The demoboard can be easily configured via jumpers on the board.
The board provides the following configuration options:
• connect the enable signal EN to VIN
• select the reset undervoltage threshold VRT,UV,th and reset delay time tRD
• determine the switching frequency fOSC
• pull up RO to VCC(OUT) with a resistor
• pull up SSON to VCC(OUT) with a resistor
2.3.1 EN selection
The EN pin can be connected to VIN by placing a jumper as shown in Figure 7. The EN pin is always connected to
the external banana plug. When the jumper is placed, do not connect an external signal to EN.
Figure 7 JP_EN jumper used to connect EN to VIN
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2.3.2 RT selection
Place the jumper as shown in Figure 8 to choose the following
• undervoltage reset threshold VRT,UV,th
• reset delay time tRD
For settings dierent from Table 3, change the value of resistor R3.
Table 3 JP_RT jumper settings
Jumper setting VRT,UV,th [% of VFB]tRD [ms]
1 - 2 -8 0.03
2 - 3 -8 1.3
not placed -8 5.1
Figure 8 JP_RT jumper placement
2.3.3 FREQ selection
The jumper shown in Figure 9 sets the switching frequency fOSC. The selectable options depend on whether the
board is configured for the high switching frequency range (HF) or the low switching frequency range (LF). To
allow for dierent settings than shown in Table 4 and Table 5, change the value of resistor R4 and R5.
Table 4 JP_FREQ jumper settings for HF board configuration
Jumper setting fOSC [MHz]
1 - 2 1.6
2 - 3 2.8
not placed 2.2
Table 5 JP_FREQ jumper settings for LF board configuration
Jumper setting fOSC [MHz]
1 - 2 0.440
2 - 3 0.320
not placed 2.2
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Figure 9 JP_FREQ jumper placement
2.3.4 RO and SSON pull-up resistors
The RO and SSON pins can be pulled up to VCC(OUT) by placing the jumpers JP_RO_PU and JP_SSON,
respectively, see Figure 10. When placing the jumper on the adjustable variants TLS412xD0EPV make sure to
maintain the Operating conditions. Depending on the nominal output voltage set-point, the functional range
criteria might not be fulfilled. In this case, connect a compliant external voltage to the pins via a series resistor.
The RO pin is an open drain output. When JP_RO_PU is not placed, then connect an external resistor via the
RESET connector to monitor the pin state. Alternatively, the external voltage can be applied to pin 1 of
JP_RO_PU to reuse the onboard pull-up resistor R8. Placing the JP_SSON jumper enables the spread spectrum
feature.
Figure 10 JP_RO_PU and JP_SSON jumpers
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2.3.5 Output voltage adjustment
For the adjustable variants TLS412xD0EPV the resistor divider consisting of R1 and R2 sets the nominal output
voltage level. The default output voltage level for these variants is 6.45 V. To set a dierent voltage level change
the resistor values according to Equation 1. VFB = 0.8 V (typ) can be assumed.
R1=R2
VCC OUT
VFB −1
Equation 1 Relationship between feedback resistors and output voltage
A feedforward capacitor CFF and a feedforward resistor RFF are placed for the adjustable variants, see Figure
11. For the fixed output voltage variants TLS412xD0EPVxx RFF, CFF and R2 are not placed. For R1 a resistor of
0 Ω shorts the output voltage directly to the FB pin.
Figure 11 Feedback network for adjustable variants
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2.3.6 Signal adaption
For easy signal adaption, for example connecting probes of an oscilloscope, the PCB oers test points. The
TP_... label of each test point indicates the probed signal. For further information on the mapping between test
points and signals see Schematic. The GND clip of the probe can be attached to the ground clamp as shown in
Figure 12.
Figure 12 Test point and GND clamp example
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3 Schematic and layout
3.1 Schematic
The schematic of the OPTIREG™ switcher TLS412xD0EPVxx demoboard is available in the following variants:
• fixed output voltage variants TLS412xD0EPVxx in HF configuration, see Figure 13
• fixed output voltage variants TLS412xD0EPVxx in LF configuration, see Figure 14
• adjustable variants TLS412xD0EPV in HF configuration, see Figure 15
• adjustable variants TLS412xD0EPV in LF configuration, see Figure 16
Parts not mounted are optional and marked with a red cross.
Figure 13 Schematic for fixed output voltage variants in HF configuration
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Figure 14 Schematic for fixed output voltage variants in LF configuration
Figure 15 Schematic for adjustable variants in HF configuration
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Figure 16 Schematic for adjustable variants in LF configuration
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3.2 Layout
The PCB uses a four layer standard stack-up. The product can also be soldered to double layer boards. However,
four layers oer better thermal characteristics. The configuration on this demoboard is comparable to the 2s2p
thermal interface situation.
Figure 17 Top layer and components
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Figure 18 Internal layer 1
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