Intel I7-900 DEKSTOP SPECIFICATION User manual

Intel®Core™ i7-900 Desktop
Processor Extreme Edition Series
and Intel®Core™ i7-900 Desktop
Processor Series
Specification Update
April 2010
Document Number: 320836-015
Notice: Intel® Core™ i7-900 Desktop Processor Extreme Edition Series and Intel® Core™ i7-
900 Desktop Processor Series may contain design defects or errors known as errata which may
cause the product to deviate from published specifications. Current characterized errata are
documented in this Specification Update.

Intel®Core™ i7 processor
Specification Update
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IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
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PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR
INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR
DEATH MAY OCCUR.
Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
Δ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor
family, not across different processor families. See http://www.intel.com/products/processor_number for details.
Intel® Core™ i7-900 Desktop Processor Extreme Edition Series and Intel® Core™ i7-900 Desktop Processor Series may contain
design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Intel, the Intel logo, Celeron, Pentium, Xeon, Intel SpeedStep, Intel Core, and Core Inside are trademarks or registered
trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2008-2010, Intel Corporation. All rights reserved.

Intel®Core™ i7 processor
Specification Update 3
Contents
Preface ................................................................................................................................. 5
Summary Tables of Changes ................................................................................................... 7
Identification Information ...................................................................................................... 17
Errata.................................................................................................................................. 19
Specification Changes ........................................................................................................... 66
Specification Clarifications ..................................................................................................... 67
Documentation Changes ........................................................................................................ 68

Intel®Core™ i7 processor
Specification Update
Revision History
Revision Description Date
-001 •Initial Release November 2008
-002 •Updated Specification Clarification AAJ1.
•Added Erratum AAJ89 January 2009
-003 •Updated Errata AAJ21, AAJ69
•Added Errata AAJ90-AAJ105 March 11th 2009
-004
•Added D0 stepping information
•Included i7-920 processor conversion to D0 step
•Deleted Erratum AAJ105 and replaced with new erratum
•Added Errata AAJ106-AAJ108
May 13th 2009
-005 •Included Intel® Core™ i7-975 processor Extreme Edition and
Intel® Core™ i7-950 processor June 3rd 2009
-006 •Added Errata AAJ109 - AAJ117 July 15th 2009
-007 •Added Errata AAJ118 - AAJ124 Aug 12th 2009
-008 •Added Errata AAJ125 and AAJ126 September 9th 2009
-009 •Added Errata AAJ127 - AAJ132 October 12th, 2009
-010 •Added Intel® Core™ i7-960 information October 19th, 2009
-011 •Added Errata AAJ133 - AAJ136 November 9th , 2009
-012 •Updated Errata AAJ121 and AAJ126 January, 2010
-013 •Added Errata AAJ137 February 7th, 2010
-014 •Added Intel® Core™ i7-930 information February 28th, 2010
-015 •Added Errata AAJ 138 March 16th, 2010
-016 •Added Errata AAJ 139 April 13th, 2010
§

Preface
Intel®Core™ i7 processor
Specification Update 5
Preface
This document is an update to the specifications contained in the Affected Documents
table below. This document is a compilation of device and documentation errata,
specification clarifications and changes. It is intended for hardware system
manufacturers and software developers of applications, operating systems, or tools.
Information types defined in the Nomenclature section are consolidated into the
specification update and are no longer published in other documents.
This document may also contain information that was not previously published.
Affected Documents
Document Title Document
Number/Location
Intel®Core™ i7-900 Desktop Processor Extreme Edition Series and
Intel®Core™ i7-900 Desktop Processor Series Datasheet Volume 1
http://download.intel.com
/design/processor/datash
ts/320834.pdf
Intel®Core™ i7-900 Desktop Processor Extreme Edition Series and
Intel®Core™ i7-900 Desktop Processor Series Datasheet Volume 2
http://download.intel.com
/design/processor/datash
ts/320835.pdf
Related Documents
Document Title Document
Number/Location
AP-485, Intel®Processor Identification and the CPUID Instruction http://www.intel.com/des
ign/processor/applnots/2
41618.htm
Intel®64 and IA-32 Architectures Software Developer’s Manual
Documentation Changes
http://www.intel.com/des
ign/processor/specupdt/2
52046.htm
ACPI Specifications www.acpi.info

Preface
Intel®Core™ i7 processor
Specification Update
Document Title Document
Number/Location
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 1: Basic Architecture
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A: Instruction Set Reference Manual A-M
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 2B: Instruction Set Reference Manual N-Z
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A: System Programming Guide
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 3B: System Programming Guide
Intel®64 and IA-32 Intel Architecture Optimization Reference Manual
http://www.intel.com/pro
ducts/processor/manuals/
index.htm
Nomenclature
Errata are design defects or errors. These may cause the Intel® Core™ i7 processor
Extreme Edition and Intel® Core™ i7 processor behavior to deviate from published
specifications. Hardware and software designed to be used with any given stepping
must assume that all errata documented for that stepping are present on all devices.
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics, e.g., core speed, L2 cache size, package
type, etc. as described in the processor identification information table. Read all notes
associated with each S-Spec number.
Specification Changes are modifications to the current published specifications. These
changes will be incorporated in any new release of the specification.
Specification Clarifications describe a specification in greater detail or further highlight
a specification’s impact to a complex design situation. These clarifications will be
incorporated in any new release of the specification.
Documentation Changes include typos, errors, or omissions from the current published
specifications. These will be incorporated in any new release of the specification.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon
request. Specification changes, specification clarifications and documentation changes
are removed from the specification update when the appropriate changes are made to
the appropriate product specification or user documentation (datasheets, manuals,
etc.).

Summary Tables of Changes
Intel®Core™ i7 processor
Specification Update 7
Summary Tables of Changes
The following tables indicate the errata, specification changes, specification
clarifications, or documentation changes which apply to the Intel® Core™ i7 processor
extreme edition and Intel® Core™ i7 desktop processor product. Intel may fix some of
the errata in a future stepping of the component, and account for the other
outstanding issues through documentation or specification changes as noted. These
tables uses the following notations:
Codes Used in Summary Tables
Stepping
X: Errata exists in the stepping indicated. Specification Change or
Clarification that applies to this stepping.
(No mark)
or (Blank box): This erratum is fixed in listed stepping or specification change
does not apply to listed stepping.
Page
(Page): Page location of item in this document.
Status
Doc: Document change or update will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Row
Change bar to left of table row indicates this erratum is either new or modified from
the previous version of the document.
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
Specification Updates:

Summary Tables of Changes
Intel®Core™ i7 processor
Specification Update
A = Dual-Core Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor
D = Dual-Core Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor
I = Dual-Core Intel® Xeon® processor 5000 series
J = 64-bit Intel® Xeon® processor MP with 1MB L2 cache
K = Mobile Intel® Pentium® III processor
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel® Pentium® 4 processor
O = Intel® Xeon® processor MP
P = Intel® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology
on 90-nm process technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2
cache versions)
T = Mobile Intel® Pentium® 4 processor-M
U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache
V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA
package
W= Intel® Celeron® M processor
X = Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and
Intel® processor A100 and A110 with 512-KB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus
AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor
Extreme Edition 955, 965
AB = Intel® Pentium® 4 processor 6x1 sequence
AC = Intel® Celeron® processor in 478 pin package
AD = Intel® Celeron® D processor on 65nm process
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm
process
AF = Dual-Core Intel® Xeon® processor LV
AG = Dual-Core Intel® Xeon® processor 5100 series
AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor
Technology

Summary Tables of Changes
Intel®Core™ i7 processor
Specification Update 9
AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop
processor E6000 and E4000 sequence
AJ = Quad-Core Intel® Xeon® processor 5300 series
AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel®
Core™2 Quad processor Q6000 sequence
AL = Dual-Core Intel® Xeon® processor 7100 series
AM = Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® dual-core processor
AO = Quad-Core Intel® Xeon® processor 3200 series
AP = Dual-Core Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® dual-core desktop processor E2000 sequence
AR = Intel® Celeron® processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AT = Intel® Celeron® processor 200 series
AU = Intel® Celeron® Dual Core processor T1400
AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad
processor Q9000 series
AW = Intel® Core™ 2 Duo processor E8000 series and E7000 series
AX = Quad-Core Intel® Xeon® processor 5400 series
AY = Dual-Core Intel® Xeon® processor 5200 series
AZ= Intel® Core™2 Duo processor and Intel® Core™2 Extreme processor on 45-
nm process
AAA= Quad-Core Intel® Xeon® processor 3300 series
AAB= Dual-Core Intel® Xeon® E3110 processor
AAC= Intel® Celeron® dual-core processor E1000 series
AAD = Intel® Core™2 Extreme processor QX9775
AAE = Intel® Atom™ processor Z5xx series
AAF = Intel® Atom™ processor 200 series
AAG = Intel® Atom™ processor N series
AAH =
Intel® Atom™ processor 300 series
AAI = Intel® Xeon® Processor 7400 Series
AAJ = Intel® Core™ i7-900 Desktop Processor Extreme Edition Series and Intel®
Core™ i7-900 Desktop Processor Series
AAL = Intel® Pentium Dual-Core Processor E5000 Series

Summary Tables of Changes
Intel®Core™ i7 processor
Specification Update
No C-0 D-0 Status ERRATA
AAJ1 X X No Fix MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a
DTLB Error
AAJ2 X X No Fix Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled
Breakpoints
AAJ3 X X No Fix MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang
AAJ4 X X No Fix Corruption of CS Segment Register During RSM While Transitioning From
Real Mode to Protected Mode
AAJ5 X X No Fix The Processor May Report a #TS Instead of a #GP Fault
AAJ6 X X No Fix REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data
Size or Lead to Memory-Ordering Violations
AAJ7 X X No Fix Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Exceptions and May Push the Wrong Address
Onto the Stack
AAJ8 X X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values
AAJ9 X X No Fix Premature Execution of a Load Operation Prior to Exception Handler
Invocation
AAJ10 X X No Fix MOV To/From Debug Registers Causes Debug Exception
AAJ11 X X No Fix Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image
Leads to Partial Memory Update
AAJ12 X X No Fix Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
AAJ13 X X No Fix Single Step Interrupts with Floating Point Exception Pending May Be
Mishandled
AAJ14 X X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack
Frame
AAJ15 X X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment Check
Exception
AAJ16 X X No Fix General Protection Fault (#GP) for Instructions Greater than 15 Bytes May
be Preempted
AAJ17 X X No Fix General Protection (#GP) Fault May Not Be Signaled on Data Segment
Limit Violation above 4-G Limit
AAJ18 X X No Fix LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt
Occurs in 64-bit Mode
AAJ19 X X No Fix Performance Monitoring Events for Read Miss to Level 3 Cache Fill
Occupancy Counter may be Incorrect
AAJ20 X X No Fix A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as
Armed
AAJ21 X X No Fix Memory Aliasing of Code Pages May Cause Unpredictable System Behavior
AAJ22 X X No Fix Delivery Status of the LINT0 Register of the Local Vector Table May be Lost
AAJ23 X X No Fix Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately