ZiLOG System 8000 Quick user guide

-
II
II
-
II
III
II
III
II
System 8000™
Bardware Reference Manual
-
III

Zilog
..'. ~
63-3237-04
December 1982
Copyright 1982 by Zilog, Inc. All rights reserved. No part of
this publication may be reproduced, stored in a retrieval system,
or transmitted, in any form or by any means, electronic, mechani-
cal, photocopying, recording, or otherwise, without the prior
written permission of Zilog.
The information in this publication is subject to change without
notice.
Zilog assumes no responsibility for the use of any circuitry
other than circuitry embodied in a Zilog product. No other cir-
cuit patent licenses are implied.
ZILOG

[NOTICE TO OWNER
FEDERAl, COMMUNICATIONS COMMISSION
RADIO FREQUENCY INTERFERENCE
STATEMENT
Warning: This equipment generates, uses, and can radiate radio frequency energy and if not install-
ed and used in accordance with the instructions manual, may cause interference to radio communica-
tions.
As temporarily permitted by regulation it has not been tested for compliance with the limits for
Class Acomputing devices pursuant to Subpart J
of Part 15 of FCC Rules, which are designed to
provide reasonable protection against such interference. Operation
of this equipment in aresidential
area
is likely to cause interference in which case the user at his own expense will be required to take
whatever measures may be required to correct the interference.

SYSTEM 8000 HARDWARE REFERENCE MANUAL
03-3237-011

HRM
Zilog
Preface
HRM
This manual contains the inform$tion necessary to install,
operate, and maintain Zilog's System 8000 Model 21, Model 31
microcomputer. This manual addresses field engineers (FE),
service technicians, and all others who require knowledge of
the hardware aspects of the system.
This manual and the related manuals listed below provide the
technical documentation of the System 8000.
Title
ZEUS System Administrator Manual
ZEUS Utilities Manual
ZEUS Reference Manual
CPU Hardware Reference Manual
Zilog Number
03-3246
03-3196
03-3195
03-3200
System 8000 is a registered trademark of Zilog, Inc.
iii
ZilOg
iii

HRM
iv
Zilog
Zilog
HRM
iv

HRM 2ilog
Table of Contents
HRM
SECTION 1 OVERVIEW............ . . . . . . . . . . . . . . . . . . . . . . . . 1 -1
1.1. System Description 1-1
1.2. Functional Relationships 1-2
1.2.1. CPU Board (CPU) 1-2
1.2.2. Winchester Disk Controller (WDC) 1-3
1.2.3. Storage Module Device Controller (SMDC) .. 1-4
1.2.4. Tape Cartridge Controller (TCC) 1-4
1.2.5. Memory Subsystem 1-4
1. 2. 6. Sec0n dar ySe ria 1 Bo ar ds (SSB) 1- 12
1.3. System Expansion .....•........................ 1-12
SECTION 2 SYSTEM SPECIFICATIONS 2-1
2.1. Introductiorl 2-1
2.2. Electrical Specifications ................•.... 2-1
2.3. Performance Specifications 2-1
2.4. Modules .... '. '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.4.1. I/O Connectors 2-8
2.5. Backplane (ZBI) Pin Assignments : 2-11
SECTION 3
INSTALLATION
3-1
3.1. Introductiofl ........•...••••.•................. 3-1
3.2. Unpacking, Inspection, Reship~ent Procedures .. 3-1
3.2.1. Shipping Container .....•.......•........• 3-1
3.2.2. Unpacking and Inspection Procedures 3-1
3.2.3. Internal Inspection 3-2
3.2.4. Reshipment Procedures ...............•.... 3-6
3.3. Installation Procedures ....•......•........... 3-7
3.3.1. Site preparation .............•........... 3-7
3.3.2. System Interconnection ....•.............• 3-8
3.4. 32 MB Winchester Disk Drive Configurations 3-14
3.4.1. Drive Cabling 3-14
3.4.2. Drive Configuration Procedures .....•..... 3-15
3.4.3. Initial Checkout and Startup Procedure 3-17
3.5. SMD Winchester Drive Configuration 3-18
3.5.1. SMD Disk Addressing ...••....•.•..••....•. 3-18
3.5.2. SMD Disk Status Indicators •.....••.•..... 3-21
3.5.3. SMD Configuration ......•....•............ 3-23
3.5.4. SMD Cabling ....................••.......• 3-25
3.5.5. Head Lock Actuator ...•.•...... ; .........• 3-26
v
2ilog v

HRM Zilog
HRM
3. 5.6. Cable Termination ' 3-27
3.6. Line Printer Installation Procedures 3-28
3.7. System power-Up Diagnostics (SPUD) 3-30
3.8. System Expansion ". 3-35
3.8.1. Installing Additional Terminal Ports 3-35
3.8.2. Adding A Disk Module 3-37
3.8.3. Adding SMD Disk Module #1 to Model 31 3-40
3.8.4. 1Mbyte Memory Array Board
Segment Setting 3-42
SECTION 11 THEORY OF OPERATION 4-1
4 • 1. Ge n era 1 ".... 4-1
L~.2. System Bus.................................... 4-1
4.3. Bus Conventions 4-1
L~ • 4. Bu s Signa1s 4- 2
4.5. Bus Modules oJ............................. 4-9
4.5.1. CPU Module 4-9
4.5.2. Winchester Disk Controller 4-16
4.5.3. Storage Module Device Controller 4-26
4.5.4. Cartridge Tape Controller 4-43
4.5.5. Tape Controller Operation 4-54
4.5.6. Memory Subsystem Controller 4-57
4 • 6. Sy stem Reset It •• , •• 4- 58
4.7. Non-Maskable Interrupts (NMI) 4-58
4 •7 . 1. Ma nua1 NM I4- 62
4. 7 . 2. Po we r- Fa iI NM I .........•............. :..... 4- 62
4.7.3. ECC Memory Error NMI 4-63
4.7.4. 'NMI Identifier 4-63
4~8·. Vectored Inter~upts i. 4-63
4.9. Memory Management Unit (MMU) ....•............. 4-66
4.9.1. MMU Operation (Non-Segmented) 4-66
4.9.2. MMU Operation (Segmented) 4-67
4.9.3. MMU Configurations ....•.............•.•.. 4-67
4.9.4. Break Registers ....................•..... 4-68
4 •9• 5. S ys t em Acce sst 0UserSpace 4- 69
4.9.6. System Segments and Protection 4-70
Sl':C~ION 5 MAINTENANCE................................ 5-1
.. '5.1. Introduction 5-1
5.2. Preventive Maintenance ; 5-1
5 . 3. Ta pe Dr i ve Per i0di c Ma in ten ance ...............' 5- 1
5.3~1. Magnetic Head Cleaning .•...... ~ 5-1
5.3.2. Tape Cleaner Cleaning ......•... ~ ....•.... 5-2
5.3.3. Motor Capstan Cleaning ...•...•.•......... 5-2
5.3.4. Heat Sink, Circuit Board,
Sensor Hole Cleaning ..........••..•......•...... 5-4
5.4. Disk Drive Assembly Cleaning.................. 5-4
vi
Zilog
vi

HRM Zilog
5.5. Disk Drive Mounting .
5 . 6. Dr i ve Ca b1in, g •••••••••••••••••••••••••••••••••
5.7. Disk Power ON Procedure .
5.8. Power Supply Voltages .....•...................
5. 8 . 1. AC In put Vol tag e Ch eck ...........•........
5.8.2. CPU Module' DC Voltage Test .
5.8.3. Disk/Tape Module DC Voltage Test .
5.8.4. Disk/Tape Module (Module 31)
DC Vol tage Test ...........• .- •....................
5.9. System 8000 Monitor , ..........•
5.9.1. Monitor Program Debug Environment .
5 . 9 . 2. Mo nit 0r pr 0gram ..........................•
5.9.3. Monitor Mode Commands .
5.9.4. Download Mode Commands .....•.............
5.9.5. System Parameters ........•...............
5.10. Monitor I/O Procedures .
5.10.1. I/O Pr'ocedures .
5.11. SADIE .. It •••••••••••• ·., ••••••••••••••••••••••••
5. 11. 1. Pu rpo se0f SAD IE .
5.11.2. Organization and principles
of Operation ..•...................................
5.12. SADIE Tape Organization .
5.13. SADIE Program Initialization .
5.14. SADIE Diagnostic Functions .
5.14.1. Console Interactions ••..... 0 •••••••••••••
5.14.2. START and RESET Interactions .
5.15. Command Level Test Functions .
5.15.1. Command Level T:
Choose and run a single TEST . .... A ••••••••••••••
5.15.2. Command Level R:
REPEAT previously loaded test ...•......•.•.... :.' ...
5.15.3. Command Level'L:
Run current tE~st LIST ......••.....•.............
5.15.4. Command Level C:
CHOOSE and run a test list •...•.......••..........
5~15.5. Command Level E:
ED ITt est 1is t~ • -. • '.' • • • • e, • • • • • -. • • .' • ':' '. ~. ~ .• '. • • +' -. ._ i: .•.' •
5.15.6. Command Level D:
HRM
5-5
5-7
5-9
5-9
5-9
5-10
5-11
5-13
5-14
5-14
5-16.
5-16
5-34
5-38
5-41
5-41
5-44
5-44
5-45
5-45
5-46
5-47
5-47
5-50
5-51
5-52
5-55
5-55
5-56
5-57
DISPLAY error log .••...•.....•.......•....•..... 5-61
5.15.7. Command Level A:
Cum ul at i veer r~or log ........•.•.... ~ ". , .. ',~ '. ; .... " ... '~ .. ~.. S~:6·l'·.
5.15.8. Command Level M:
Do Ta pe Ma in ten ance ..•..........•.... ,:. .. . . •. . . . . . "5- 62
5.15.9. Command Level Q:QUIT ..... ~ •.. ~! ••••••••• 5-62
5.16. SADIE Test Line. and Control statem~nts ,. 5-62
5.16.1. SADIE Test List ...••.•...... 'i '., .. e •••••• ,.~ 5-62
5.16.2. Control Statements •.... ~.~ ... ~ .. ~ ..•• ~ .. 5-62
5.17. Using SAD+~ •••••••••• ,_ •••••• '" •••••••••••• ~. '"' 5-64
vii
ZilQg
vii'

HRM Zilog HRM
APPENDIX A SADIE TEST DESCRIPTIONS A-1
APPENDIX B WINCHESTER DISK CONTROLLER COMMANDS B-1
B.'. General ............•...•...•..•....•.......... B-1
B.2. Format/UNIT/ B-1
B• 3. Re ad S-e c tor ••••••••••••••••••••••••••••••••••• B-1
B.4. Write Sector.................................. B-2
B.5. Read Detailed Status/UNIT/ ADDRESS/ B-3
B.6. Restore/UNIT/ B-3
B• 7. Nu 11 •••••••••••••••••••••••••••••••••••••••••• B- 3
B.8. Seek/UNIT/CYLINDER/ 8-4
B.9. Set Strobe/Offset/UNIT/SO/ 8-4
B.10. Set Write Protect/UNIT/SURFACES/ B-4
B.11. Format Read/UNIT/HEAD/CYLINDER/
/SECTOR/ADDRESS/
8-5
B.12. Set Interrupt Address/SECTOR/ 8-5
8.13. Self Test ...•................................ B-5
8.14. Format Verify/UNIT/HEAD/CYLINDER/ 8-6
8.15. Unit Format Verify/UNIT/ •.................... 8-6
B.16. Command Notes 8-6
APPENDIX C CARTRIDGE TAPE ERROR CONDITIONS C-1
C .1. ~General •••••.•....•.••.••.•.•......•.......... C-1
viii
Zilog
viii

HRM
Figure
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
2-1
2-2
2-3
Zilog
List of Illustrations
sy3t em 8aa0 II • • • • • • ;8 •••••••••••••••••
System 8000 CPU Board (CPU) .
System 8000 Winchester Disk Controller .
System 8000 Storage Module
Device Controller (SMDCA) .
System 8000 Storage Module
Device Controller (SMDCB) .•.................
System 8000 Tape Cartridge Controller (TCC) .
System 8000 ECC Controller ••................
1M Byte Memory Array (MEM) ~ .
System 8000, Functional Relationships .
Processor Module Controls and Indicators ....
Mo du leD im ens ion s (W i tho ut Sid ePa neI 3) •••••
Model 21 Processor Module
HRM
1-3
1-5
1-6
1-7
1-8
1-9
1-10
1 -11
1-13
2-6
2-7
I/O Connector Panel 2-8
2-4 Model 31 Processor Module
I/O Connector Panel 2-9
2-5 Backplane Assignments .....•................. 2-14
2-6 Model 31 Backplane Slot Assignments 2-15
3-1 Switch Selectable AC Line Voltages,
Processor Module 3-4
3-2 Switch Selectable ACLine Voltages
Disk/Tape Module ~ .....•............ ·3-6
3-3 Model 21 Connector Identification 3-10
3-4 Model 31 Connector Id.entification 3-11
3-5 Model 21 System Intermodule Cabling 3-12
3-6 Model 31 System Intermodule Cabling 3-13
3-7 FINCH Power and Signal
Connector Orientation .............•....•.... 3-14
3- 8 FINC HAd apt er Bo a rd. .. ..................... .. 3- 16
3-9 Rotary-Arm Shipping Lock Orientation 3-17
3-10 Mode Select Switch Location •................ 3-19
3-11 84 MB SMD Configuration ..............•...... 3-24
3-12 Mounting Positions of SMD Connectors 3-25
3-13 SMD Interface Cabling 3-26
3-14 SMD Mounting Bracket
with Head Lock Actuator ...................•. 3-27
3-15
SMD Cable Terminators ..•.................... 3-28
3-16 EXisting Model 21 and
Expanded System Configurations 3-37
ix
4-1
System 8000, Functional Relationships 4-2
Zilog ix

HRM
l~ -2
L~_ 3
L~ -4
L~ -5
1l-6
1l-7
l~ -8
1~-9
4-10
4-11
4-12
4-13
4-14
4-15
Zilog HRM
CPU Board, Functional Relationships 4-11
Winchester Disk Controller,
Functional Relationships 4-17
Disk Controller Command
Command status (C/S) Registers 4-18
Disk Controller, I/O Space 4~19
SMD
Controller Functional Relationship 4-27
Cartridge Tape Controller
Functional Relationships 4-45
Cartridge Tape Controller
I/O Address Space ' 4-46
Cartridge Tape Controller,
Command Processing 4-56
Memory Subsystem Controller,
Functional Relationships 4-59
Memory Organization 4-59
Byte Translation 4-60
Word Translation •........................... 4-61
Long-Word Translation 4-62
Interrupt Priority Connections 4-66
Location of Parts
Requiring Periodic Cleaning 5-3
FINCH Major Components '... 5-5
Disk Drive Mounting 5-6
SMD Mounting Bracket '. . . .. 5-7
Power Supply Voltage
Test Points, CPU Module 5-12
Voltage Test points,
Finch DC Power Connector 5-12
Voltage Test poin~s,
SMD Power Connector 5-13
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
x
Power Supply Voltage
Adjustments (Model 31)
Zilog
5-14
x

HRM
Table
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
3-1
3-2
3-3
3-4
3-5
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
}.J-16
4-17
xi
Zilog
List of Tables
Electrical Specifications .
System Performance Characteristics .
32MB Winchester Disk Drive
Performance Characteristics .
SMD Performance Characteristics .
Tape
Cartridge Drive
Performance Charactetistics .
I/O Connectors , .
TTY Connector, Pin Assignments .
Printer Connector, Pin Assignments .
ZBI
Backplane Connector Pin Assignments
CPU Board, Connector P2/J21, Slot 1 .
Secondary Serial Board .
Winchester Disk Controller, Connector .
Tape Cartridge Controller, Connector .
Storage Module Device Controller Board A .
Storage Module Device Controller Board B .
System 8000 Memory Bus .
SMD Disk' A.ddressing .
Fault Indicator ' .
SPUD Diagno'stics Error List .
Segment Address Settings
on 1 M By t e Me m0r y .................."....'.'....
Memory Array Jumper Selection ,.' .
Bus Lines - .
ZBI Status Lines, Transaction Coding .
Data Width Codes: Byte, Word, and Long Word.
CPU I/O Bus, Signal Definitions .
CPU Board Jumper Selection .........•...•....
Parallel Printer Output, port A ..•..........
Parallel Printer Input, Port A .
Parallel Printer Data, Port B .
Serial I/O Devices and Channel Assignments ..
Serial Channels and Baud-rate Generators ....
Baud Rate and Primary
Boot Device, Switch U70 .............•.......
I/O Channels and Their Addresses .
Disk Contrc)ller and Disk Drive, .
Command and Command-Status Registers •.......
Jumper Settings
Command & CiS Registers .••..•...•...........
Disk Controller Jumper Settings for Memory .•
Disk Command and Status Words ....•..........
Zilog
HRM
2-1
2-2
2-4
2-5
2-6
2-9
2-10
2-10
2-12
2-16
2-17
2-18
2-19
2-20
2-21
2-22
3-20
3-22
3-32
3-42
3-42
4-3
4~8
4-8
4-9
4-11
4-12
4-12
4-13
4-13
4-14
4-14
4-15
4-20
4-22
4-24
4-25
4-26
xi

HRM
4-18
4-19
4-,20
4-,21
4-22
4-23
4-24
4-25
4-26
Zi10g HRM
ZBI Tape Controller Interface Registers 4-41
Tape Controller Jumper Selection 4-48
Tape Interrupt Vector, Bit Definitio~s 4-50
Host-Tape Controller Commands 4-50
Status Register, Bit Definitions 4-52
Master Interrupt Control 4-53
Tape Controller to Drive Interface Signals .. 4-53
Tape Drive to Controller Interface Signals .. 4-55
Device Priority Scheme 4-65
5-1 Cleaning Schedule 5-1
5-2 Interface Cables 5-8
5-3 Program Status Area 5-40
5-4 System Hardware I/O Port Addresses 5-41
C-1
xii
Cartridge Tape Error Conditions C-1
Zilog xii

HRM
1.1. System Description
Zi log'
SECTION 1
OVERVIEW
HRM
The System 8000 is a multiuser free-standing unit, based on
Zilog's 16-bit Z8001A microprocessor and running the ZEUS
Operating System at 5.5 megahertz. The System 8000 product
line consists of several different models. The Model 21 and
Model 31 are both similar in appearance having four or more
separate stacked modules. The Model 21 contains a 32 MB
Winchester Disk Drive within the Disk/Tape module. The
Model 31 is equipped with an 84 MB Storage Module Drive
(SMD). Both the t-I[odel 21 and Model 31 have a17 MB Car-
tridge Tape Drive and will accomodate additional Disk or
Disk/Tape modules. Figure 1-1 shows the modules that make up
the system.
The top Processor Module controls the system and contains
the the CPU and various system controller boards within its
ten-slot card cage. The system communication is over the
32-bit Z-Bus Backplane Interconect (ZBI). Two I/O panels
located at the re?r of the processor module interconnect
with the lower modules ,I/O panels and provide disk, tape and
terminal communication.
The Disk/Tape module beneath the top module has either a
32-megabyte Winchester 9isk drive or an 84-megabyte SMD and
a 17-megabyte cartridge tape drive. Disk and Tape I/O con-
nectors are provided on the rear I/O panel.
The remaining two modules can be additional Disk/Tape or
Accessory modules that are 'interconnected to the above Disk
and/or Disk/Tape Modules. Terminal distributIon panels for
serial terminal and parallel printer connection can be added
to these modules.
Both the Model 21 and 31 system can be expanded from 8 to 24
users by installing two Secondary Serial Boards (SSB) and
terminal distribution panels.
1 -1
Zilog
1 -1

HRM
Zilog HRM
The basic system contains five or six printed circuit boards
in the ten-slot card cage. These boards (Figures 1-2
through 1-8) are:
the CPU
the Winchester Disk Controller (WDC)
or Storage Module Device Controller Boards A and B
the Cartridge Tape Controller
and the Memory Subsystem
including ~he ECC Controller
and one or more Memory Arrays.
The lower three slots of the card cage are normally dedi-
cated to the memory sUbsystem; with the addition of more
memory boards, the basic system can have a physical memory
of 2 megabytes, not including the small bootstrap memory on
the CPU board. An optional memory configuration uses the
lower five slots of the card cage for amaximum physical
memory of 4 megabytes.
An expansion chassis module will be available that can be
added to the system increasing the number of cards attached
to the bus from 10 to 18. This allows still more options.
1.2. Functional Relationships
The diagram in Figure 1-9 shows the functional relationships
of the boards that make up the basic system. These elements
communicate with one a~other over Zilog's Z-Bus Backplane
Interconnect (ZBI), a high-speed, 32-bit, semisynchronous
bus. The following paragraphs briefly describe the func-
tions of each element on the bus.
1.2.1. CPU Board (CPU): The CPU is the host of the System
8000; it controls the ZBI and terminal communications into
and out of the system. The CPU supports eight serial I/O
ports and a parallel I/O port (Figure 1-9). The serial
ports are compatible with RS232-C. The parallel port, with
the appropriate jumpers inserted, is compatible with the
line printer standards of either Centronics or Data Pro-
ducts.
1-2
Zilog
1-2

HRM
Zilog
Figure 1-1 System 8000
HRM
1.2.2. Winchester Disk Controller (WDC): The disk con-
troller enables the CPU to communicate with up to four 24 or
32 MB Winchester disk drives. An intelligent bus module
with an on-board Z80B microprocessor, the controller can be
polled or interrupt-driven by the CPU. The appropriate
jumper arrangement determines the controller's mode of
operation. The disk is organized into 512-byte sectors. A
single command can cause the transfer of up to 128 512-byte
sectors. In addition, the disk controller uses a full-track
1-3
Zilog
1-3

HRM
Zilog
HRM
buffer which permits the transfer of 24 512-byte sectors in
one disk revolution.
1.2.3. storage Module Device Controller (SMDC): The SMDC
is a high performance controller (1.8 MB/second max. data
rate) linking the system ZBI backplane to the industry stan-
dard storage Module Device (SMD) interface. The SMDC con-
sists of two cards, SMDC A and SMDC B. Card A connects to
the ZBI at the 96-pin board connector P1. It also connects
to the SMD A daisy-chain cable at plug P2. Card B connects
to four SMD B radial cables. All drive connections are
through the P2 backplane connector.
Bit slice processor and sequencer logic control all the
operations of the SMDC. The SMDC can control up to four
eight inch drives that have SMD interface. SMDC features
include packet control, overlapped seek, automatic error
recovery, data buffering, flagged sectors, long writes and
reads, and self-test on power-up or system initialization.
The SMDC can be interrupt driven or operate in the polled
mode to the host when a packet is complete. It gives a com-
plete status report of the SMD and the controller.
1.2.4. Tape Cartridge Controller (TCC): The tape con-
troller is the intelligent interface between the CPU and up
to four cartridge tape drives. A Zilog Z80B microprocessor
controls the operation of the controller. The controller
uses direct-memory access (DMA) to transfer data between the
cartridge tape drive and the CPU. When the CPU wants to
initiate an operation, it sends acommand to the controller.
The controller completes the specified operation and then
interrupt~ the CPU to notify it that the ope~ation is com-
plete.
1.2.5. M4~mory Subsystem: The Memory Subsystem includes an
Error Checking and Correcting (ECC) Controller board and one
or more Memory Array boards.
The ECC Controller can control the operation of up to 4
megabytes of dynamic read/write memory. The data can be
t ran s fer r l~ d as by t es (e ight bit s), wo r ds (1 6 bit s), 0 rIo ng
words (32 bits); the controller translates the width of the
data and places the data in the proper locations. The con-
troller transparently corrects all single-bit errors (soft)
and detects all double-bit errors (hard). The controller
uses a soft-error logging system that counts soft errors in
each 64K-byte block of memory.
1-4
Zilog
1-4

HRM
Zilog
HRM
Z8001A
MICROPROCESSOR
CONSOLE BAUD RATE
SELECTOR SWITCH
AND BOOT DEVICE
3MEMORY
MANAGEMENT
UNITS
SEGMENTED/NIDN·SEGMENTED
OPERATING SYSTEM
CONFIGURATICIN JUMPERS
E1-E12
rEST POINTS
PRINTER JUMPERS
E16,17,18
BAUD
RATE
GENERATORS
4PROM
MONITORS
PARALLEL
PORT
8SERIAL I/O
CHANNELS
Figure 1-2
1-5
System 8000 CPU Board (CPU)
Zilog
1-5