Intel iSBC 432/100 Quick user guide

inter
iSBC 432/100™
Processor Board
Hardware Reference Manual
PN 171820-001

I I
11
I
iSBC 432/100™
PROCESSOR BOARD
HARDWARE REFERENCE MANUAL
Manual Order Number: 171820-001
Copyright© 1981 Intel Corporation
Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051
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ii
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lntde1i,ion
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IC!:-
iSHC
PRO\IPT
iCS iSHX
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I ihrrir'.·· \h1naL~er
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and the combination of ICE. iCS. iR\1X. iSBC. iSBX, l\1CS. or R\1X and a numerical suffix.

PREFACE
This manual contains general information, installation, programming information,
and principles
of operation for the Intel iSBC 432/ 100 Processor Board. Additional
hardware/ architectural information pertaining to the iSBC 432/ 100 board is
available in the following documents:
• iAPX 432 General Data Processor Architecture Reference Manual, Order No.
171860-001.
• Intel 8251 Universal Synchronous/Asynchronous Receiver/Transmitter,
Appiication Note AP-i6.
• Intel Multibus Specification, Order No 9800683.
• Intel Multibus Interfacing, Application Note AP-28.
Introductory iAPX 432 information, if required, is contained in the following
documents:
• The iAP X 432 Object Primer, Order No. 171858-001.
• Introduction to the iAPX 432 Architecture, Order No. 171821-001.
• GettingStartedontheintellec432/JOO, OrderNo.171819-001.
• Object Builder User's Guide, Order No. 171859-001.
• Object Programming Language User's Manual, Order No. 171823-001.
iii

. ~
n
CHAPTER 1
GENERAL INFORMATION PAGE
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . l-1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . l-l
Equipment Supplied . . . . . . . . . . . . . . . . . . . . . . . . . . . l-2
Equipment Required . . . . . . . . . . . . . . . .
.. . . . . . . . . . . l-2
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . !-2
CHAPTER2
PREPARATION FOR USE
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-l
Unpacking and Inspection . . . . . . . . . . . . . . . . . . . . . . 2-1
Installation Considerations . . . . . . . . . . . . . . . . . . . . . 2-l
User Furnished Components . . . . . . . . . . . . . . . . . . . . 2-2
Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Cooling Requirements . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
1/0 Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Multibus Bus Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Multibus Bus Configuration . . . . . . . . . . . . . . . . . . . . 2-4
Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Serial Priority Resolution . . . . . . . . . . . . . . . . . . . . . . . 2-4
Parallel Priority Resolution ..................... 2-l l
Serial 1/0 Cabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Board Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
CHAPTER3
PROGRAMMING INFORMATION
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-l
Memory Addressing and Access . . . . . . . . . . . . . . . . .
3-1
1/0 Addressing and Access . . . . . . . . . . . . . . . . . . . . . 3-1
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-l
8251A USART Programming . . . . . . . . . . . . . . . . . . .
3-1
Mode Instruction Format . . . . . . . . . . . . . . . . . . . . . 3-1
Sync Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Command Instruction Format . . . . . . . . . . . . . . . . . 3-4
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
CONTENTS
PAGE
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Data Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
8253A PIT Programming . . . . . . . . . . . . . . . . . . . . . . . 3-5
Mode Control Word and Count . . . . . . . . . . . . . . . 3-6
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Counter Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Clock Frequency/Divide Ratio Selection . . . . . . . . 3-9
Synchronous Mode ........................ 3-9
Asynchronous Mode ....................... 3-9
iSBC 432/ 100 Control and Status Registers . . . . . . . . 3-10
CHAPTER4
PRINCIPLES OF OPERATION
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 4-l
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2
iAPX 432 Processor . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Data Transfer State Machine . . . . . . . . . . . . . . . . . . 4-4
Multibus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Serial 1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Parallel 1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Circuit Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
iAPX 432 General Data Processor . . . . . . . . . . . . . 4-8
Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Data Transfer State Machine . . . . . . . . . . . . . . . . . . 4-8
Multibus Interface ........................... 4-11
1/0 Operation .............................. 4-14
CHAPTERS
REFERENCE INFORMATION
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Replaceable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Schematic and Parts Location Diagrams . . . . . . . . . . 5-1
Service and Repair Assistance . . . . . . . . . . . . . . . . . . . 5-1
v

TABLE
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
FIGURE
1-1
2-1
2-2
2-3
2-4
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
vi
TITLE PAGE
iSBC 432/ 100 Specifications . . . . . . . . . . . . 1-2
Connector Details . . . . . . . . . . . . . . . . . . . . . 2-1
Jumper Selectable Options . . . . . . . . . . . . . . 2-2
Multibus Connector P1Pin Assignments . . 2-5
Multibus Signal Functions -. . . . . . . . . . . . . . 2-6
iSBC 432/ 100 DC Characteristics . . . . . . . . 2-7
iSBC 432/ 100 AC Characteristics
(Master Mode) . . . . . . . . . . . . . . . . . . . . . .
2-8
iSBC 432/ 100 l/O Access
AC Characteristics . . . . . . . . . . . . . . . . . . 2-8
TITLE PAGE
iSBC 432/ 100 Processor Board
Bus Exchange Timing (Master Mode) .... .
I/O Access Timing (Read/Write) ....... .
Serial Priority Resolution Scheme
....... .
Parallel Priority Resolution Scheme ..... .
USART Synchronous Mode Instruction
Word Format
...................... .
USART Synchronous Mode Transmission
Format
........................... .
USART Asynchronous Mode Instruction
Word Format
...................... .
USART Asynchronous Mode Transmission
Format
........................... .
USART Command Instruction Word
Format
........................... .
Typical USART Initialization and Data
I/O Sequence ...................... .
USART Status Read Format
PIT Mode Control Word Format ....... .
1-1
2-9
2-10
2-10
2-11
3-3
3-3
3-3
3-3
3-4
3-5
3-6
3-7
TABLE
2-8
2-9
3-1
3-2
5-1
5-2
TABLES
TITLE PAGE
Serial l/O Connector J1 Pin Assignments 2-12
Connector J1 vs RS-232-C Pin
Correspondence . . . . . . . . . . . . . . . . . . . . . 2-12
iSBC 432/ 100 l/O Address Assignments . . 3-2
PIT Count Value vs. Rate Multiplier for
Each Baud Rate . . . . . . . . . . . . . . . . . . . . . 3-10
Replaceable Parts . . . . . . . . . . . . . . . . . . . . .
5-2
List of Manufacturers' Codes . . . . . . . . . . . 5-3
ILLUSTRATIONS
FIGURE
TITLE
PAGE
3-9
3-10
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
5-1
5-2
PIT Programming Sequence Examples 3-8
PIT Counter Register Latch Control Word
Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-9
iSBC 432/ 100 Processor Board Functional
Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2
iSBC 4321100 Processor Board Block
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3
Two-Phase Overlapped Processor Clock . . 4-3
24-Bit Processor Physical Address to 20-Bit
Multibus Address Conversion . . . . . . . . .
4-4
iSBC 432/ 100 Data Transfer Routing
to/from the Multibus Bus . . . . . . . . . . . . 4-5
Typical Processor Write Cycle Timing . . . . 4-9
Typical Processor Read Cycle Timing . . . . 4-9
Eight--Bit Transfer Specification Opcode .. 4-10
Data Transfer State Machine State
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-12
iSBC 432/100 Parts Location Diagram . . . 5-5
Schematic Diagram . . . . . . . . . . . . . . . . . . . . 5- 7

1.1 INTRODUCTION
The iSBC 432/100 Processor Board is a Multibus-
compatible
implementation of the iAPX 432 Micro-
mainframe, a 32-bit VLSI microprocessor. This
board is designed to operate as a Multibus master in
Intellec microcomputer systems. The iSBC 432/100
board contains an iAPX 432 microprocessor, a serial
communications interface, programmable timers,
Multibus
control logic, and bus expansion drivers for
interfacing with other Multibus-compatible boards.
1.2 DESCRIPTION
The iSBC 432/ 100 Processor Board (figure 1-1) is
controlled by an iAPX 432 General Data Processor
(GDP).
The GDP consists of two VLSI components:
the 43201
Instruction Decode Unit and the 43202
Instruction Execution Unit. The GDP's instruction
set supports a wide range
of data addressing modes
and
data manipulation operations, as well as highly
efficient
and secure protection mechanisms. The
iSBC 432/100 board accesses the Multibus system
bus for all
memory and 1/0 operations.
CHAPTER 1
GENERAL INFORMATION
An RS-232-C compatible serial 110 port, controlled
by an Intel 8251A
USART (Universal Synchronous/
Asynchronous Receiver /Transmitter), operates with
standard CRT terminals at baud rates from 110 to
19.2K
bits/second. The USART is individually pro-
grammable for
operation in many synchronous and
asynchronous serial data transmission formats
(including IBM Bi-sync). In operation, most
transmission characteristics (e.g., character length,
parity,
and baud rate) are programmable.
In both the synchronous and asynchronous modes,
the serial 110 port features half- or full-duplex,
double
buffered transmit and receive capability. In
addition,
USART error detection circuits can check
for parity, overrun, and framing errors. The USART
transmit and receive clocks are supplied by a
programmable baud rate generator. The RS-232-C
control lines, serial
data lines, and signal ground lines
are
brought out to a 26-pin edge connector (in the
upper right corner of the board) that mates with flat
or
round cable (through a standard board edge
connector).
Figure 1-1. iSBC 432/ 1 OO'M Processor Board 171820-1
1-1

General Information
Three programmable 16-bit interval timers are pro-
vided by
an Intel 8253 Programmable Interval Timer
(PIT). All three timers are reserved for processor
time base generation
and serial I/O baud rate genera-
tion. Additional
on-board l/O registers, containing
processor control
and status information, may be
accessed from the Multibus bus.
The iSBC 432/100 board provides full Multibus arbi-
tration
control logic. This control logic allows up to
three bus masters to share the Multibus bus in serial
(daisy-chain) fashion
or up to 16 bus masters to share
the Multibus bus using
an external parallel priority
resolution network.
The Multibus aribtration logic
operates synchronously with the bus clock, which
is
derived from another Multibus master or generated
by customer supplied logic. (The iSBC 432/100
board does not generate the bus clock signal.) Data is
transferred by means of a handshake between the
controlling master
and the addressed bus module.
This arrangement allows different speed controllers
to share resources
on the same bus, and transfers via
the bus proceed asynchronously. The transfer speed
is dependent on the transmitting and receiving
devices only. This design prevents slower master
modules from being handicapped in their attempts to
iSBC 432/100
gain control of the bus, but does not restrict the
speed
at which faster modules can transfer data over
the same bus.
1.3 EQUIPMENT SUPPLIED
The following items are supplied with the iSBC
432/ 100 Processor Board:
a. Schematic diagram, drawing no. 171773
b. Assembly drawing, drawing no. 171826
1.4 EQUIPMENT REQUIRED
The iSBC 432/ 100 Processor Board is designed to
operate in
an Intellec 800, Intellec Series II, or
Intellec Series III Microcomputer Development
System.
1.5 SPECIFICATIONS
Specifications of the iSBC 432/ 100 Processor Board
are listed in table 1-1.
Table 1-1. iSBC 432/100™ Specifications
Word Size
Instruction:
Variable, 6 bits to 271 bits.
Data:
8, 16, 32, 64, or 80 bits.
Memory Addressing
Physical: 1
Megabyte RAM, ROM, or EPROM.
Virtual: 2
40
bytes
Serial Cojllmunications
Synchronous:
5-, 6-, 7-,
or 8-bit characters. One or two sync characters.
Automatic sync insertion.
Asynchronous:
5-, 6-, 7-, or 8-bit characters. Break character generation. 1, 11/2, or
2 stop bits. False start bit detection.
Sample Baud Rate:
Frequency
1 Baud Rate (Hz)2
(kHz, software selectable)
Synchronous
Asynchronous
16
64
307.2
-
19200 4800
153.6
-
9600
2400
76.8
-
4800
1200
38.4 38400 2400 600
19.2 19200
1200 300
9.6 9600 600
150
4.8
4800 300
75
2.4
2400
150
-
1.76
1760 110 -
1-2

iSBC 432/100 General Information
Table 1-1. iSBC 432/100™ Specifications (Cont'd.)
Interval Timer and Baud Rate Generator
Output Frequencies:
1/0 Addressing
Interface Compatibility
Serial 1/0:
Interrupts:
Compatible Connectors/Cables:
Environmental Requirements:
Relative Humidity:
Physical Characteristics
Width:
Height:
Thickness:
Weight:
Power Requirements
+
5V 5% at 4.5 A
+12V 5% at 40 mA
-12V
5% at 40 mA
Notes.
1. Frequency selected by 1/0 writes of appropriate 16-bit fre-
quency factor into
8253 PIT registers.
2. Baud rates shown here are only a sample subset of possible
software programmable rates available. Any frequency from
37.5 to 614.4 kHz may be generated utilizing the on-board
crystal oscillatorand 16-bit PIT.
1.228 MHz± 0.1% (.82 micmsecond nominai period).
Rate Generator:
37.5 Hz to 614.4 kHz
Process Clock:
3.25 microseconds to 58.25 minutes. (cascaded
timers)
On-board 1/0 devices recognize
an 8-bit 1/0address. iSBC 432/100
local accesses are translated to Multibus 1/0accesses.
EIA standard RS-232-C signals provided and supported:
Clear to Send
Request to Send
Data Set Ready
Transmitted Data
Received Data
Data Terminal Ready
The 432 CPU can generate a single interrupt on the Multibus
INT5/, INT6/, orINT7/ lines.
Refer to Table 2-1 for compatible connector details. Refer to
paragraph
2-15 for recommended types and lengths of 1/0 cables.
0° to 50° C (32° to 122° F)
To 90% without condensation.
30.48 cm (12.00 inches)
17.15 cm (6.75 inches)
1.52 cm (0.6 inches)
453.6 gm (16 ounces)
1-3

2.1 INTRODUCTION
This chapter provides instructions for configuring
the iSBC
432/ 100 Processor Board for operation in a
user-defined
environment. It is advisable that the
contents of Chapters 1 and 3 be fully understood
before beginning the configuration and installation
procedures described in this
chapter.
2.2 UNPACKING AND INSPECTION
Inspect the shipping carton immediately upon receipt
for evidence
of mishandling during transit. If the
shipping
carton is severely damaged or waterstained,
request
that the carrier's agent be present when the
carton is opened. If the carrier's agent is not present
when the
carton is opened and the contents of the
carton are damaged, keep the carton and packing
material
for the agent's inspection.
CHAPTER 2
PREPARATION FOR USE
For repairs to a product damaged in shipment, refer
to the
customer letter contained in the shipping car-
ton. It is suggested that salvageable shipping cartons
and packing material be saved for future use in the
event the
product must be reshipped.
2.3 INSTALLATION
CONSIDERATIONS
The iSBC 432/ 100 board is designed for use as a bus
master in
an lntellec 800, Intellec Series II, or Intellec
Series III Microcomputer Development System.
Important criteria for installing and interfacing the
iSBC 432/ 100 board in this configuration are
presented in the following
paragraphs.
Table 2-1. Connector Details
No. of
Pairs/
Centers Connector
Intel®
Function
Pins
(inches)
Type Vendor Vendor Part No. Part No.
Serial 13/26
0.1 Flat Crimp 3M 3462-0001 iSBC 955
1/0 AMP
88106-1 Cable
Connector
ANSLEY
609-2615
Set
SAE SD6726 SERIES
Serial 13/26
0.1
Soldered
Tl H312113 N/A
1/0 AMP 1-583485-5
Connector
Serial 13/26
0.1
Wirewrap1
Tl H311113
N/A
1/0
Connector
Multibus 43/86 0.156 Soldered1
CDC3
VPB01E43DOOA1
N/A
Connector
MICRO PLASTICS MP-0156-43-BW-4
ARCO AE443WP1 LESS EARS
VIKING 2VH43/1AV5
Multibus 43/86 0.156
Wirewrap 1,2
CDC3
VFB01E43DOOA1 or
MDS 985*
Connector
CDC3
VP 801E43AOOA1
VIKING 2VH43/1AV5
NOTES:
1. Connector heights are not guaranteed to conform to OEM packaging requirements.
2. Wirewrap pin lengths are not guaranteed to conform to OEM packaging requirements.
3. CDC VPB01 ..., VPB02..., VP804..., etc. are identical connectors with different electroplating thickness or metal
surfaces.
*"MOS" is an ordering code only, and is not used as a
product name or trademark. MDS® is a registered
trademark of Mohawk Data Sciences Corp.
2-1

:Preparation for Use
2.4 USER FURNISHED COMPONENTS
A serial 1/0 connector (see ·table 2-1) and RS-232-C
cable
must be installed to interface the processor
board to a CRT terminal.
2.5 .POWER REQUIREMENTS
The iSBC 432/ 100 board requires +5V, + l2V, and
- l
2V power supplies at the currents listed in table
1-1.
2.6 COOLING REQUIREMENTS
The iSBC 432/100 board dissipates 336.5 gram-
calories/minute (1.33 BTU/minute), and adequate
circulation must be provided to prevent a
temperature rise above 50° C (122° F). Intellec
systems include fans to provide adequate intake and
exhaust
of ventilating air.
iSBC 432/100
2.7 PHYSICAL DIMENSIONS
Physical dimensions of the iSBC 432/ 100 board are
as follows:
a. Width: 30.48 cm (12.00 inches)
b. Height:
17 .15 cm (6. 75 inches)
c. Thickness: 1.52 cm (0.6 inch)
2.8 JUMPER CONFIGURATION
The iSBC 432/ 100 design includes a variety of
jumper-selectable options that allow the user to
configure the
board for his/her particular applica-
tion. Table 2-2 summarizes these options
and lists the
grid reference locations
of the jumpers as shown in
figure 5-1 (parts location diagram) and figure 5-2
(schematic diagram).
Table 2-2. Jumper SelectableOptions
Fig. 5-1 Fig. 5-2
Function Grid Ref. Grid Ref. Description
1/0 Base Address 1B6 2C5
Selects the Multibus base address for on-board 1/0 ports. The
default jumper (79-80*) configures the 110 addresses to 1X. The
value of X is
determined by the 1/0 port to be addressed (refer
to table 3-1 ). Other base addresses are selected as follows:
address jumper
7X
67-68
6X 69-70
5X 71-72
4X
73-74
3X
75-76
2X 77-78
1X
79-80*
XACK/Timing
1B8 3A6
The factory default jumper 54-55* provides the correct XACK
delay to read and write on-board 1/0 ports. This jumper should
not be modified.
8/16-bit bus access
1B4 7C2
Selects 8- or 16-bit Multibus transfer mode. The default jumper
configuration (46-47*) selects the ·a-bit transfer mode. In this
I mode, all Multibus accesses are single-byte accesses. By
jumpering
45-46, the 16-bit Multibus mode is selected.
Bus Lock 187 2A6
Default jumper 65-66* locks the Multibus bus during each GDP
data transfer. A GDP initiated data transfer may require as
many as ten Multibus transfers in the 8-bit mode. To allow
other masters
to acquire the bus during GDP transfers, remove
this jumperand connect
64-65.
Processor ID
1C8
2C4 Default jumpr 33-34* permits the GOP to read its processor ID
from an on-board register at 1/0 address OOH. This jumper
should not be removed.
InterruptSignals 1
B7 4D1
A board generated interrupt may be routed to one of the
Multibus interrupt lines (INT5/, INT6/,
or INT?/). Default jumper
J
86-87* routes the interrupt signal to INT6/. If another interrupt
line is desired. remove this jumper and connect 88-89 (INT?/) or
90-91 (INT51).
-~
•Default jumper configured at the factory
2-2

iSBC 432/100 Preparation for Use
Table2-2. Jumper Selectable Options (Cont'd.)
Function Fig.
5-1 I Fig. 5-2 I
Grid Ref. Grid Ref.
Bus Arbitration 1B7
2A4
UserSelectable Inputs 1B6
4C5
GDP Initialization 1C5 4D6
Serial 1/0 Port
1C4
3C2
*Default jumper configured at the factory.
Study table 2-2 carefully while making reference to
figures
5-1 and 5-2. If the default (factory con-
figured)
jumper configuration is appropriate for a
particular function, no further action
is required for
that function. If, however, a different configuration
is required, remove the default jumper(s) and/ or
install optional jumper(s) as specified. For most
options, the
information in table 2-2 is sufficient for
proper configuration. Additional information, where
necessary,
is contained in the following paragraphs.
2.9 1/0 ACCESS
All on-board 1/0 devices are accessible only from the
Multibus bus.
The selection of an 1/0 base address is
performed by the user as described in table 2-2. By
moving the address selection jumper, the most
significant
four 1/0 address bits are fixed as:
Description
Default jumper 81-82* routes the Bus Priority Out signal BPRO/
to the Multibus bus. (Refer to table 2-4.) This jumper should
always be connected when the processor board is inserted in
an lntellec system or used with a serial priority bus resolution
scheme.
The Common Bus Request signal (CBRQ) from the Multibus
bus is not presently used.
Three user selectable jumpers are available for system
confiQuration inputs. These three inputs are read throuqh the
processor status port. These inputs·appear on the
three most
significant data lines as follows:
Port Associated
Data Bit Jumper
=0
=1
07 40-41 * remove
jumper
install jumper*
06 38-39* remove jumper install jumper*
05
36-37*
remove jumper
install jumper*
In normal operation (default jumper 43-44*), the GDP is
initialized when a Multibus master writes an initialization
pattern to the processor control 1/0 port and also when the
Multibus INITI signal is activated. The GDP is held in the
initialized state until the Multibus master subsequently
rewrites the 110 port.
The serial 1/0 port has three
jumper selectable options.
Jumper
31-32 provides 1/0 loopback for testing. This jumper
should not be connected in normal operation; 27-28* provides
an automatic data set ready response when the data terminal
ready signal is asserted; 29-30* provides an automatic clear-to-
send response when the request-to-send signal is asserted.
Userconfiguration of these jumpers is terminal dependent.
A7 A6
AS A4 Hex Jumper
0 0 0 1 1
79-80
0 0 1 0 2
77-78
0 0 1 1 3
75-76
0 1 0 0 4
73-74
0 1 0 1 5
71-72
0 1 1 0 6
69-70
0 1 1 1 7
67-68
The least significant four bits of the 1/0 address are
determined by the individual
1/0 port; a list of 1/0
addresses and corresponding I/O ports is given in
table 3-1. The processor ID register always resides at
Multibus 1/0 address OOH and cannot be relocated.
Note
that all Multibus 1/0 addresses generated by
the iSBC 432/ 100 board are even, i.e., the least-
significant address bit is always zero. In addition, all
Multibus addresses (110
or memory) are generated
using the
on-board off set register, as discussed in
paragraph 4-5.
2-3

Preparation for Use
2.10 MULTIBUS BUS ACCESS
The iSBC 432/ 100 board contains no local memory.
All system memory resides
on separate Multibus
modules. Both system
memory and all 1/0 ports
(including
1/0 ports contained on the processor
board) must be accessed via the Multibus bus. Each
GDP access specifies either a local address or a
physical address (refer
to the discussion in Chapter
3). Local address requests are translated into
Multibus
1/0 commands; physical address requests
are translated into Multibus memory commands.
The iSBC
432/ 100 board is designed to operate with
either 8-bit
or 16-bit memory modules. A user-
selectable
jumper (table 2-2) is provided to select the
8-bit
or 16-bit Multibus transfer mode. (The board is
factory-configured to operate in the 8-bit mode.)
GDP memory accesses may require the transfer of
one to ten data bytes over the Multibus bus. In the 8-
bit mode, all GDP memory requests initiate a series
of single-byte read or write accesses. In the 16-bit
mode, all
GDP multibyte memory requests that
originate
on even byte boundaries are satisfied by a
series
of double-byte (16-bit) read or write accesses.
All
other accesses are performed in the same manner
as are accesses in the 8-bit mode.
When operating with iSBC/MDS* 016
16K
RAM memory modules, the 8-bit mode must
be used. The 16-bit
mode may be used with
iSBC/MDS 032/048/064 RAM memory
modules.
As mentioned earlier, a single
GDP memory request
may require the transfer
of ten data bytes over the
Multibus bus. In
order to shorten the overall time
required for these
data transfers, the bus may be
locked from the beginning
of the first transfer until
the
GDP memory transfer has been completed.
Locking the bus eliminates the time required to·
acquire and release the bus for each byte data
transfer. This "bus lock" feature, which results in
higher processor
throughput, is user selectable as
described in table 2-2. The processor
board is shipped
with the
"bus lock" feature enabled.
The bus lock provision
cannot be enabled in
systems with double-density diskette
controllers and 8-bit memory if the diskette
controller will operate simultaneously with
· the iSBC 432/100 board.
*"lllDS" is an ordering code only, and is not used as a
product name or trademark.
MOS® is a registered
trademark of Mohawk Data Sciences Corp.
2-4
iSBC 432/100
2.11 MULTIBUS BUS CONFIGURATION
For system applications, the iSBC 432/ 100 board is
designed for installation in a standard Multibus
backplane (e.g.,
an Intellec Microcomputer Develop-
ment System). Multibus signal characteristics and
methods
of implementing a serial or parallel priority
resolution scheme for resolving bus contention in a
multiple bus master system are described in the
following paragraphs.
Always
turn off the system power supply
before installing
or removing any board
from the backplane. Failure to observe this
precaution can cause damage to the
board.
2.12 SIGNAL CHARACTERISTICS
As shown in figure 1-1, connector P1 interfaces the
iSBC 432/100 board to the Multibus bus. The pin
assignments for this 86-pin connector are listed in
table
2-3 and descriptions of the signal functions are
provided in table 2-4.
The de characteristics
of the iSBC 432/ 100 bus inter-
face are provided in table 2-5. The ac characteristics
of the iSBC 432/ 100 board when operating in the
master mode
and slave mode are provided in tables
2-6
and 2- 7, respectively. Bus exchange timing
diagrams are provided in figures
2-1 and 2-2.
2.13 SERIAL PRIORITY RESOLUTION
In a multiple bus master system, bus contention can
be resolved by implementing a serial priority resolu-
tion scheme as shown in figure 2-3. Due to the prop-
agation delay
of the BPRO/ signal path, this scheme
is limited to a maximum of three bus masters capable
of acquiring and controlling the Multibus bus. In the
configuration shown in figure 2-3, the bus master
installed in slot J2 has the highest priority
and is able
to acquire control
of the bus at any time because its
BPRN/ input is always enabled (tied to ground).
If the bus master in slot J2 desires control of the
Multibus bus, it drives its BPRO/
output high and
inhibits the BPRN/ input to all lower-priority bus
masters. When finished using the bus, the J2 bus
master pulls its
BPRO/ output low and gives the J3
bus master the opportunity to take control of the
bus.
If the J3 bus master does not desire to control
the bus
at this time, it pulls its BPRO/ output low
and gives the lowest priority bus master in slot J4 the
opportunity to assume control
of the bus.

iSBC 4321100 Preparation for Use
Table 2-3. Multibus™ Connector Pl Pin Assignments
Pin* Signal Function Pin* Signal
Function
1 I GND \ AA
ADRF/ \
I 1
Ground
....
2 GND
45 ADRC/
3 +5V
46 ADRD/
4 +5V
47 ADRA/
5 +5V
48
ADRB/
6 +5V
Power input
49 ADR8/
7 +12V
50 ADR9/
8 +12V
51
ADR6/ Address bus
9
-5V
52 ADR7/
10
-5V
53
ADR4/
11
GND
l
Ground
54 ADR5/
1"1 I
GND
I r::r::
ADR2/
1£.
,
.J.J
13 BCLK/ Bus Clock 56 ADR3/
14 INIT/ System Initialize
57 AORO/
15 BPRN/
Bus Priority In
58
ADR1i
16 BPRO/
Bus Priority Out 59 DATE/
17 BUSY/
Bus Busy 60 DATF/
18
BREQ/ Bus Request 61 DATC/
19 MRDC/ Memory Read Command 62
DATO/
20
MWTC/ Memory Write Command 63 DATA/
21
IORC/
1/0 Read Command
64 DATB/
22
IOWC/ 1/0 Write Command
65
OATS/
23
XACK/
Transfer Acknowledge 66 DAT9/ Data
Bus
24 INH1/ Inhibit RAM
67 DAT6/
25
68
DAT?/
26
69
DAT4/
27 BHEN/ Byte High Enable
70 DAT5/
28 ADR10/ Address bus bit 10 71 DAT2/
29 CBRQ/ Common Bus Request 72 DAT3/
30 AOR11 / Address bus bit 11 73
DATO/
31 CCLK/ Constant Clock 74 DAT1/
32 ADR12/ Address bus bit 12 75 GND }
Ground
33
INTA/ Interrupt Acknowledge
76 GND
34 ADR13/ Address bus bit 13 77
35 INT6/ Interrupt request on levern 78
36 INT?/ Interrupt request on level 7 79
-12V
37 INT4/ Interrupt request on level 4
80
-12V
38
INT5/ Interrupt request on level 5 81
+5V
Power input
39 INT2/ Interrupt request on level 2
82 +5V
40 INT3/ Interrupt request on level 3
83
+5V
41 INTO/ Interrupt request on level 0 84 +5V
42 INT1 I Interrupt request on level 1
85
GND }
Ground
43 ADRE/
86
GND
*All odd-numbered pins (1,3,5... 85) are on component side of the board. Pin 1 is the left-most pin when viewed from the
component side of the board with the extractors at the top. All unassigned pins are reserved.
2-5

Preparation for Use
iSBC 432/lQO
Table 2-4. Multibus™ Signal Functions
Signal Functional Description
ADRO/ADRF/ Address. These 20 lines transmit the address of the memory location or 1/0 port to be
AOR10/-ADR13/ accessed. For memory access,
ADRO/ (when active low) enables the even byte bank
(DATO/-DAT71) on the Multibus bus; i.e., ADRO/ is active low for all even addresses. ADR13/
is the most significant address bit.
BCLK/ Bus Clock. Used to synchronize the bus contention logic on all bus masters. BCLK/ is
approximately
10 MHz with a worst case 35/65 percent duty cycle.
BHENI Byte High Enable. When active low, enables the odd byte bank (DAT8/-DATFI) onto the
Multibus bus.
BPRN/ Bus Priority In. Indicates to a particular bus master that no higher priority bus master is
requesting use ofthe bus. BPRN I is synchronized with BCLK/.
BPRO/
Bus Priority Out. In serial (daisy chain) priority resolution schemes, BPRO/ must be
connected to the BPRN I input ofthe bus master with the next lower bus priority.
BREQ/ Bus Request.
In parallel priority resolution schemes, BREQ/ indicates that a particular bus
master requires control of the bus for one or more data transfers. BREQ/ is synchronized
with BCLK/.
BUSY/ Bus Busy. Indicates that the bus is in use and prevents all
other bus masters from gaining
control of the bus. BUSYI is synchronized with BCLK/.
CBRQ/ Common Bus Request. Indicates that a bus master wishes control of the bus but does not
presently have control. As soon
as control of the bus is obtained, the requesting bus con-
troller raises the CBRQ/ signal.
CCLK/ Constant Clock. Provides a clock signal of constant frequency for use by other system
modules. CCLK/ is approximately 10 MHz with a worst case 35/65 percent duty cycle.
DATO/-DATF/ Data. These
16 bidirectional data lines transmit data to, and receive data from, the
addressed memory location
or 1/0 port. DATF/ is the most-significant bit. For data byte
operations, DATO/-DAT7/ is the even byte and DAT8/-DATFI is the odd byte.
INH1/ Inhibit RAM. For system applications, allows
RAM addresses to be overlaid by ROM IPROM
or memory mapped 1/0devices.
INIT/ Initialize. Resets the entire system to known internal state.
INTA/ Interrupt Acknowledge. This signal is issued in response to
an interrupt request.
INTO/-INT7/ Interrupt Request. These eight lines transmit Interrupt Requests to the appropriate
interrupt handler.
INTO has the highest priority.
IORC/ 1/0 Read Command. Indicates that the address of
an 1/0 port is on the Multibus address
lines, and that the output of that port is to be read (placed) onto the Multibus data lines.
IOWC/ 1/0 Write Command. Indicates that the address of
an 1/0 port is on the Multibus address
lines, and that the contents on the Multibus data lines are to be accepted by the addressed
port.
MRDC/ Memory Read Command. Indicates that the address of a memory location is on the
Multibus address lines, and that the contents of that location are to be read (placed) on the
Multibus data lines.
MWTC/ Memory Write Command. Indicates that the address of a
memory location is on the
Multibus address lines, and that the contents on the Multibus data lines are to be written
into that location.
XACK/ Transfer Acknowledge. Indicates that the address memory location has completed the
specified read
or write operation. That is, data has been placed onto, or accepted from, the
Multibus data lines.
2-6

iSBC 432/100 Preparation for Use
Table 2-5. iSBC 432/100™ DC Characteristics
r l
Parameter
l
Test
I l
Signals
Symbol Description
Conditions Min. Max.
Units
XACK/
Vol
Output Low Voltage t0L
=16 mA
0.4 v
VoH
Output High Voltage t0H =-2.6 mA
2.4 v
VIL
Input Low Voltage
0.8 v
VIH
Input High Voltage
2.0 v
Ill
Input Current at Low V
VIN =0.4V
-0.4
mA
llH
Input Current at High V
VIN =2.7V
20 µA
ADRO/-ADRF/
Vol
Output Low Voltage t0L
=32 mA
0.45 v
ADR10/-ADR13/ VoH
Output High Voltage loH
=-5 mA
2.4 v
BHENi VIL
input Low Voltage
0.8 v
VIH
Input High Voltage
2.0
v
Ill
Input Current at Low V
VIN =0.45V
-2.2
mA
llH
Input Current at High V
VIN =2.7V
100 µA
ILH
Output Leakage High v0 =5.25V
50 µA
1
LL
Output Leakage Low v0 =0.45V
-50
µA
BCLK/
VIL Input Low Voltage
0.8 v
VIH
Input High Voltage
2.0
v
1
1L
Input Current at Low V
VIN =0.45V
-0.5
mA
llH
Input Current at High V
VIN =5.5V
60
µA
CCLK VIL Input Low Voltage
.8 v
VIH
Input High Voltage
2.0
v
1
1L
Input Current at Low V
VIN =0.4V
-0.4
mA
llH
Input Current at High V
VIN =2.7V
20 µA
BPRN/
VIL
Input Low Voltage
0.8 v
VIH
Input High Voltage
2.0
v
Ill
Input Current at Low V
VIN =0.45V
-0.5
mA
llH
Input Current at High V
VIN =5.5V
60 µA
BPRO/ ,BREQ/
Vol
Output Low Voltage
loL =10 mA
0.45 v
VoH
Output High Voltage loH
=-0.4 mA
2.4
v
BUSY/ ,CBRQ/,
Vol
Output Low Voltage
loL =20 mA
0.45 v
(OPEN COLLECTOR)
DATO/-DATF/
Vol
Output Low Voltage loL
=32 mA
0.45 v
VoH
Output High Voltage loH
=-5 mA
2.4
v
VIL
Input Low Voltage
0.90 v
VIH
Input High Voltage
2.0
v
Ill
Input Current at Low V
VIN =0.45V -0.80 mA
llH
Output Leakage High v0 =5.25V
200
µA
INIT/ VIL Input Low Voltage
0.8
v
(SYSTEM RESET)
VIH
Input High Voltage
2.0 v
Ill
Input Current at Low V
VIN =0.4V
-0.9
mA
llH
Input Current at High V
VIN =2.4V
80 µA
INT5/-INT7/
Vol
Output Low Voltage
loL =16 mA
0.4 v
IORC/,IOWC/
Vol
Output Low Voltage loL
=32 mA
0.5 v
VoH
Output High Voltage t0H =-5 mA
2.4
v
ILH
Output Leakage High V0=5.25V
100
µA
IILL
Output Leakage Low
Vo =0.4V -100
µA
I
VIL
Input Low Voltage
.8
v
VIH
Input High Voltage
2.0
v
Ill
Input Current at Low V
VIN =.4V
-.4
mA
llH
Input Current at High V
VIN =2.7V
20
µA
MRDC/,MWTC/
Vol
Output Low Voltage t0L =32 mA
0.5
v
VoH
Output High Voltage loH
=-5 mA
2.4
v
ILH
Output Leakage High v0 =5.25V
100
µA
ILL
Output Leakage Low
v0 =.4V -100
µA
2-7

Preparation for Use iSBC 432/100
Table 2-6. iSBC 432/100™ AC Characteristics (Master Mode)
Minimum Maximum
Parameter (ns) (ns) Description Remarks
tAS
50
Address setup time to command
tAH
50
Address hold time from command
tos
50 Data setup to write GMO
toHW
50
Data hold time from write CMD
tcv
198 202 CPU cycle time
tcMDR
594 Read command width
tcMDW
594 Write command width
tcswR
396
Read-to-write command separation
In override mode
tcsRR
396
'Read-to-read command separation
In override mode
tcsww
594
Write-to-write command separation
In override mode
tcsRw
594
Write-to-read command separation
In override mode
tsAM
198
202 Time between XACK samples
to HR
0 Read data hold time
toxL
-400 Read data setup to XACK
txAH
0 XACK hold time
tBs
23
BPRN to BCLK setup time
to BY
55
BCLK to BUSY delay
tNOD
30
BPRN to BPRO delay
to Bo
40
BCLKI to bus priority out
tBcv
100
Bus clock period (BCLK)
tBw
.35tBcv .65tBcv Bus clock low
or high interval Supplied by system
tiNIT
3000
Initialization width After all voltages
have stabilized
Table 2-7. iSBC 432/ 100™ 1/0 Access AC Characteristics
Minimum Maximum
Parameter (ns) (ns) Description Remarks
tAs
50 Address setup to command From address to
command
tos
-100 Write data setup to command
tACK 4
tBcv
Command to XACK
tcMO
400
Command width
tAH
50 Address hold time
toHW
50
Write data hold time
toHR
25
125 Read data hold time
txAH
50 Acknowledge hold time Acknowledge turn-
off delay
tACC
300
Read to data valid
toxL
100 Read data setup to XACK
2-8

iSBC 432/100
BCLK/
BREQ/
BPRN/
BUSY/
BPRO/
ADDRESS
WRITE DATA
WRITE COMMAND
WRITEXACK/
READ COMMAND/
READ DATA
READ XACK/
1
acv---..j
I
'aw---1 H r- taw
Preparation for Use
I
tt~.J
--------------
~
tas
=7 _J
~1---------____,r( ___ _
l.--1DBY
~
l.:==1Dao
=7 \
STABLE ADDRESS
~
(
=7 J ~TABLE DATA x T
IAS· IDS .____r- ____ --1____,i:== 'AH· 'DHW
\w • ......_~~~~~tcMDw~~~~~-----4~~/r-----------
\'--__ __;. ____________ --'7
IACKWT\ u
__J k- txAH
STABLE DATA
IDXL~ r-
---1
I
L.DHR
* CBRQ/ timing not shown relative to other bus signals other than BCLK/.
Figure2-1. Bus Exchange Timing (Master Mode)
171820-2
2-9