Intel 82562EZ Guide

82562EZ(EX)/82547GI(EI) Dual
Footprint
Design Guide
Networking Silicon
317520-002
Revision 2.2

ii
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The product(s) described in this document may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708-
296-9333.
Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
Copyright © Intel Corporation, 2008
*Third-party brands and names are the property of their respective owners.

iii
82562EZ(EX)/82547GI(EI) Dual Footprint
Revision History
Revision Revision Date Description
0.25 Jul 2002 Initial publication of preliminary design guide information.
0.75 Sep 2002 Published revised design guide information:
• Added information on EEPROM settings
• Added design checklist
• Revised reference design schematic
• Revised Ball Number to signal mapping Table to conform to changes in
82547EI datasheet rev 0.75
1.0 Oct 2002 Published revised design guide information:
• Added layout checklist
• Updated LAN disable circuit
• Removed EEPROM information due to publication of separate guides
1.5 Sep 2003 Published revised design guide information:
• Added 82547GI coverage
• Removed Confidential status
• Updated schematics, removed redundant caps
• Revised LAN disable circuit
1.6 Nov 2004 Added crystal start-up information. Information includes:
• New crystal parameters
• Crystal selection guidelines
• Crystal validation methods
• Crystal testing methods
Changed signal name FL_SO to the correct signal name FLSH_SO.
Added 82562EX applicability.
Added new values for TX and RX terminations (next to LAN silicon). New
values are now 110 Ωfor both TX and RX terminations.
Added new starting values for RBIAS100 and RBIAS10. New starting values
are now 649 Ω for RBIAS100 and 619 Ω for RBIAS10.
Updated reference schematics to reflect new Tx and Rx termination values,
new LAN disable circuit, and RBIAS100/RBIAS10 values.
Removed excess capacitors and changed pins F12 and H12 to no connects.
Added a 1K Ω resistor to pin A13 output.
1.7 Jan 2005 • Changed text in the Catalyst EEPROM revision H table note from
“Revision H or higher not supported” to “Revision H is not supported”.
• Removed the Design and Layout Checklists. These checklists are now
separate Microsoft* Excel spreadsheets.
1.8 Jan 2005 Updated reference schematics to reflect current differential pair termination
resistor values for the 82547GI/EI.
Updated section 4.2.1 “Termination Resistors for Designs Based on 82562EZ/
EX PLC Device” to reflect current resistor and RBIAS values.
Updated section 4.3.1 “Termination Resistors for Designs Based on 8257GI(EI)
Gigabit Ethernet Controller” to reflect current resistor values.
1.9 June 2006 Updated reference schematics for signals EE_MODE and JTAG_TRST#
(changed resistor values from 1 K Ωto 100 Ω).
2.0 Feb 2007 Updated sections 3.1.3, 3.1.1.8, and Table 5 in section 3.1.1 (changed max
ESR rate from 20 Ω to 10 Ω for the 82547GI/EI).
2.1 June 2007 Updated reference schematics: sheets 4 and 6.
2.2 Jan 2008 Added Table 6; approved crystals for the 82547GI(EI).

iv
82562EZ(EX)/82547GI(EI) Dual Footprint
Note: This page is intentionally left blank.

v
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
Contents
1.0 Introduction.........................................................................................................................1
1.1 Scope............................................................................................................................................1
1.2 Reference Documents..................................................................................................................2
1.3 Product Codes..............................................................................................................................2
2.0 System Data Port Interfaces ..............................................................................................3
2.1 LCI Connection to 82562EZ(EX) Platform LAN Connect Device .................................................3
2.2 CSA Port Connection to 82547GI(EI) Gigabit Ethernet Controller ...............................................4
2.2.1 Generation/Distribution of Reference Voltages ...............................................................4
2.2.2 CSA Port Resistive Compensation..................................................................................5
3.0 Ethernet Component Design Guidelines............................................................................7
3.1 General Design Considerations for Ethernet Controllers..............................................................7
3.1.1 Crystal Selection Parameters..........................................................................................7
3.1.2 Reference Crystal..........................................................................................................10
3.1.3 Reference Crystal Selection..........................................................................................11
3.1.4 Circuit Board..................................................................................................................11
3.1.5 Temperature Changes...................................................................................................11
3.1.6 Integrated Magnetics Module ........................................................................................12
3.2 Designing with the 82562EZ(EX) Platform LAN Connect Device...............................................12
3.2.1 82562EZ/EX PLC Device LAN Disable Guidelines .......................................................12
3.2.2 Serial EEPROM for 82562EZ(EX) Implementations......................................................13
3.2.3 Magnetics Modules for 82562EZ(EX) PLC Device........................................................14
3.2.4 Power Supplies for 82562EZ(EX) PLC Implementations ..............................................14
3.2.5 82562EZ(EX) Device Test Capability............................................................................14
3.3 Designing with the 82547GI(EI) Gigabit Ethernet Controller......................................................14
3.3.1 82547GI(EI) Ethernet Controller LAN Disable Guidelines.............................................14
3.3.2 Serial EEPROM for 82547GI(EI) Controller Implementations .......................................15
3.3.3 EEPROM Map Information............................................................................................17
3.3.4 Magnetics Modules for 82547GI(EI) Controller Applications.........................................17
3.3.5 Power Supplies for the 82547GI(EI) Device..................................................................17
3.3.6 82547GI(EI) Controller Power Supply Filtering..............................................................18
3.3.7 82547GI(EI) Controller Power Management and Wake Up...........................................18
3.3.8 82547GI(EI) Device Test Capability ..............................................................................19
4.0 Ethernet Component Layout Guidelines ..........................................................................21
4.1 General Layout Considerations for Ethernet Controllers............................................................21
4.1.1 Guidelines for Component Placement...........................................................................21
4.1.2 Crystals..........................................................................................................................22
4.1.3 Board Stack Up Recommendations...............................................................................22
4.1.4 Differential Pair Trace Routing.......................................................................................23
4.1.5 Signal Trace Geometry..................................................................................................24
4.1.6 Trace Length and Symmetry .........................................................................................24
4.1.7 Impedance Discontinuities.............................................................................................25
4.1.8 Reducing Circuit Inductance..........................................................................................25
4.1.9 Signal Isolation ..............................................................................................................25
4.1.10 Power and Ground Planes.............................................................................................25

vi
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
4.1.11 Traces for Decoupling Capacitors .................................................................................26
4.1.12 Ground Planes Under the Magnetics Module................................................................26
4.1.13 Special Considerations for Non-Integrated
Magnetics Modules and RJ-45 Connectors...................................................................28
4.2 Layout for the 82562EZ(EX) Platform LAN Connect Device......................................................29
4.2.1 Termination Resistors for Designs Based on 82562EZ(EX) PLC Device......................29
4.2.2 Light Emitting Diodes for Designs Based on 82562EZ(EX) PLC Device.......................29
4.3 Layout for the 82547GI(EI) Gigabit Ethernet Controller .............................................................30
4.3.1 Termination Resistors for Designs Based on 82547GI(EI) Gigabit Ethernet Controller 30
4.3.2 Light Emitting Diodes for Designs Based on 82547GI(EI) Controller............................30
4.4 Physical Layer Conformance Testing.........................................................................................30
4.5 Troubleshooting Common Physical Layout Issues.....................................................................31
5.0 Design and Layout Checklists..........................................................................................33
6.0 Ball Number to Signal Mapping with Population Options.................................................35
7.0 Dual Footprint Reference Schematic...............................................................................43
A Measuring LAN Reference Frequency Using a Frequency Counter................................51
B GigConf.exe Register Settings for 82547GI(EI) Devices.................................................57
Figures
1 ICH5 Platform LAN Connect Sections..........................................................................................3
2 CSA Port Locally Generated Reference Divider Circuits..............................................................4
3 CSA port CI_RCOMP Circuits......................................................................................................5
4 Crystal Circuit...............................................................................................................................9
5 LAN Disable Circuitry .................................................................................................................13
6 82547GI(EI) LAN Disable Circuitry.............................................................................................15
5 General Placement Distances....................................................................................................22
6 Trace Routing.............................................................................................................................23
7 Ground Plane Separation...........................................................................................................26
8 Ideal Ground Split Implementation .............................................................................................27
9 Termination Plane Example for 82562EZ(EX) PLC Device and Discrete Magnetics.................28
10 82562EZ(EX) PLC Device Differential Signal Termination.........................................................29
11 Indirect Probing Setup................................................................................................................52
12 Direct Probing Method................................................................................................................55

vii
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
Tables
1 LAN Component Connections/Features.......................................................................................1
2 Product Ordering Codes...............................................................................................................2
3 CSA Port Reference Circuit Specifications...................................................................................4
4 CSA Port CI_RCOMP Resistor Values.........................................................................................5
5 Crystal Parameters.......................................................................................................................7
6 82547GI(EI) Recommended Crystals...........................................................................................8
7 82562EZ(EX) Memory Layout (128 Byte EEPROM)..................................................................13
8 82562EZ(EX) Memory Layout (512 Byte EEPROM)..................................................................14
9 82562EZ(EX) Recommended Magnetics Modules.....................................................................14
10 Microwire 64 x 16 Serial EEPROMs...........................................................................................16
11 SPI Serial EEPROMs for 82547GI(EI) Controller.......................................................................16
12 82547GI(EI) EEPROM Memory Layout......................................................................................17
13 82547GI(EI) Recommended Magnetics Modules.......................................................................17
14 Ball Number to Signal Mapping..................................................................................................35

viii
82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
Note: This page intentionally left blank.

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
1
1.0 Introduction
Intel currently supports several footprint compatible Ethernet options depending upon the target
application. The term “footprint compatible” means that the silicon devices are all manufactured in
a 15 mm x 15 mm, 196-ball grid array package with the same ball pattern. Many of the critical
signal pin locations are identical, allowing designers to create a single LAN on Motherboard
(LOM) design that accommodates all devices. This is a flexible, cost-effective, multipurpose
design technique that allowing maximized value while matching performance needs.
Note: Since some of the signal pins have different usages, the term “pin-compatible” is not applicable.
Available LAN components with the same footprint include the 82547GI(EI) Gigabit Ethernet
Controller and the 82562EZ(EX) Platform LAN Connect components.
The LAN component used on a specific platform depends on the end user’s need for connection
speed and manageability. As the requirements change, footprint compatibility makes it possible to
re-focus the platform without the need to redesign a new a motherboard.
1.1 Scope
This application note contains Ethernet design guidelines applicable to LOM designs based on the
Intel®865 Chipset and Intel®875 Chipset. The document identifies similarities and differences
between the 82562EZ(EX) Platform LAN Connect device and the 82547GI(EI) Gigabit Ethernet
Controller.
Section 2 describes the port interfaces specific to each device.
Section 3 explains what you need to know to hook up an Ethernet device to the system.
Section 4 describes board layout techniques applicable to these devices.
Section 5 provides a reference to the design and layout checklists.
Table 1. LAN Component Connections/Features
LAN Component Interface Connection Features
Intel®82547GI(EI) CSA GigabitEthernet(1000BASE-T)
with Alert Standard Format
(ASF) alerting
Gigabit Ethernet, ASF 2.0
alerting
Intel®82562EX (196 BGA) LCI 10/100 Ethernet with ASF
alerting Ethernet 10/100 connection, ASF 1.0
alerting
Intel®82562EZ (196 BGA) LCI Basic 10/100 Ethernet Ethernet 10/100
connection

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
2
Section 6 compares pin names and numbers between the two components.
Section 7 concludes with a reference design schematic of the full dual footprint configuration.
Note: It is assumed that the reader is acquainted with high-speed design and board layout techniques.
Additional documents may be referred to for further information.
1.2 Reference Documents
•82547GI(EI) Gigabit Ethernet Controller Datasheet. Intel Corporation.
•82562EZ 10/100 Mbps Platform LAN Connect (PLC) Networking Silicon Datasheet. Intel
Corporation.
•82562ET/EM Platform LAN Connect Printed Circuit Board Design Guide. Intel Corporation.
•82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map and Programming Information. Intel
Corporation.
•ICH2 Integrated LAN Controller Function Disable and Power Control. Intel Corporation.
•PCI Bus Power Management Interface Specification, Rev. 1.1, PCI Special Interest Group.
•IEEE Standard 802.3, 2000 Edition. Incorporates various IEEE standards previously published
separately.
•I/O Control Hub 2, 3, and 4 EEPROM Map and Programming Information. Intel Corporation.
•I/O Control Hub 5, 6, and 7 EEPROM Map and Programming Information. Intel Corporation.
Programming information can be obtained through your local Intel representative.
1.3 Product Codes
Table 2 lists the product ordering codes for the 82562EZ(EX)and 82547GI(EI).
Table 2. Product Ordering Codes
Device Product Code Product Code (Lead Free)
82562EZ GD82562EZ LU82562EZ
82562EX GD82562EX LU82562EX
82547GI GD82547GI LU82547GI
82547EI GD82547EI LU82547EI

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
3
2.0 System Data Port Interfaces
The 82562EZ(EX) Platform LAN Connect Device and the 82547GI(EI) Gigabit Ethernet
controller employ different system interfaces, as illustrated in Figure 1.
Figure 1. ICH5 Platform LAN Connect Sections
2.1 LCI Connection to 82562EZ(EX) Platform LAN Connect
Device
The 82562EZ(EX) Platform LAN Connect device uses the LAN Connect Interface (LCI) to
connect to the I/O Control Hub 5 (ICH5). LCI is a point-to-point interface optimized to support one
device.
Line termination mechanisms are not specified for the LCI. Slew rate controlled output buffers
achieve acceptable signal integrity by controlling signal reflection, undershoot and ringing.
For details about how to connect the LCI interface between the 82562EZ(EX) Platform LAN
Connect device and ICH5, please refer to the 82562ET/EM Platform LAN Connect Printed Circuit
Board (PCB) Design Guide, the Intel®865 Chipset design guide, or the Intel®875 Chipset design
guide.
GMCH
Magnetics
Module Connector
Intel®
82562EZ(EX)
Intel®
ICH5
LCI
Intel®
82547GI(EI)
CSA

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
4
2.2 CSA Port Connection to 82547GI(EI) Gigabit Ethernet
Controller
The 82547GI(EI) Gigabit Ethernet Controller uses the Communications Streaming Architecture
(CSA) port to connect to the Memory Control Hub (MCH). CSA is a point-to-point interface
supporting one device.
CSA has a theoretical bandwidth of 266 MB/s, sufficient to support Gigabit Ethernet speeds. The
connection to the MCH places the Ethernet controller close to system memory for minimum
latency.
The CSA interface uses IGTL buffers to achieve very high data speeds while controlling
transmission line characteristics. For details on connecting the CSA interface between the
82547GI(EI) Gigabit Ethernet Controller and the MCH, please refer to the Intel®865 Chipset
design guide, or the Intel®875 Chipset design guide.
2.2.1 Generation/Distribution of Reference Voltages
The 11-bit CSA port on the 82547GI(EI) controller has a dedicated CI_VREF pin to sample the
reference voltage. The nominal CSA port reference voltage is 0.35 V ± 3%. In addition to the
reference voltage, a reference swing voltage, CI_SWING must be supplied to control buffer
voltage swing characteristics. The nominal CSA port reference voltage swing must be 0.8 V ± 3%.
Figure 2. CSA Port Locally Generated Reference Divider Circuits
Table 3. CSA Port Reference Circuit Specifications
Reference Voltage
Specification (V) Reference Swing Voltage Specification (V) 1.2 V Voltage Divider Circuit Recommended Resistor Values (Ω)
0.350 ± 3% 0.8 ± 3% R1 = 523 ± 1%
R2 = 665 ± 1%
R3 = 604 ± 1%
Intel®
82547GI(EI)
0.35 V
0.8 V
CI_SWING
CI_VREF
R1
R2
R3
C2C1
C1 C2
1.2V

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
5
The values of R1, R2 and R3 must be rated at ±1% tolerance. The selected resistor values must also
ensure that the reference voltage and reference swing voltage tolerance are maintained over the
input leakage specification. A 0.1 µF capacitor (C1 in Figure 2) should be placed within 0.5 inches
to each resistor divider, and a 0.01 µF bypass capacitor (C2 in Figure 2) should be placed within
0.25 inches of reference voltage pins. If the length of the trace from the voltage divider to the pin is
greater than 1 inch, place more than one 0.01 µF capacitor near the reference voltage pin. The trace
length from the voltage divider circuit to the CI_REF pins must be no longer than 3.5 inches.
Both the voltage reference and voltage swing reference signals should be routed at least 10mils
wide and spaced at least 20 mils from all other signals.
2.2.2 CSA Port Resistive Compensation
The CSA port uses a resistive compensation signal (CI_RCOMP) to compensate buffer
characteristics for temperature, voltage, and process.
Figure 3. CSA port CI_RCOMP Circuits
Table 4. CSA Port CI_RCOMP Resistor Values
Component Trace Impedance RCOMP Resistor Value RCOMP Resistor Tied To
Intel® 82547GI(EI) 60 Ω± 15% R1 = 30.1 Ω± 1% VCC1.2
R1
1.2V
Intel®
82547GI(EI)
CI_RCOMP

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
6
Note: This page intentionally left blank.

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
7
3.0 Ethernet Component Design Guidelines
These sections provide recommendations for selecting components and connecting special pins.
The main design elements are the 82562EZ(EX) Platform LAN Connect device or the
82547GI(EI) Gigabit Ethernet Controller, an integrated magnetics module with RJ-45 connector,
and a crystal clock source.
3.1 General Design Considerations for Ethernet Controllers
These recommendations apply to all designs, 10/100 or 10/100/1000 Mb/s.
Follow good engineering practices with respect to unused inputs by terminating them with pull-up
or pull-down resistors, unless the data sheet, design guide or reference schematic indicates
otherwise. Do not attach pull-up or pull-down resistors to any balls identified as No Connect.
These devices may have special test modes that could be entered inadvertently.
3.1.1 Crystal Selection Parameters
Quartz crystals are generally considered to be the mainstay of frequency control components due to
their low cost and ease of implementation. They are available from numerous vendors in many
package types and with various specification options.
All crystals used with Intel®Ethernet controllers are described as “AT-cut”, which refers to the
angle at which the unit is sliced with respect to the long axis of the quartz stone.
Table 5 lists the crystal electrical parameters and provides suggested values for typical designs. The
parameters listed are described in the following subsections.
Table 5. Crystal Parameters
Parameter Suggested Value
Vibration Mode Fundamental
Nominal Frequency 25,000 MHz at 25°C (required)
Frequency Tolerance • ±30 ppm recommended; ±50 ppm across the entire operating
temperature range as required by IEEE specifications
• ±30 ppm required for the 82547GI(EI)
Temperature Stability • ±50 ppm at 0°C to 70°C
• ±30 ppm at 0°C to 70°C required for the 82547GI(EI)
Calibration Mode Parallel
Load Capacitance • 16 pF to 20 pF
• 18 pF required for the 82547GI(EI)
Shunt Capacitance 6 pF maximum
Equivalent Series Resistance • 50 Ω maximum
• 10 Ω maximum required for the 82547GI(EI)
Drive Level 0.5 mW maximum
Aging ±5 ppm per year maximum

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
8
.Table 6 lists the approved crystals for use with the 83547GI(EI) B1 steppings.
3.1.1.1 Vibration Mode
Crystals in the frequency range listed in Table 5 are available in both fundamental and third
overtone. Unless there is a special need for third overtone, use fundamental mode crystals.
At any given operating frequency, third overtone crystals are thicker and more rugged than
fundamental mode crystals. Third overtone crystals are more suitable for use in military or harsh
industrial environments. Third overtone crystals require a trap circuit (extra capacitor and inductor)
in the load circuitry to suppress fundamental mode oscillation as the circuit powers up. Selecting
values for these components is beyond the scope of this document.
3.1.1.2 Nominal Frequency
Intel® Ethernet controllers use a crystal frequency of 25.000 MHz. The 25 MHz input is used to
generate a 125 MHz transmit clock for 100BASE-TX and 1000BASE-TX operation; 10 MHz and
20 MHz transmit clocks, for 10BASE-T operation.
3.1.1.3 Frequency Tolerance
The frequency tolerance for an Ethernet physical layer device is dictated by the IEEE 802.3
specification as ±50 parts per million (ppm). This measurement is referenced to a standard
temperature of 25° C.
Note: Intel recommends a frequency tolerance of ±30 ppm.
3.1.1.4 Temperature Stability and Environmental Requirements
Temperature stability is a standard measure of how the oscillation frequency varies over the full
operational temperature range (and beyond). Several optional temperature ranges are currently
available, including -40° C to +85° C for industrial environments. Some vendors separate operating
temperatures from temperature stability. Manufacturers may also list temperature stability as 50
ppm in their data sheets.
Note: Crystals also carry other specifications for storage temperature, shock resistance, and reflow solder
conditions. Crystal vendors should be consulted early in the design cycle to discuss the application
and its environmental requirements.
3.1.1.5 Calibration Mode
The terms “series-resonant” and “parallel-resonant” are often used to describe crystal circuits.
Specifying parallel mode is critical to determining how the crystal frequency is calibrated at the
factory.
Table 6. 82547GI(EI) Recommended Crystals
Manufacturer Manufacturer's Part Number
Raltron (<20 ΩESR and +/-30 ppm) AS-25.000-20-F-SMD-TR
TXC 6C25000355

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
9
A crystal specified and tested as series resonant oscillates without problem in a parallel-resonant
circuit, but the frequency is higher than nominal by several hundred parts per million. The purpose
of adding load capacitors to a crystal circuit is to establish resonance at a frequency higher than the
crystal’s inherent series resonant frequency.
Figure 4 illustrates a simplified schematic of the 82562EZ(EX) and the 82547GI(EI) controller’s
crystal circuit. The crystal and the capacitors form a feedback element for the internal inverting
amplifier. This combination is called parallel-resonant, because it has positive reactance at the
selected frequency. In other words, the crystal behaves like an inductor in a parallel LC circuit.
Figure 4. Crystal Circuit
3.1.1.6 Load Capacitance
The formula for crystal load capacitance is as follows:
where C1 = C2 = 22 pF (as suggested in most Intel reference designs)
and Cstray = allowance for additional capacitance in pads, traces and the chip carrier
within the Ethernet controller package
An allowance of 3 pF to 7 pF accounts for lumped stray capacitance. The calculated load
capacitance is 16 pF with an estimated stray capacitance of about 5 pF.
Individual stray capacitance components can be estimated and added. For example, surface mount
pads for the load capacitors add approximately 2.5 pF in parallel to each capacitor. This technique
is especially useful if Y1, C1 and C2 must be placed farther than approximately one-half (0.5) inch
from the controller. It is worth noting that thin circuit boards generally have higher stray
capacitance than thick circuit boards.
C1 C2
LAN
Silicon
X1 or Xin
LAN
Silicon
X2 or Xout
CLC1C2⋅()
C1C2+()
------------------------- Cstray +=

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
10
Standard capacitor loads used by crystal manufacturers include 16 pF, 18 pF and 20 pF. Any of
these values will generally operate with the controller. However, a difference of several picofarads
between the calibrated load and the actual load will pull the oscillator slightly off frequency.
Note: C1 and C2 may vary by as much as 5% (approximately 1 pF) from their nominal values.
3.1.1.7 Shunt Capacitance
The shunt capacitance parameter is relatively unimportant compared to load capacitance. Shunt
capacitance represents the effect of the crystal’s mechanical holder and contacts. The shunt
capacitance should equal a maximum of 6 pF (7 pF is also acceptable).
3.1.1.8 Equivalent Series Resistance
Equivalent Series Resistance (ESR) is the real component of the crystal’s impedance at the
calibration frequency, which the inverting amplifier’s loop gain must overcome. ESR varies
inversely with frequency for a given crystal family. The lower the ESR, the faster the crystal starts
up. Use crystals with an ESR value of 50 Ωor better.
Note: Check the specific controller documentation carefully; some devices may have tighter ESR
requirements. For example, Intel recommends that 82547GI(EI) devices use crystals with an ESR
value of 10 Ωor less.
3.1.1.9 Drive Level
Drive level refers to power dissipation in use. The allowable drive level for a Surface Mounted
Technology (SMT) crystal is less than its through-hole counterpart, because surface mount crystals
are typically made from narrow, rectangular AT strips, rather than circular AT quartz blanks.
Some crystal data sheets list crystals with a maximum drive level of 1 mW. However, Intel®
Ethernet controllers drive crystals to a level less than the suggested 0.5 mW value. This parameter
does not have much value for on-chip oscillator use.
3.1.1.10 Aging
Aging is a permanent change in frequency (and resistance) occurring over time. This parameter is
most important in its first year because new crystals age faster than old crystals. Use crystals with a
maximum of ±5 ppm per year aging.
3.1.2 Reference Crystal
The normal tolerances of the discrete crystal components can contribute to small frequency offsets
with respect to the target center frequency. To minimize the risk of tolerance-caused frequency
offsets causing a small percentage of production line units to be outside of the acceptable frequency
range, it is important to account for those shifts while empirically determining the proper values for
the discrete loading capacitors, C1 and C2.
Even with a perfect support circuit, most crystals will oscillate slightly higher or slightly lower than
the exact center of the target frequency. Therefore, frequency measurements (which determine the
correct value for C1 and C2) should be performed with an ideal reference crystal. When the
capacitive load is exactly equal to the crystal’s load rating, an ideal reference crystal will be
perfectly centered at the desired target frequency.

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
11
3.1.3 Reference Crystal Selection
There are several methods available for choosing the appropriate reference crystal:
•If a Saunders and Associates (S&A) crystal network analyzer is available, then discrete crystal
components can be tested until one is found with zero or nearly zero ppm deviation (with the
appropriate capacitive load). A crystal with zero or near zero ppm deviation will be a good
reference crystal to use in subsequent frequency tests to determine the best values for C1 and
C2.
•If a crystal analyzer is not available, then the selection of a reference crystal can be done by
measuring a statistically valid sample population of crystals, which has units from multiple
lots and approved vendors. The crystal, which has an oscillation frequency closest to the center
of the distribution, should be the reference crystal used during testing to determine the best
values for C1 and C2.
•It may also be possible to ask the approved crystal vendors or manufacturers to provide a
reference crystal with zero or nearly zero deviation from the specified frequency when it has
the specified CLoad capacitance.
Note: For 82547GI(EI) devices, Intel® recommends choosing a crystal with a ESR value of 10 Ω or less,
an equivalent Cload of 18 pF, and a maximum of 30 ppm frequency shift. Cload is defined to be the
load capacitance of the crystal, specified by the crystal vendor.
When choosing a crystal, customers must keep in mind that to comply with IEEE specifications for
10/100 and 10/100/1000Base-T Ethernet LAN, the transmitter reference frequency must be precise
within ±50 ppm. Intel® recommends customers to use a transmitter reference frequency that is
accurate to within ±30 ppm to account for variations in crystal accuracy due to crystal
manufacturing tolerance. For information about measuring transmitter reference frequency, refer to
Appendix A, “Measuring LAN Reference Frequency Using a Frequency Counter”.
3.1.4 Circuit Board
Since the dielectric layers of the circuit board are allowed some reasonable variation in thickness,
the stray capacitance from the printed board (to the crystal circuit) will also vary. If the thickness
tolerance for the outer layers of dielectric are controlled within ±17 percent of nominal, then the
circuit board should not cause more than ±2 pF variation to the stray capacitance at the crystal.
When tuning crystal frequency, it is recommended that at least three circuit boards are tested for
frequency. These boards should be from different production lots of bare circuit boards.
Alternatively, a larger sample population of circuit boards can be used. A larger population will
increase the probability of obtaining the full range of possible variations in dielectric thickness and
the full range of variation in stray capacitance.
Next, the exact same crystal and discrete load capacitors (C1 and C2) must be soldered onto each
board, and the LAN reference frequency should be measured on each circuit board.
The circuit board, which has a LAN reference frequency closest to the center of the frequency
distribution, should be used while performing the frequency measurements to select the appropriate
value for C1 and C2.
3.1.5 Temperature Changes
Temperature changes can cause the crystal frequency to shift. Therefore, frequency measurements
should be done in the final system chassis across the system’s rated operating temperature range.

82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide
12
3.1.6 Integrated Magnetics Module
The magnetics module has a critical effect on overall IEEE and regulatory conformance. The
device should meet the performance required for a design with reasonable margin to allow for
manufacturing variation. Occasionally, components that meet basic specifications may cause the
system to fail IEEE testing because of interactions with other components or the printed circuit
board itself. Carefully qualifying new magnetics modules can go a long way toward preventing this
type of problem.
The steps involved in magnetics module qualification are similar to those for oscillator
qualification:
1. Verify that the vendor's published specifications in the component datasheet meet the required
IEEE specifications.
2. Independently measure the component's electrical parameters on the test bench, checking
samples from multiple lots. Check that the measured behavior is consistent from sample to
sample as well as meeting the published specifications.
3. Perform physical layer conformance testing and EMC (FCC and EN) testing in real systems.
Vary temperature and voltage while performing system level tests (for IEEE only).
Magnetics modules for 1000BASE-T Ethernet are similar to those designed solely for
10/100 Mbps, with the exception of four differential signal pairs instead of two for 10/100 Mbps.
3.2 Designing with the 82562EZ(EX) Platform LAN Connect
Device
This section provides design guidelines specific to the PLC device.
3.2.1 82562EZ/EX PLC Device LAN Disable Guidelines
Note: ICHx Integrated LAN Controller resides on the ICHx VccSus3_3 and VccSus1_8 power wells
(typically referred to as “auxiliary” (“aux”) or “standby” supplies at the platform level).
The ICHx Integrated LAN’s RST# is the ICHx Resume-well input. It can be held low indefinitely
to keep the ICHx Integrated LAN Controller in a reset state. The LAN Reset (RST#) signal must
not be deasserted sooner than 10 ms after the Resume power supply reaches its nominal voltage.
This ensures that the ICHx Integrated LAN Controller is initialized. Figure 5 illustrates a possible
solution for ICHx Integrated LAN disable.