Intel 82571EB EEPROM Technical manual

82571EB/82572EI EEPROM
Information Guide
316937-004
Revision 2.3

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82571EB/82572EI EEPROM Information Guide
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future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
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Current characterized errata are available on request.
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Copyright © 2009, Intel Corporation. All rights reserved.

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82571EB/82572EI EEPROM Information Guide
Revision History
Revision Revision Date Description
2.3 August 2009 Updated Table 34 “iSCSI Module Structure”.
2.2 May 2008 Updated Table 6, Software Defined Pins Control (Word 10h/20h), changed the
value of bit 4 from 1b to 0b.
2.1 Aug 2007 Updated bit descriptions for words 03h, 10h/20h, 21h, and 37h.
2.0 April 2007 Updated default values and bit descriptions for words 03h, 0Ah, 17h, 1Bh, 1Eh,
and 21h
Updated Table 1.
1.9 Feb 2007 Updated section 1.0.
Updated Table 1, words 03h and 04h.
Updated Word 0Ah, bits 13 and 12.
Updated Word 10h/20h, bits 4 and 3.
1.8 Dec 2006 Updated Word 03h,18h, 19h, 0Ah, 1Ah, and 1Eh bit assignments.
1.7 June 2006 Initial public release.
1.6 Mar 2006 Added new description for Word 13h. Updated bit assignments for Words 0Ah,
0Fh, 1Ah, 1Bh, 1Eh, 18h, 19h, and 21h.
1.5 Mar 2006 Final release (Intel Confidential)
1.0 Nov 2005 Initial release (Intel Confidential).
0.25 July 2004 Initial release (Intel Secret).

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Contents
1.0 Introduction.........................................................................................................................1
1.1 Reference Documents .................................................................................................1
1.2 EEPROM Device..........................................................................................................2
1.3 Software Accesses.......................................................................................................2
1.4 Signature Fields and CRC Fields.................................................................................3
1.5 Protected EEPROM Space..........................................................................................3
1.5.1 Initial EEPROM Programming...............................................................................3
1.5.2 Activating the Protection Mechanism.....................................................................4
1.5.3 Non Permitted Accessing to Protected areas in the EEPROM..............................4
1.6 EEPROM Map..............................................................................................................4
1.7 Hardware Accessed Words..........................................................................................7
1.7.1 Ethernet Address (Words 02h:00h).......................................................................7
1.7.2 Initialization Control Word 1 (Word 0Ah) ...............................................................7
1.7.3 Subsystem ID (Word 0Bh).....................................................................................8
1.7.4 Subsystem Vendor ID (Word 0Ch)........................................................................8
1.7.5 Device ID (Word 0Dh, 11h)....................................................................................9
1.7.6 Vendor ID (Word 0Eh)...........................................................................................9
1.7.7 Initialization Control Word 2 (Word 0Fh)................................................................9
1.7.8 Software Defined Pins Control (Word 10h/20h)...................................................10
1.7.9 EEPROM Sizing and Protected Fields (Word 12h) .............................................12
1.7.10 Management Capabilities (Word 13h, Lower Byte).............................................12
1.7.11 Management Enable Byte (Word 13h, Upper Byte) ............................................12
1.7.12 Initialization Control 3 (Word 14h/24h, Lower Byte) ............................................13
1.7.13 Initialization Control 3 (Word 14h/24h Upper Byte) .............................................14
1.7.14 Firmware Start Address; Including PHY Initialization Area (Word 17h)...............15
1.7.15 PCIe* Init Configuration Word 1 (Word 18h)........................................................15
1.7.16 PCIe* Init Configuration Word 2 (Word 19h)........................................................16
1.7.17 PCIe* Init Configuration Word 3 (Word 1Ah).......................................................16
1.7.18 PCIe* Control (Word 1Bh) ...................................................................................17
1.7.19 LED 1-3 Configuration Defaults (Word 1Ch) .......................................................17
1.7.20 Device Rev ID (Word 1Eh) ..................................................................................19
1.7.21 LED 0-2 Configuration Defaults (Word 1Fh)........................................................19
1.7.22 Functions Control (Word 21h)..............................................................................20
1.7.23 LAN Power Consumption (Word 22h) .................................................................21
1.7.24 Management Hardware Configuration Control (Word 23h).................................22
1.7.25 PXE Code (Words 30h:35h)................................................................................22
1.7.26 Alternate MAC Address (Word 37h)....................................................................22
1.7.27 Manageability D0 Power Consumption (Word 100h/40h)....................................22
1.7.28 Manageability D3 Power Consumption (Word 101h/41hh)..................................23
1.7.29 IDE Device ID (Word 102h/42h)..........................................................................23
1.7.30 Serial Port Device ID (Word 103h/43h) ...............................................................23
1.7.31 IPMI/KCS Device ID (Word 104h/44h) ................................................................23
1.7.32 IDE Subsystem ID (Word 105h/45h) ...................................................................24
1.7.33 Serial Port Subsystem ID (Word 106h/46h).........................................................24
1.7.34 IPMI/KCS Subsystem ID (Word 107h/47h)..........................................................24
1.7.35 IDE Boot Control (Word 108h/48h)......................................................................24

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1.7.36 KCS Device Class Code Low (Word 10Eh/4Eh) .................................................25
1.7.37 KCS Device Class Code High (Word 10Fh/4Fh).................................................25
1.8 Vital Product Data Pointer (Word 2Fh).......................................................................25
1.9 iSCSI Boot Configuration Start Address (Word 3Dh).................................................26
1.10 Checksum Word Calculation (Word 3Fh)...................................................................27
1.11 ASF Controller Words................................................................................................28
1.11.1 ASF Words - Content ..........................................................................................28
1.11.2 ASF Words - EEPROM Checksum (CRC) ..........................................................28
1.12 Software Owned EEPROM Words Description..........................................................29
1.12.1 EEPROM Map for Words 03h:09h ......................................................................29
1.12.2 Software Compatibility Word 1 (Word 03h) .........................................................29
1.12.3 OEM LED Configuration Word (Word 04h) .........................................................30
1.12.4 EEPROM Version Word (Word 05h) ...................................................................30
1.12.5 OEM Configuration (Words 06h:07h) ..................................................................30
1.12.6 PBA Number (Words 08h, 09h)...........................................................................30

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1.0 Introduction
A series of 82571EB/82572EI EEPROMs are developed and validated as part of the 82571EB/
82572EI validation effort. These dev_starter images represent a cross section of configurations that
are available. Intel strongly recommends that designers use the dev_starter image that corresponds
most closely with the desired configuration options. Dev_starter images have been fully validated
with the reference design and can be used to ensure that the base functionality of a specific design
is working as expected.
Dev_starter images are developed using generic modules (modules that expose a particular feature
in a given EEPROM). Because some features are mutually exclusive, these modules are developed
to preclude any generation of an EEPROM that has conflicting features. If a dev_starter image does
not contain all the appropriate features that a specific design requires, please contact your Intel
representative instead of modifying individual word or bit assignments to avoid conflicts.
The 82571EB/82572EI uses an EEPROM device to store product configuration information. The
EEPROM is divided into three general regions:
•Hardware Accessed — Loaded by the Ethernet controller after power-up, PCIe* reset de-
assertion, in-band PCIe* reset, a D3 to D0 transition, a software commanded EEPROM read
(CTRL_EXT.EE_RST), and a software reset (CTRL.RST, word 00000h, bit 26).
•Software Accessed — Used by software only. These registers are listed in this document for
convenience and are only for software and are ignored by the Ethernet controller.
•Firmware Accessed — Used by BMC, PT, SPT, or ASF firmware (For more information
about manageability, contact your Intel field representative).
— Firmware Reset (all modes) - occurs after any of the following:
LAN power up (LAN_PWR_GOOD assertion)
Software-initiated firmware reset through a host command
Software-initiated firmware reset through MAC CSRs (writing 40h and then 80h to
HICR)
Certain unrecoverable errors during manageability operation (RAM parity error, hardware
watchdog timer expiration, etc.)
— Software-Initiated EEPROM Reload (ASF mode only) - occurs after any of the following:
Software-initiated assertion of the SWSM.WMNG bit while manageability clock is off
Software-initiated EEPROM reload through ASF register (asserting FR_RST.FRC_EELD
or FRC_FLUSH)
Software-initiated ERPROM reload through a host command
System state transition S0 to S5 while ASF register bit CTL_PWRLS is cleared
1.1 Reference Documents
•82571/82572/631xESB/632xESB System Manageability Application Note, Intel Corporation.
•PCIe* Family of Gigabit Ethernet Controllers Software Developer’s Manual, Intel
Corporation.
Note: Contact your Intel field representative for access to these documents.

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1.2 EEPROM Device
The EEPROM interface supports Serial Peripheral Interface (SPI) mode 0 and expects the
EEPROM to be capable of 2 MHz operation.
The 82571EB/82572EI is compatible with many sizes of 4-wire serial EEPROM devices. If
flexibility mode functionality is desired (ASF, PT, SPT, or full BMC), up to a 256 Kb serial SPI can
be used.
Note: Minimum EEPROM sizes: 16 Kb (no manageability image); 128 Kb (any manageability image).
Recommended EEPROM sizes are: 32 Kb (no manageability image); 256 Kb (any manageability
image.
The 82571EB/82572EI automatically determines the address size to be used with the SPI
EEPROM it is connected to and sets the EEPROM Size field of the EEPROM/Flash Control and
Data Register (EEC.EE_ADDR_SIZE; bit 10). Software uses this size to determine the EEPROM
access method. The exact size of the EEPROM is stored within one of the EEPROM words.
Note: The different EEPROM sizes have two different numbers of address bits (8 bits or 16 bits). Thus
they must be accessed with a slightly different serial protocol. Software must be aware of this if it
accesses the EEPROM using direct access.
1.3 Software Accesses
The 82571EB/82572EI provides two different methods for software access to the EEPROM. It can
either use the built-in controller to read the EEPROM or access the EEPROM directly using the
EEPROM’s 4-wire interface.
Software can use the EEPROM Read register (EERD) to cause the 82571EB/82572EI to read a
word from the EEPROM that the software can then use. To do this, software writes the address to
read into the Read Address field (EERD.ADDR; bits 15:2) and simultaneously writes a 1b to the
Start Read bit (EERD.START; bit 0). The 82571EB/82572EI then reads the word from the
EEPROM, sets the Read Done bit (EERD.DONE; bit 1), and puts the data in the Read Data field
(EERD.DATA; bits 31:16). Software can poll the EEPROM Read register until it sees the Read
Done bit set, then use the data from the Read Data field. Any words read this way are not written to
the 82571EB/82572EI’s internal registers.
Software can also directly access the EEPROM’s 4-wire interface through the EEPROM/Flash
Control register (EEC). It can use this for reads, writes, or other EEPROM operations.
To directly access the EEPROM, software should follow these steps:
1. Write a 1b to the EEPROM Request bit (EEC.EE_REQ; bit 6).
2. Read the EEPROM Grant bit (EEC.EE_GNT; bit 7) until it becomes 1b. It remains 0b as long
as the hardware is accessing the EEPROM.
3. Write or read the EEPROM using the direct access to the 4-wire interface as defined in the
EEPROM/Flash Control & Data register (EEC). The exact protocol used depends on the
EEPROM placed on the board and can be found in the appropriate datasheet.
4. Write a 0b to the EEPROM Request bit (EEC.EE_REQ; bit 6).

82571EB/82572EI EEPROM Information Guide
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Finally, software can cause the 82571EB/82572EI to re-read part of the hardware accessed fields of
the EEPROM (setting the 82571EB/82572EI’s internal registers appropriately) by writing a 1b to
the EEPROM Reset bit of the Extended Device Control register (CTRL_EXT.EE_RST; bit 13).
1.4 Signature Fields and CRC Fields
The only way the 82571EB/82572EI can discover whether an EEPROM is present is by trying to
read the EEPROM. The 82571EB/82572EI first reads the EEPROM Sizing & Protected field Word
at address 12h. The 82571EB/82572EI checks the signature value for bits 15 and 14. If bit 15 is 0b
and bit 14 is 1b, it considers the EEPROM to be present and valid and reads additional EEPROM
words and programs its internal registers based on the values read. Otherwise, it ignores the values
it read from that location and does not read any other words.
In ASF Mode, the 82571EB/82572EI’s ASF function reads the ASF CRC word to determine if the
EEPROM is valid. If the CRC is not valid, the ASF Configuration registers retain their default
values. This CRC does not affect the remaining 82571EB/82572EI configuration, including the
Management Control register. For details on how the CRC is calculated see Section 1.10.
Note: When the signature is not correct (the EEPROM is blank), it cannot be accessed by parallel access
if its size is 512 bytes or smaller. As a result, the EEPROM should be accessed using the bit-bang
mechanism.
1.5 Protected EEPROM Space
The 82571EB/82572EI provides a mechanism for a hidden area in the EEPROM to the host. The
hidden area cannot be accessed via the EEPROM registers in the CSR space. It can be accessed
only by the Manageability (MNG) subsystem. For more information about the management
subsystem, contact your Intel field representative.
1.5.1 Initial EEPROM Programming
In most applications, initial EEPROM programming is done directly on the EEPROM pins.
Nevertheless, it is desirable to enable existing software utilities (accessing the EEPROM via the
host interface) to initially program the whole EEPROM without breaking the protection
mechanism. Following a power-up sequence, the 82571EB/82572EI reads the hardware
initialization words in the EEPROM. If the signature in word 12h does not equal 01b the EEPROM
is assumed as non-programmed. There are two effects for non-valid signature:
•The 82571EB/82572EI stops reading EEPROM data and sets the relevant registers to default
values
•The 82571EB/82572EI enables access to any location in the EEPROM via the EEPROM CSR
registers including the protected EEPROM space.

82571EB/82572EI EEPROM Information Guide
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1.5.2 Activating the Protection Mechanism
Following an 82571EB/82572EI initialization, it reads the EEPROM. It then turns on the
protection mechanism if word 12h [15:14] contains a valid signature (equals 01b) and a hidden
area with a non-zero size is defined (if required). Once the protection mechanism is turned on,
word 12h becomes write-protected and the area that is defined by word 12h becomes hidden (i.e.,
R/W protected).
1.5.3 Non Permitted Accessing to Protected areas in the EEPROM
This section refers to EEPROM accesses via the EEC (bit banging) or EERD (parallel read access)
registers. Following a write access to the write protected areas in the EEPROM, the hardware
responds properly on the PCIe* bus, but does not initiate any access to the EEPROM. Following a
read access to the hidden area in the EEPROM (as defined by word 12h), the hardware does not
access the EEPROM and returns meaningless data to the host.
Note: Using bit banging, the SPI EEPROM can be accessed in a burst mode. For example, providing an
opcode address and then reading or writing data for multiple bytes. The hardware inhibits an
attempt to access the protected EEPROM locations even in burst accesses.
Software should not access the EEPROM in a Burst Write mode starting in a non protected area
and continue to a protected one. In such a case, it is not guaranteed that the write access to any area
ever takes place.
1.6 EEPROM Map
Table 1 lists the EEPROM map used in the 82571EB/82572EI.
Table 1. 82571EB/82572EI EEPROM Map (Sheet 1 of 3)
Word Used
By 15 8 7 0 Image Value Function
00h
01h
02h
HW
HW
HW
Ethernet Address Byte 2
Ethernet Address Byte 4
Ethernet Address Byte 6
Ethernet Address Byte 1
Ethernet Address Byte 3
Ethernet Address Byte 5
IA(2,1)
IA(4,3)
IA(6,5) both
03h SW Compatibility 1 High Compatibility 1 Low both
04h SW OEM LED 2, 3
Configuration OEM LED 0, 1 Configuration 0000h both
05h SW EEPROM Major Version EEPROM Minor Version XXXXh both
06h
07h SW OEM Configuration FFFFh both
08h
09h SW PBA, Byte 1 PBA, Byte 3 PBA, Byte 2 PBA, Byte 4
0Ah HW Initialization Control 1 both
0Bh HW Subsystem ID both
0Ch HW Subsystem Vendor ID both
0Dh HW Device ID LAN 0

82571EB/82572EI EEPROM Information Guide
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0Eh HW Vendor ID both
0Fh HW Initialization Control 2 both
10h HW Software Defined Pins Control xxxxh LAN 1
11h HW Device ID LAN 1
12h HW EEPROM Sizing and Protected Fields both
13h HW Management Enable Bits Management Capabilities both
14h HW Initialization Control 3 xxxxh LAN 1
15h
16h HW Reserved
17h FW Firmware Start Address (including PHY Init Address) 0100h both
18h HW PCIe* Init Configuration 1 both
19h HW PCIe* Init Configuration 2 both
1Ah HW PCIe* Init Configuration 3 both
1Bh HW PCIe* Control both
1Ch HW LEDCTL 1 3 Default both
1Dh HW Reserved
1Eh FW Device Revision ID both
1Fh FW LEDCTL 0 2 Default both
20h HW Software Defined Pins Control xxxxh LAN 0
21h HW Functions Control
22h HW LAN Power Consumption both
23h HW Management Hardware Configuration Control xxxxh both
24h HW Initialization Control 3 xxxxh LAN 0
25h
. . .
2Ch HW Reserved
2Dh SW ETrack_ID (high)
2Eh SW ETrack_ID (low)
2Fh HW Vital Product Data (VPD) Pointer
Note: OEM configurable, see Section 1.8 for detailed
description.
Table 1. 82571EB/82572EI EEPROM Map (Sheet 2 of 3)
Word Used
By 15 8 7 0 Image Value Function

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Table 2. 82571EB/82572EI EEPROM Manageability Map
30h
31h
32h
33h
35h:34h
36h
37h
. . .
3Dh
3Eh
SW
PXE Word 0 (Software Use) Configuration
PXE Word 1 (Software Use) Configuration
PXE Word (Software Use) PXE Version
PXE Word (Software Use) EFI Version
PXE Word (copies of words 30h and 31h)
Reserved
Alternate MAC Address
…
iSCSI Boot Configuration Start Address
Reserved
3Fh Software Checksum, Words 00h Through 3Fh
FW Reserved for SerDes / PCIe* Ana and PHY Init both
1C0h
. . .
1FFh FW Saved for Firmware
(TBL, Loadable code. . .) both
Secured …
Table 1. 82571EB/82572EI EEPROM Map (Sheet 3 of 3)
Word Used
By 15 8 7 0 Image Value Function
Word Used
By 15 8 7 0 Image Value Function
40h:FFh ASF/Pass Through/BMC Configuration Area MNG
100h/40h HW MNG D0 Power Consumption MNG
101h/41h HW MNG D3 Power Consumption MNG
102h/42h HW IDE Device ID MNG
103h/43h HW Serial Port Device ID MNG
104h/44h HW IPMI/KCS Device ID MNG
105h/45h HW IDE Subsystem ID MNG
106h/46h HW Serial Port Subsystem ID MNG
107h/47h HW IPMI/KCS Subsystem ID MNG
108h/48h IDE Boot Control IDE
109h/49h
...
10Dh/4Dh HW Reserved
10Eh/4Eh IPMI Device Class Code Low MNG
10Fh/4Fh IPMI Device Class Code High MNG
FW Reserved for SerDes / PCIe* Ana and PHY Init both

82571EB/82572EI EEPROM Information Guide
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1.7 Hardware Accessed Words
This section describes the EEPROM words that are loaded by the 82571EB/82572EI hardware.
Most of these bits are located in configuration registers. The words are only read and used if the
Signature field in the EEPROM Sizing & Protected fields (word 12h) is valid.
Note: When changing a default value of a reserved bit, 82571EB/82572EI behavior is undefined.
1.7.1 Ethernet Address (Words 02h:00h)
The Ethernet Individual Address (IA) is a 6-byte field that must be unique for each Ethernet port
and each copy of the EEPROM image. The first three bytes are vendor specific. The value from
this field is loaded into the Receive Address Register 0 (RAL0/RAH0) after resets and after being
in D3.
The Ethernet address is loaded for LAN0 and bit 41, the least significant bit of the last Ethernet
address byte, and is inverted (bit 8 of Word 2) for LAN11.
Note: A default value of FFFFh means the word is not used for any purpose.
1.7.2 Initialization Control Word 1 (Word 0Ah)
The first word read by the 82571EB/82572EI contains initialization values that:
•Sets defaults for some internal registers
•Enables/disables specific features
•Determines which PCI configuration space values are loaded from the EEPROM
Word Used
By 15 8 7 0 Image Value Function
Flexible
Size up to
7Eh
FW
Flex
Filter Flexible Filter Data both
1 Word FW Flex
Filter Flexible Filter Length both
Flexible
Size Reserved
1. LAN1 is not applicable to the 82572EI.
Table 3. IA Byte Ordering Convention
IA Byte / Value
Vendor 1 2 3 4 5 6
Example 1 (Intel Original) 00 AA 00 Variable Variable Variable
Example 2 (Intel New) 00 A0 C9 Variable Variable Variable

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1.7.3 Subsystem ID (Word 0Bh)
If the Load Subsystem IDs in word 0Ah is set, this word is read in to initialize the Subsystem ID.
The default value is 0h.
1.7.4 Subsystem Vendor ID (Word 0Ch)
If the Load Subsystem IDs in word 0Ah is set, this word is read in to initialize the Subsystem
Vendor ID. the default value is 8086h.
Table 4. Initialization Control Word 1 (Word 0Ah)
Bit Name Description
15 Link Status
Change
Wake
Enable
Enables wake on link status change as part of APM wake capabilities.
0b = Disable.
1b = Enable.
14 Link Status
Change
Wake
Override
If set to 1b, wake on Link Status Change does not depend on the LNKC bit
in the Wake Up Filter Control register (WUFC). Instead, it is determined by
the APM setting in the WUC register.
0b = Do not override.
1b = Override.
13 Reserved Reserved. Must be set to 1b.
12 Reserved Reserved. Set to 0b.
11 FRCSPD Default setting for the Force Speed bit in the Device Control register
(CTRL[11]).
10 FD Default for duplex setting. Mapped to CTRL[0] and TXCW[5]. The
hardware default value is 1b.
9LRST Default setting for link reset (CTRL[3]). Should be set to 0b for hardware to initiate Auto-Negotiation (for SerDes mode) at power up or when asserting
a PCIe* reset without driver intervention. The image default is 0b..
8 Reserved Reserved. Set to 0b.
7 Reserved Reserved. Set to 0b.
6:5 Reserved Reserved. Set to 01b.
4 Reserved Reserved. Set to 0b.
3 Reserved Reserved. Set to 1b.
2 Reserved Reserved. Set to 1b.
1Load Subsystem
IDs
This bit, when set to 1b, indicates that the 82571EB/82572EI is to load its
PCIe* Subsystem ID and Subsystem Vendor IDs from the EEPROM
(words 0Bh, 0Ch).
0Load Vendor/
Device IDs
This bit, when set to 1b, indicates that the 82571EB/82572EI is to load its
PCIe* Vendor and Device IDs from the EEPROM (words 0Dh, 0Eh, and
11h).

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1.7.5 Device ID (Word 0Dh, 11h)
If the Load Vendor/Device IDs bit in the Initialization Control Word 1 (0Ah) is set, this word is
read in to initialize the Device ID of LAN 0 and LAN 1 functions, respectively. Its default value is
105Eh.
1.7.6 Vendor ID (Word 0Eh)
If the Load Vendor/Device IDs bit in the Initialization Control Word 1 (0Ah) is set, this word is
read in to initialize the Vendor ID. The default value is 8086h.
1.7.7 Initialization Control Word 2 (Word 0Fh)
This is the second word read by the 82571EB/82572EI and contains additional initialization values
that:
•Sets defaults for some internal registers
•Enables/disables specific features
Table 5. Initialization Control Word 2 (Word 0Fh)
Bit Name Description
15 APM PME# Enable Initial value of the Assert PME On APM Wakeup bit in the Wake Up
Control register (WUC.APMPME).
14 Reserved Reserved. Set to 0b.
13:12 Pause Capability Desired PAUSE capability for advertised configuration base page.
Mapped to TXCW[8:7].
11 ANE Auto-Negotiation Enable (for SerDes mode). Mapped to
TXCW[31].
10:8 Serial FLASH Size
Indication
Indicates Flash size according to the following equation: Size = 64
KB * 2** (Flash Size Indication field). For example, 64 KB up to
8 MB in the power of 2.
The Flash size impacts the requested memory space for the Flash
and Expansion ROM BARs in PCIe* configuration space.
7 Reserved Reserved. Set to 0b.
6PHY Power Down
Enable
When set, enables the PHY to enter a low-power state.
0b = Disable.
1b - Enable.
5 Reserved Reserved. Set to 1b.
4 Reserved Reserved. Set to 0b.
3 Reserved Reserved. Set to 0b.
2Enable SerDes
Power Down
When set, enables SerDes to enter a low power state when the
function is in Dr state.
0b = Disable.
1b = Enable.

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1.7.8 Software Defined Pins Control (Word 10h/20h)
These words are used to configure the initial settings of the Software Definable Pins.
Note: Word 10h is for LAN1 (Port 1/Port B) and Word 20h is for LAN0 (Port 0/Port A).
Bit Name Description
1 Enable Speed Smart Power Down.
When set, enables PHY Smart Power Down mode. Image default
is 0b.
0 Reserved Reserved. Set to 1b.
Table 5. Initialization Control Word 2 (Word 0Fh)
Table 6. Software Defined Pins Control (Word 10h/20h)
Bit Name Description
15 SDPDIR[3]
SDP3 Pin - Initial Direction.
This bit configures the initial hardware value of the SDP3_IODIR bit in the
Extended Device Control register (CTRL_EXT) following power up. This
relates to the SDP0/SDP1 ports, respectively, for LAN0/LAN1.
0b = Input.
1b = Output.
14 SDPDIR[2]
SDP2 Pin - Initial Direction.
This bit configures the initial hardware value of the SDP2_IODIR bit in the
Extended Device Control register (CTRL_EXT) following power up. This
relates to the SDP0/SDP1 ports, respectively, for LAN0/LAN1.
0b = Input.
1b = Output.
13:12 Reserved Reserved. Set to 00b.
11 LAN_DIS
LAN Disable.
When set to 1b, the appropriate LAN is disabled.
0b = Enable.
1b = Disable.
10 LAN _PCI_DIS
LAN PCI Disable.
When set to 1b, the appropriate LAN PCI function is disabled. For
example, the LAN is functional for MNG operation but is not connected to
the host through PCIe*.
0b = Enable.
1b = Disable.
9 SDPDIR[1]
SDP1 Pin - Initial Direction.
This bit configures the initial hardware value of the SDP1_IODIR bit in the
Device Control register (CTRL) following power up. This relates to the
SDP0/SDP1 ports, respectively, for LAN0/LAN1.
0b = Input.
1b = Output.

82571EB/82572EI EEPROM Information Guide
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Bit Name Description
8 SDPDIR[0]
SDP0 Pin - Initial Direction.
This bit configures the initial hardware value of the SDP0_IODIR bit in the
Device Control register (CTRL) following power up. This relates to the
SDP0/SDP1 ports, respectively, for LAN0/LAN1.
0b = Input.
1b = Output.
7 SDPVAL[3]
SDP3 Pin - Initial Output Value.
This bit configures the initial power on value output on SDP3 (when
configured as an output) by configuring the initial hardware value of the
SDP3_DATA bit in the Extended Device Control register (CTRL_EXT)
after power up. This relates to the SDP0/SDP1 ports, respectively, for
LAN0/LAN1.
6 SDPVAL[2]
SDP2 Pin - Initial Output Value.
This bit configures the initial power on value output on SDP2 (when
configured as an output) by configuring the initial hardware value of the
SDP2_DATA bit in the Extended Device Control Register (CTRL_EXT)
after power up. This relates to the SDP0/SDP1 ports, respectively, for
LAN0/LAN1.
5:4 Reserved Reserved. Set to 00b.
3Disable1000in
non-D0a When set to 1b, disables 1000 Mb/s operation in non-D0a states.
2D3COLD_ WAKEUP_
ADV_EN
Configures the initial hardware default value of the ADVD3WUC bit in the
Device Control register (CTRL) following power up.
0b = Not advertised.
1b = Advertised.
1 SDPVAL[1]
SDP1 Pin - Initial Output Value.
This bit configures the initial power on value output on SDP1 (when
configured as an output) by configuring the initial hardware value of the
SDP1_DATA bit in the Device Control register (CTRL) after power up.
This relates to the SDP0/SDP1 ports, respectively, for LAN0/LAN1.
0 SDPVAL[0]
SDP0 Pin - Initial Output Value.
This bit configures the initial power on value output on SDP0 (when
configured as an output) by configuring the initial hardware value of the
SDP0_DATA bit in the Device Control register (CTRL) after power up.
This relates to the SDP0/SDP1 ports, respectively, for LAN0/LAN1.
Table 6. Software Defined Pins Control (Word 10h/20h)

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1.7.9 EEPROM Sizing and Protected Fields (Word 12h)
Note: The software device driver has read but no write access to this word via the EEC and EERD
registers. Write access is possible only through an authenticated firmware interface.
1.7.10 Management Capabilities (Word 13h, Lower Byte)
This word contains the 82571EB/82572EI’s manageability capabilities and is only used by device
software. It should not enable any capability (in the upper byte) that is not enabled in this byte. The
OEM is responsible for initializing this byte.
1.7.11 Management Enable Byte (Word 13h, Upper Byte)
This byte contains information for firmware regarding enabled manageability functions. After this
byte is updated, the software device driver should notify firmware of the change. If the
manageability subsystem is in a mode where its host interface is active, then it should be done by
the manageability host command. If the host interface is inactive, the software device driver should
wake the manageability subsystem by asserting the Wake Management Clock (WMNG) bit in the
Software Semaphore (SWSM) register.
Table 7. EEPROM Sizing and Protected Fields (Word 12h)
Bit Name Description
15:14 Signature The Signature field indicates to the device that there is a valid EEPROM
present. If the Signature field is not 01b, the other bits in this word are
ignored, no further EEPROM read is performed and default values are used
for the configuration space IDs.
13:10 EEPROM
Size
These bits indicate the EEPROM actual size:
0000b = 128 bytes
0001b = 256 bytes
0010b = 512 bytes
0011b = 1 KB
0100b = 2 KB
0101b = 4 KB
0110b = 8 KB
0111b = 16 KB
1000b = 32 KB
1001b = 64 KB
1010b - 1011b = Reserved
9:4 Reserved Reserved. Set to 00h.
3:0 Reserved Reserved. Set to 00h.

82571EB/82572EI EEPROM Information Guide
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Note: The Management Enable Byte word 13h must be set to 000b (no manageability) when using the
ASF EEPROM image. It is the ASF agent’s responsibility to set this field to 001b for ASF mode.
If the additional PCI functions (SMS, IDE, COM) are enabled in the EEPROM, the firmware is
notified of their relevant functionality.
When no manageability mode is present or enabled and no other functionality is enabled (SMS,
IDE, COM), the manageability subsystem is not functional and the host interface is not functional.
In other words, it does not respond to accesses made to CSR addresses 8800h through 8FFFh.
The EEPROM contains information for the enabled mode only. Additional information on mode
operation (fail over enable, active port, etc.) is available in the manageability CSR area if the block
is functional.
1.7.12 Initialization Control 3 (Word 14h/24h, Lower Byte)
Note: Word 14h is used for LAN 1. Word 24 is used for LAN 0.
Table 8. Initialization Control 3 (Word 14h/24h, Lower Byte)
Bit Name Description
7:1 Reserved Reserved. Set to 0h.
0No PHY Reset for
IDE
No PHY reset when IDE or SOL is enabled. When asserted, this bit
can prevent the PHY reset signal according to the
MANC.BLK_PHY_RST value. This bit should be set to the same value
at both words (14h, 24h) to reflect the same option to both LANs.
0b = PHY reset always asserted by a PCIe* reset.
1b = PHY reset blocked by firmware.

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1.7.13 Initialization Control 3 (Word 14h/24h Upper Byte)
This word controls general initialization values.
Note: If applicable, word 14h is used for LAN1 (Port 1/Port B). Word 24 is used for LAN0 (Port 0/Port
A).
Table 9. Initialization Control 3 (Word 14h/24h Upper Byte)
Bit Name Description
15 Reserved Reserved. Set to 0b.
14 Multiple Read Req
Ena
When set to 0b, the 82571EB/82572EI initiates one Tx DMA request
at a time. When set to 1b, the 82571EB/82572EI can initiate up to four
outstanding multiple TX DMA requests. This bit sets the default value
of the MULR field (bit 28) in the Transmit Control (TCTL) register.
13 LAN Flash
Disable When set to 1b, disables the Flash logic. Flash access BAR in the PCI configuration space is disabled.
12 Interrupt Pin
Controls the value advertised in the Interrupt Pin field of the PCI
configuration header for a given port. A value of 0b, reflected in the
Interrupt Pin field, indicates that the 82571EB/82572EI uses INTA#; a
value of 1b indicates that the 82571EB/82572EI uses INTB#.
Note: If a single port of the 82571EB/82572EI is enabled, this value is
ignored and the Interrupt Pin field of the enabled port reports INTA#
usage.
11 LAN Boot
Enable A value of 1b disables the Expansion ROM BAR in the PCI configuration space.
10 APM Enable
Initial value of Advanced Power Management Wake Up Enable in the
Wake Up Control register (WUC.APME). Mapped to CTRL[6] and to
WUC[0].
0b = Disable APM.
1b = Enable APM.
9:8 Link Mode
Initial value of the Link Mode field (bits 22 and 23) in the Extended
Device Control register (CTRL_EXT.LINK_MODE), specifying which
link interface and protocol is used by the MAC portion of the 82571EB/
82572EI.
00b - MAC operates in GMII/MII mode with internal copper PHY
(1000Base-T)
01b = Reserved.
10b = Reserved.
11b = MAC operates in TBI mode when using internal SerDes.