Intel 82801EB User manual

Intel®82801EB (ICH5) and
Intel®82801ER (ICH5R)
Serial ATA Controller
Programmer’s Reference Manual (PRM)
July 2003
Document Number: 252671-002
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL
DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR
WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT,
COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining
applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® ICH5 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2003, Intel Corporation

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Contents
1Introduction.......................................................................................................................... 7
1.1 Overview................................................................................................................. 7
2Conventions ........................................................................................................................ 9
2.1 Register Access...................................................................................................... 9
2.2 Keywords ................................................................................................................ 9
3Intel®ICH SATA Controller Basic Attributes...................................................................... 11
3.1 Legacy Sub-Mode................................................................................................. 11
3.2 Native Sub-Mode .................................................................................................. 11
3.3 Host Controller Configurations ............................................................................. 12
4Theory of Operation .......................................................................................................... 13
4.1 Compatible Configuration ..................................................................................... 13
4.1.1 Additional Register Support .................................................................. 14
4.1.1.1 MAP – Address Map Register – Offset 90h......................... 14
4.1.2 Compatible Configuration - Option 1..................................................... 15
4.1.3 Compatible Configuration - Option 2..................................................... 16
4.1.4 Compatible Configuration - Option 3 (Combined)................................. 17
4.2 Enhanced Configuration ....................................................................................... 20
4.2.1 PI - Programming Interface Register – Offset 09h................................ 21
4.2.2 MAP Register Programming ................................................................. 23
4.3 PCS - Port Control and Status Register – Offset 92h........................................... 23
4.3.1.1 Port Enabling/Disabling ....................................................... 24
4.3.1.1.1 BIOS Considerations ........................................... 24
4.3.1.1.2 Enabling/Disabling a SATA Port from an
Operating System Driver ..................................... 25
4.3.1.1.3 Enabling/Disabling a SATA Port from ACPI ........ 25
4.4 Device Presence Detect ....................................................................................... 26
4.4.1 Hardware and Software Considerations ............................................... 26
4.4.2 Device Detection – Software Examples................................................ 28
4.5 ATA Swap Bay Support ........................................................................................ 28
4.6 Implementing the Intel®ICH5 SATA Host Controller in ACPI Namespace .......... 29
Appendix A – Coding Examples ........................................................................................................... 31
A.1 Enabling/Disabling SATA Ports from a WDM Driver ............................................ 31
A.2 Enabling/Disabling SATA Ports in the _PSx Control Method ............................... 33
A.3 Device Presence Check – Using I/O .................................................................... 37
A.4 Device Presence Check – Using ACPI................................................................. 39
A.5 ACPI Control Method (GSPS) .............................................................................. 43
Appendix B – Example ACPI Namespace............................................................................................ 47

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Figures
Figure 1. Compatible Configuration - Option 1.................................................................. 15
Figure 2. Compatible Configuration - Option 2.................................................................. 16
Figure 3. Compatible Configuration - Option 3.................................................................. 17
Figure 4. Compatible Configuration - Option 3a................................................................ 18
Figure 5. Compatible Configuration - Option 3b................................................................ 19
Figure 6. Compatible Configuration - Option 3c................................................................ 19
Figure 7. Compatible Configuration - Option 3d................................................................ 20
Figure 8. Enhanced Configuration..................................................................................... 21
Figure 9. Power-on to Device Ready Elapsed Time ......................................................... 27
Tables
Table 1. Intel®ICH5 Device IDs .......................................................................................... 7
Table 2. Valid BIOS Option for the Programming Interface Register................................ 22
Table 3. Illegal BIOS Options for the Programming Interface Register ............................ 22

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Revision History
Revision
Number
Description Revision Date
-001 Initial Release April 2003
-002 Updated register/bit names to match Intel® 82801EB I/O Controller
Hub 5 (ICH5) / Intel® 82801ER I/O Controller Hub 5 R (ICH5R)
Datasheet
July 2003

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Introduction
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1 Introduction
1.1 Overview
This document was prepared to assist BIOS software providers and Operating System (OS)
providers in supporting the Intel®82801EB (ICH5)/ 82801ER (ICH5R) SATA Controller feature
set and programming interface.
It is assumed that the reader has a working knowledge of ATA/SATA architecture. Also, the
reader should have an understanding of ATA, BIOS (including ACPI) and device driver
development for the target operating systems.
This document also describes functions that the BIOS and the OS shall perform in order to ensure
correct and reliable operation of the platform. This document will be supplemented from time to
time with specification updates. The specification updates contain information relating to the latest
programming changes. Check with your Intel representative for availability of specification
updates.
This document does not cover any of the software requirements around configuration of the RAID
controller in ICH5R.
The recommendations in this Programmers Reference Manual (PRM) apply to the following
components:
Table 1. Intel®ICH5 Device IDs
Note: In this document, references to an ICHx device that has a corresponding ICHx-M/R device will
include the ICHx-M/R part (e.g., reference to ICH5 includes ICH5R).
Intel® ICH Device Device Function
Number
PCI Device ID PCI Vendor ID
Intel®82801EB (ICH5) and
Intel®82801ER (ICH5R)
02h 24D1 8086h

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Conventions
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2 Conventions
2.1 Register Access
This document uses the following notation as related to register access: RegOffset.BitOffset.
Where:
 RegOffset specifies the name of the register to be accessed (either in I/O or PCI configuration
space)
 BitOffset specifies the name of a bit contained within RegOffset that is to be accessed.
Example (Uses the Class Code register defined in the table below):
Assumes the following standard PCI configuration register (Class Code) with
CC.SCC refers to the Sub Class Code (SCC - bits 0:7) implemented within the Class Code (CC –
offset 0Ah) register in the PCI Configuration space.
Offset 0Ah - Class Code Register (CC)
Bits Type Reset Description
15:08 RO 01h Base Class Code (BCC): Indicates that this is a mass storage device.
07:00 RO 01h Sub Class Code (SCC): Indicates that this is an IDE device.
2.2 Keywords
• Mandatory - A keyword indicating items to be implemented as defined by this
document.
• System Software – A keyword that refers to both BIOS and operating system software
unless specifically stated otherwise.
• Shall - A keyword indicating a mandatory requirement. Equivalent to the term “must.”
• Should - A keyword indicating flexibility of choice with a strongly preferred alternative.
Equivalent to the phrase “it is recommended.”

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Intel® ICH SATA Controller Basic Attributes
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3 Intel®ICH SATA Controller Basic
Attributes
The register set for the ICH5 SATA controller is basically identical to that of the integrated
parallel ATA controller. Because the underlying SATA functionality is transparent to operating
system software, it need not have any special knowledge about SATA or SATA devices. In
addition to supporting the same programming interface, the SATA host controller can also be
configured to use legacy ATA resources as well as native PCI resources.
3.1 Legacy Sub-Mode
A host controller (channel) configured for legacy sub-mode of operation has the following
requirements:
• Has its Programming Interface register set for legacy mode
• Shall interrupt via IRQ14 (primary channel) and IRQ15 (secondary channel)
• Command and control block are accessed at fixed I/O locations:
 Command Block Offset: 01F0h for primary and 0170h for secondary
 Control Block Offset: 03F4h for primary and 0374h for secondary
3.2 Native Sub-Mode
A host controller (channel) configured for native sub-mode of operation has the following
requirements:
• Has its Programming Interface register set for native mode.
• Shall interrupt via the INTA#.
• Command and control blocks are accessed via I/O space specified by the following BARs
located by the following PCI configuration offsets:
 Offset 10h – Primary Command Block Base Address
 Offset 14h – Primary Control Block Base Address
 Offset 18h – Secondary Command Block Base Address
 Offset 1Ch – Secondary Control Block Base Address

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3.3 Host Controller Configurations
The SATA host controller can function independently of, or in conjunction with the parallel ATA
(P-ATA) host controller. The ICH5 can support a maximum of six ATA devices: four parallel
ATA device plus two serial ATA devices.
The flexibility and software transparency of the SATA host controller presents an interesting
problem for older operating systems that do not comprehend or support the native mode of
operation (i.e., the ports/channels on both controller’s could be configured to use legacy resources,
which would result in hardware resource conflicts). To prevent this problem, ICH5 supports
multiple SATA and P-ATA device configurations: compatible and enhanced. These configurations
are discussed on the next section.

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4 Theory of Operation
This section describes the proper usage and programming of the SATA host controller by BIOS
and the operating system when the host controller is operating in compatible or enhanced
configuration.
4.1 Compatible Configuration
The compatible configuration is for the express purpose of maintaining backward-compatibility
with those operating systems that do not comprehend native mode of operation. In this
configuration, a maximum of four ATA (serial and/or parallel) devices on the primary and/or
secondary channels can be supported. This mode allows both the primary and secondary channels
to be configured for legacy and/or native sub-modes of operation.
Since the ICH5 supports up to six ATA devices (parallel + serial), it is possible for an end-user to
populate a platform with a combination of parallel and serial ATA devices. The fact that the ICH5
supports up to six ATA devices is not necessarily an issue for older operating systems; it is the fact
that both the P-ATA controller and SATA controller can be configured to consume legacy
resources (see Section: 3.1 Legacy Sub-Mode) that causes the issues (i.e., the primary and
secondary channel interfaces will attempt to share the same resources).
The compatible configuration solves this dilemma. The compatible configuration allows certain
device configurations to be accessed by software without the issue of legacy resource conflicts and
yet remain backward compatible with operating systems that don’t implement native mode
functionality.
The ICH5 supports three compatible configuration options. These options are summarized as
follows and are discussed in detail in the following sections:
• P-ATA devices only (maximum of four) – Compatible Configuration Option 1
• SATA devices only (maximum of two) – Compatible Configuration Option 2
• P-ATA (maximum of two) and SATA devices (maximum of two) – Compatible Configuration
Option 3
Note: Proper support of these options requires that system BIOS provide a BIOS setup option (that is
subsequently saved in nonvolatile memory) that allows the end user to select an option that is
appropriate for their particular hardware/operating system configuration. To insure backward
compatibility with existing software, BIOS is not permitted to dynamically select a configuration.

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4.1.1 Additional Register Support
Support of certain Compatible configuration options requires that the ICH5 implement an
additional hardware register that is configurable via BIOS. This register is located in the SATA
function’s PCI configuration space at offset 90h and is defined below. The usage model for this
register is described in subsequent sections.
4.1.1.1 MAP – Address Map Register – Offset 90h
This register is set by BIOS during POST. The exact value programmed into this register is based
on a BIOS setup option. Dynamic modifications of this register by BIOS as a result of POST or
some other event (e.g., docking event) is not permitted, as the underlying operating system
software may not comprehend the new device topology and may result in undefined behavior.
Bit Type Reset Description
7:3 RO 0 Reserved
2:0 RW 000
Map Value (MV): The value in the bits below indicate the address range the
SATA port responds to, and whether or not the P-ATA and SATA functions are
combined.
Bits Mapping
000 Non-combined, SATA Port 0 is primary master, SATA Port 1 is
secondary master
001 Non-combined, SATA Port 0 is secondary master, SATA Port 1
is primary master
100 Combined, SATA Port 0 is primary master, SATA Port 1 is
primary slave, P-ATA is secondary
101 Combined, SATA Port 0 is primary slave, SATA Port 1 is
primary master, P-ATA is secondary
110 Combined, P-ATA is primary, SATA Port 0 is secondary master,
SATA Port 1 is secondary slave
111 Combined, P-ATA is primary, SATA Port 0 is secondary slave,
SATA Port 1 is secondary master
Caution: Programming the MAP.MV register with values other than those specified above will result in
undefined hardware behavior.
Note: The P-ATA host controller does not implement this register.

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4.1.2 Compatible Configuration - Option 1
This option is selected when one or more P-ATA devices are to be used. SATA device(s) may or
may not be attached to the SATA ports, but will not be accessible to software. Figure 1 illustrates
this configuration:
Figure 1. Compatible Configuration - Option 1
S
Intel®ICH5
P-ATA
S-ATA
M
M
S
Primary
Secondary
Port 0
Port 1
Disabled
Note: In the figure above, devices represented by dotted lines may be attached, but are not accessible to
software.
Note: This configuration requires no additional programming of the Port Mapping register, as in this
configuration it has no effect on the P-ATA or SATA functions.
To enable this configuration, system BIOS:
1. Shall not program the SATA (Device 31, Function 2) controller’s base address registers
(Offsets 10h – 24h in PCI configuration space).
2. Shall disable access to the SATA controller’s I/O space by programming the command
register (PCI configuration, offset 04h, bit 0) with a 0.
3. Shall disable the SATA function by programming bit 2 (D31_F2_DISABLE) of the Function
Disable register (Device 31, Function 0, Offset F2h) with a 1. This will insure that the PCI
configuration registers associated with the SATA function are not decoded and thus will
insure that operating system configuration software does not enumerate and configure the
SATA function.
4. Shall insure that the SATA ports are not enabled. This is accomplished by writing ‘0’ to bits
1:0 in the Port Control and Status (PCS) register.
5. Shall program the P-ATA registers appropriately (the exact details are beyond the scope of
this document).

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4.1.3 Compatible Configuration - Option 2
This option is selected when one or more (maximum of two) SATA devices are to be used. P-ATA
device(s) may or may not be attached to the P-ATA channels, but will not be accessible to
software. Figure 2 illustrates this configuration:
Figure 2. Compatible Configuration - Option 2
M
Intel®ICH5
P-ATA
S-ATA
Port 1 M
Logical Primary
Port 0
Logical Secondary
BIOS Selectable
S
M
M
S
Disabled
Note: In the figure above, devices represented by dotted lines may be attached, but are not accessible to
software.
Note: In this configuration, software reads and writes to the slave device registers will result in a master
abort and as such reading from the slave device registers will return all 1. The Drive/Head register
(offset 06h in the command block) is the exception.
To enable this configuration, system BIOS:
1. Shall not program the P-ATA (Device 31, Function 1) controller’s base address registers
(Offsets 10h – 24h in PCI configuration space).
2. Shall disable access to the P-ATA controller’s I/O space by programming the command
register (PCI configuration, offset 04h, bit 0) with a 0.
3. Shall disable the P-ATA function by programming bit 1 (D31_F1_DISABLE) of the
Function Disable register (Device 31, Function 0, Offset F2h) with a 1. This will insure that
the PCI configuration registers associated with the P-ATA function are not decoded and thus
will insure that operating system configuration software does not enumerate and configure the
P-ATA function.
4. Shall program the MAP.MV register as follows:
Note: These mappings represent a master-master device arrangement.

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• MAP.MV == ‘000b’. This indicates that a SATA device on port 0 behaves as a master device
on the logical primary channel and a device on port 1 behaves as a master device on the
logical secondary channel.
The flexibility of the mapping register also allows the following configuration:
• MAP.MV == ‘001b’. This indicates that a SATA device on port 0 behaves as a master device
on the logical secondary channel and a device on port 1 behaves as a master device on the
logical primary channel.
5. Shall program the SATA registers appropriately. Because the programming interface is
identical to that of P-ATA, BIOS should follow the same programming guidelines as used for
the P-ATA (the exact details are beyond the scope of this document).
4.1.4 Compatible Configuration - Option 3 (Combined)
This option is selected when at least one SATA device (maximum of two) and at least one P-ATA
device (maximum of two) are connected to both SATA and P-ATA host controllers and are both
accessible by software. This configuration is referred to as the “combined” mode. In combined
mode of operation, devices can be supported in legacy mode, native mode or both. In this mode, it
is expected that the host controller will be programmed for legacy mode of operation. It is
important to note that in this configuration, the SATA and P-ATA host controllers share
functionality but appear as a single PCI function. In this case, the actual P-ATA function is hidden
from system software (i.e., cannot be enumerated or accessed directly) but P-ATA devices
connected to the function (primary channel only) may still be accessed. These devices are accessed
via the standard, P-ATA compatible register set exposed by the SATA controller. Figure 3
illustrates this configuration:
Figure 3. Compatible Configuration - Option 3
Intel® ICH5
S-ATA
P-ATA
Port 0
Port 1
M
S
Viewed as a
single logical
channel
M
S
M
S
Physical Primary/Secondary
Channels are Mutually Exclusive
Logical Primary/Secondary
Channel Assignment
are BIOS Selectable

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To enable this configuration, the system BIOS:
1. Shall not program the P-ATA (Device 31, Function 1) controller’s base address registers
(Offsets 10h – 24h in PCI configuration space).
2. Shall disable access to the P-ATA controller’s I/O space by programming the command
register (PCI configuration, offset 04h, bit 0) with a 0.
3. Shall disable the P-ATA function by programming bit 1 (D31_F1_DISABLE) of the Function
Disable register (Device 31, Function 0, Offset F2h) with a 1. This will insure that the PCI
configuration registers associated with the P-ATA function are not decoded and thus will
insure that operating system configuration software does not enumerate and configure the P-
ATA function.
4. Shall program the MAP.MV register as follows:
• If SATA is the primary channel and P-ATA is the secondary channel and Port 0 device is
primary master and Port 1 device is primary slave then MAP.MV == ‘100b’. Figure 4
illustrates this configuration:
Figure 4. Compatible Configuration - Option 3a
S-ATA
P-ATA
Port 0
Port 1
M
S
Logical Primary
Channel
Intel® ICH5
M
S
Physical Primary
Channel
Not Used
M
S
Logical Secondary
Channel
Note: In the figure above, devices represented by dotted lines may be attached, but are not accessible to
software.
• If SATA is the primary channel and P-ATA is the secondary channel and Port 0 device is
primary slave and Port 1 device is primary master then MAP.MV == ‘101b’. Figure 5
illustrates this configuration:

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Figure 5. Compatible Configuration - Option 3b
M
S
S-ATA
P-ATA
Port 0
Port 1
Loical Primary
Channel
Intel® ICH5
M
S
Physical Primary
Channel
Not Used
M
S
Logical Secondary
Channel
Note: In the figure above, devices represented by dotted lines may be attached, but are not accessible to
software.
• If SATA is the secondary channel and P-ATA is the primary channel and Port 0 device is
secondary master and Port 1 device is secondary slave then MAP.MV == ‘110b’. Figure 6
illustrates this configuration:
Figure 6. Compatible Configuration - Option 3c
S
M
S-ATA
P-ATA
Port 0
Port 1
Logical Secondary
Channel
Intel® ICH5
M
S
Physical Secondary
Channel
Not Used
M
S
Logical Primary
Channel
Note: In the figure above, devices represented by dotted lines may be attached, but are not accessible to
software.
• If SATA is the secondary channel and P-ATA is the primary channel and Port 0 device is
secondary slave and Port 1 device is secondary master then MAP.MV == ‘111b’. Figure 7
illustrates this configuration:

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Figure 7. Compatible Configuration - Option 3d
M
S
S-ATA
P-ATA
Port 0
Port 1
Logical Secondary
Channel
Intel® ICH5
M
S
Physical Secondary
Channel
Not Used
M
S
Logical Primary
Channel
Note: In the figure above, devices represented by dotted lines may be attached, but are not accessible to
software.
4.2 Enhanced Configuration
The enhanced configuration is intended for those operating systems (e.g., Microsoft Windows*
2000, Windows* XP) that comprehend both legacy and native modes of operation. It is the
preferred configuration for system software due to the maximum flexibility that it offers. Enhanced
mode allows both the P-ATA and SATA host controllers to be used, providing a maximum of six
ATA (4 P-ATA + 2 SATA) devices that can be used simultaneously.
Note: In this configuration, the P-ATA controller must be programmed for legacy mode while the SATA
controller must be programmed for native mode of operation. Figure 8 illustrates the enhanced
mode configuration: