Intel iSBC 546 Quick user guide

iSBC® 546/547/548
HIGH PERFORMANCE
TERMINAL CONTROLLERS
HARDWARE REFERENCE MANUAL
Order Number: 122704-001
Copyright 1986, Intel Corporation, All Rights Reserved
I Intel Corporation,
3065 Bowers Avenue, Santa Clara, California 95051
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11
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Copyright 1985, Intel Corporation, All
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REV. REVISION HISTORY
DATE
-001 Original Issue. 2/86
iii/tv

PREFACE
This manual provides information about the iSBC 54B and iSBC 547
Eight Channel Terminal Controllers and the iSBC 546 Terminal and
Printer Controller. The iSBC 548 and iSBC 547 boards are
functionally identical, but the iSBC 547 is a larger form factor
(10" x 12") board with backpanel connectors on-board. The iSBC 546
is a four channel board with a clock calendar and a centronix
printer interface.
General information about all three boards is provided in Chapter
1. Chapter 2 provides a block diagrams and functional descriptions
of the boards. Chapter 3 provides the information required to
install the board. Programming information is provided in Chapter
4 as well as in Appendix A and B. Connector pin-out information for
all boards is shown in Chapter 5. If you need to refer to the
schematic diagrams see Chapter 6.
For reference purposes Appendix A provides jumper information for
the boards. Appendix B covers the board firmware.
In addition to this manual you will need the following reference
material ( all are available from the Intel Literature Department,
see page ii for address).
o Intel MULTIBUS Handbook, Order Number 210883
o
Microsystem Components Handbook, Order Number 230843
o
Serial Communications Controller Technical Manual,
Order Number 230834.
v

CONTENTS ]
PAGE
CHAPTER 1
GENERAL INFORMATION
1. 1 Introduction .................................... " 1-1
1.2 Board Features ................................... l-l
1.3 Board Description ................................ 1-2
1.3.1 iSBC 546 Board Description .................. 1-2
1.3.2 iSBC 547 Board Description .................. 1-3
1.3.3 iSBC 548 Board Description .................. 1-3
1.4 Specifications ................................... 1-8
CHAPTER 2
BOARD OPERATION
2 • 1 Introduction .................................... " 2-1
2.2 iSBC 547 and iSBC 548 Functional Descriptions .. 2-l
2.3 iSBC 546 Functional Description ................. 2-4
CHAPTER 3
INSTALLATION
3 • 1 Introduction ..................................... 3-1
3.2 Unpacking And Inspection ......................... 3-l
3.3 Compatible Equipment .......•..................... 3-l
3.4 Installation Considerations ...................... 3-2
3.4.1 Connector Configurations ...................... 3-2
3.4.2 Battery Backup ................................ 3-3
3.4.3 Cabling ....................................... 3-6
3.5 Installation Procedures .......................... 3-9
CHAPTER 4
PROGRAMMING CONSIDERATIONS
4.1 Introduction ..................................... 4-1
4 • 2 Jumpers .......................................... 4-1
4.3 Addressing ....................................... 4-1
4.4 Programming Considerations ....................... 4-3
4.4.1 Firmware ...................................... 4-3
4.4.2 80186 Processor Programming Considerations .... 4-3
4.4.3 8255 Programming .............................. 4-6
4.4.4 DSR Port ...................................... 4-7
4.5 Baud Rate Programming (All Boards) ............... 4-7
vii

CONTENTS (continued)
PAGE
CHAPTER 5
INTERFACING INFORMATION
5.1 Introduction .... to ••••••••••••••••••••••••••••••• • 5-1
MULTI BUS
Information ........................... 5-1
5.2
5.3
5.4
serial Interfaces ................................ 5-6
Printer InterfaCE~ (iSBC 546 Only) ............... 5-11
CHAPTER 6
SERVICE ASSISTANCE INFORMATION
6 -1 Introduction ...................................... 6-1
6-2 Service and Repair Assistance .................... 6-1
6-3 Service Diagrams .................................. 6-3
APPENDIX A
JUMPER INFORMATION
A.1 Introduction ...................................... A-1
A.2 Flag Byte Address Jumpers ........................ A-4
A.3 MULTIBUS Interrupt Jumpers ..................... A-5
A.4 Memory Mapping Jumpers ........................... A-5
APPENDIX B
FIRMWARE
B.1 Introduction ...................................... B-1
B.2 Firmware Overvie'iliT ................................ B-1
B.2.1 Firmware Operation ............................ B-4
B.2.2 Recommendations For High Performance .......... B-5
B.3 Functional Architecture .......................... B-6
B.3.1 structures of Dual Ported RAM ................. B-6
B.3 . 1. 1 Test EnginE~ering Boot Area ................. B-7
B.3.1.2 static Structures .......................... B-8
B.3.1.3 Dynamic Structures ......................... B-10
B. 3 . 1 . 4 Queue. . . . . ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 0
B.3.1.5 Receive Buffers ............................ B-11
B.3.1.6 Transmit Buffers ........................... B-11
B.3.2 Inter-Processor Messages ...................... B-11
B.3.2.l Host CPU to Controller Messages ............ B-ll
B.3.2.1.1 Initialize ............................... B-12
B.3.2.1.2
B.3.2.1.3
B.2.2.1.4
B.3.2.1.5
B.3.2.1.6
B.3.2.1.7
B.3.2.1.8
Enable .. ~I •••••••••••••••••••••• " ••••••••• B-13
Disable. ~ ........................ ' ........ . B-14
Conf igurE~ ...................... " ......... B-15
Transmit Buffer .......................... B-20
Abort Transmit ........................... B-2 2
Suspend Transmit ............... " ......... B-23
Resume Transmit ................ " ......... B-24
viii

TABLEfJ (continued)
3-2 Pin to Pin Wiring List •.....•.......•..•.•...•.... 3-7
5-1 MULTI BUS Connector Pl Pin Assignments ......•.... 5-l
5-2 MULTI BUS Connector Pl Signal Descriptions ....... 5-3
5-3 Connector P2 Pin Assignments ...................... 5-5
5-4 Serial Connectors Pin Assignments, iSBC 546 ...... 5-6
Board
5-5 Serial Connectors Pin A!;signments, iSBC 547 ...... 5-7
Board
5-6 Serial Connectors Pin Assignments, iSBC 548 ...... 5-9
Board
5-7 Printer Interface Connec:::tor J5 Pin Assignments .... 5-ll
5-8 Connector J5 Signal Desc:::riptions .................. 5-12
A-l Jumper Combinations iSBC 546 Boards .....••....... A-l
A-2 Jumper Combinations iSBC 547/548 Boards .......... A-3
A-3
Flag Byte Address options And Jumpers ............. A-4
A-4 Memory Map jumpers and Addresses .................. A-6
B-1 iSBC 546/547/548 Firmware Features ............... B-2
B-2 Confidence Test Result Codes ..•..........•........ B-59
FIGUlRES
1-1 iSBC 546, iSBC 547 and iSBC 548 Boards ........ 1-5
Block Diagram
1-2 iSBC 548 High Performance Terminal Controller ... 1-6
1-3 iSBC 547 High Performance Terminal Controller ... 1-6
1-4
iSBC 548 High Performance Terminal Controller ... 1-7
2-1 iSBC 547 and iSBC 548 Functional Block Diagram.2-2
2-2 iSBC 546 Functional BLock Diagram ............... 2-6
3-1 iSBC 546 Board Connector Locations ............. 3-4
3-2 iSBC 547 Board Connector Locations .............. 3-5
3-3 iSBC 548 Board Connector Locations .............. 3-6
3-4 iSBC 548 RS232 Cable Construction ............... 3-8
4-1 iSBC 546/547/548 Boards Memory Map .............. 4-2
6-1 Territorial Service Telephone Numbers ............ 6-2
6-2 iSBC 548 Schematic Diagram ...................... 6-4
6-3
iSBC 547 Schematic Diagram ...................... 6-l5
6-4 iSBC 546 Schematic Diagram ...................... 6-27
A-l iSBC 546 Board Jumper Location .................. A-7
A-2 iSBC
547 Board Jumper Location .................. A-8
A-3 iSBC
548 Board Jumper Location .................. A-9
B-1 Layout of Shared (Dual Port) Memory .............. B-6
B-2 Test Engineering Boot Area Layout ................ B-7
B-3
static Structure Area Layout ..................... B-9
B-4 Dynamic Structure Layout ......................... B-10
B-5 Layout of Queue Area ............................. B-10
B-6 Initialize Message Format ........................ B-12
x

B-7
B-8
B-9
B-10
B-11
B-12
B-13
B-14
B-15
B-16
B-17
B-18
B-19
B-20
B-21
B-22
B-23
B-24
B-25
B-26
B-27
B-28
B-29
B-30
B-31
B-32
B-33
B-34
B-35
B-36
B-37
B-38
B-39
FIGURES (continued)
PAGE
Enable Message F0rIl1at ................... " ........ B-13
Disable Message Format .................. " ........ B-14
Configure Message Pormat ................ " ........ B-15
Transmit Buffer Message Format .......... " ........ B-21
Abort Transmit Message Format ........... " ........ B-22
Suspend Transmit Message Format ......... " ........ B-23
Resume
Transmit Message Format .......... " ........ B-24
Assert DTR Message Format •.............. " ........ B-25
Set CTS and CD GatE~s Message Format ..... " ........ B-26
Clear CTS and CD Gates Message Format ... " ........ B-27
Set DSR Report Message Format ........... " ........ B-28
Clear DSR Report Message Format •........ " ........ B-29
Set RI Report Message Format ............ ' ......... B-30
Clear RI Report Message Format .......... ' ......... B-31
Clear DTR Message Format ................ , ......... B-32
Set Break Message Format ................ ' ......... B-33
Clear Break Message Format ....................... B-34
Download
Message Format ................. ' ......... B-37
Execute Command Message Format ................... B-38
Clear Receive Buffer Command Message Format ...... B-40
Transmit Complete Message Format ................. B-41
Input Available message Format ................... B-43
Download
Complete 'Message Format ................. B-44
Carrier Detect Message Format .................... B-45
Carrier Loss Message Format .....••.•............. B-46
Initialization Responses Message Format .......... B-47
Autobaud Complete Message Format ................. B-48
Special Character Received Message Format ........ B-49
DSR Detected Message Format ...................... B-50
DSR Lost Message Format .......................... B-51
RI Detected Message Format ....................... B-52
RI Lost Message Format ........................... B-53
EPROM Checksum .... " .............................. B-60
xi