Kaya Instruments KY-FGK User manual

Komodo CXP Reference Guide
(Part-No. KY-FGK)
July 2018
20 aMesila St., N e s h e r 3 6 88520, Is r a e l
P O B 2 5 0 0 4 , H a i f a 3 1 2 5 0 0 1 , I s r a e l
T el:( +9 72 ) -72- 2 72 3 5 0 0 F a x: ( + 97 2 ) - 72-2 7 2 3 5 1 1
www.kayainstruments.com

Komodo CXP Reference Guide
1
Figures and Tables..............................................................................................................3
Introduction.........................................................................................................................5
Safety Precautions.................................................................................................5
Disclaimer .............................................................................................................6
Key Features .......................................................................................................................7
3.1 Overview...............................................................................................................7
3.2 Features.................................................................................................................7
3.3 Product Applications.............................................................................................8
Related documents and accessories.......................................................................8
3.5 Ordering Codes……………………..........................………………….…….......9
Board Components..............................................................................................................10
4.1 Board component Blocks......................................................................................10
4.2 Board Block diagram ............................................................................................11
4.3 External View of the Board...................................................................................11
4.4 Komodo CXP Board components.........................................................................12
4.5 Featured device: Arria V GZ FPGA......................................................................12
4.6 FPGA Configuration.............................................................................................12
4.6.1 FPGA configuration via JTAG.............................................................13
4.6.2 FPGA configuration via on board flash memory..................................13
4.7 Clocking................................................................................................................14
4.8 I/O and Transceivers .............................................................................................15
4.8.1 General purpose I\O..............................................................................16
4.8.2 General purpose LEDs..........................................................................19
4.9 PCI Express (Gen 3.0)...........................................................................................20
4.10 Memory.................................................................................................................21
4.10.1 On-Board 16Gb DDR3.........................................................................23
4.10.2 Optional SODIMM (up to 128Gb)........................................................27
4.11 CoaXPress interface..............................................................................................30
4.12 Fan Control (J6) ....................................................................................................35
4.13 Authentication device (U55).................................................................................35
Mechanical Specifications ..................................................................................................36
5.1 Mechanical dimensions.........................................................................................36
Contents

Komodo CXP Reference Guide
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5.2 Absolute maximum ratings ...................................................................................36
Electrical Characteristics.....................................................................................................37
6.1 Power Supply........................................................................................................37
6.2 Maximum and minimum input voltages ...............................................................37
6.3 Power rails.............................................................................................................37
6.4 Electrical characteristics for board IO’s:...............................................................38
6.5 Absolute maximum ratings for GPIO ...................................................................40
Available Configurations....................................................................................................41
Available Configurations ......................................................................................41
Top Level Example Design.................................................................................................42
Reference Design ...............................................................................................................43
9.1 Functional block diagram......................................................................................43
9.1.1 DDR3 memories ...................................................................................44
9.1.2 PCI Express...........................................................................................44
9.1.3 CoaxPress receiver................................................................................44
9.2 Using the reference design....................................................................................45
9.3 Board Diagnostic...................................................................................................46
Revision History
Version
Date
Notes
1.0
30/07/15
Initial Release
1.1
15/02/15
Added reference design and top level
1.2
30/07/18
Minor corrections
Contents

Komodo CXP Reference Guide
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Figures
FIGURE 1:BOARD BLOCK DIAGRAM................................................................................................................ 11
FIGURE 2: KOMODO CXP FRONT VIEW ........................................................................................................... 11
FIGURE 3: JTAG CONNECTOR.......................................................................................................................... 13
FIGURE 4: FLASH CONNECTOR....................................................................................................................... 13
FIGURE 5: CLOCKS PIN ASSIGNMENTS,SIGNAL NAME AND FUNCTIONS.......................................................... 14
FIGURE 6: I/O AND TRANSCEIVER USAGE........................................................................................................ 15
FIGURE 7: GENERAL PURPOSE INPUTS AND OUTPUTS ..................................................................................... 16
FIGURE 8: GENERAL PURPOSE LED’S LOCATION............................................................................................ 19
FIGURE 9: RZQ CONNECTION WHEN ONLY THE ON-BOARD MEMORY IS USED................................................ 22
FIGURE 10: RZQ CONNECTION WHEN ONLY THE SODIMM MEMORY IS USED............................................... 22
FIGURE 11: RZQ CONNECTION WHEN BOTH MEMORIES ARE USED ................................................................. 23
FIGURE 12: ON-BOARD DDR3 SIGNAL CONNECTIONS .................................................................................... 24
FIGURE 13: RX CHANNEL CONNECTION TO THE EQUALIZER ........................................................................... 33
FIGURE 14: TX CHANNEL CONNECTION TO THE DRIVER.................................................................................. 33
FIGURE 15: DEDICATED COAXPRESS LED’S LOCATIONS............................................................................... 34
FIGURE 16: FAN CONNECTIONS....................................................................................................................... 35
FIGURE 17: PCB MECHANICAL DIMENSIONS.................................................................................................. 36
FIGURE 18: FUNCTION DIAGRAM..................................................................................................................... 43
FIGURE 19: DDR3 SODIMM .......................................................................................................................... 46
FIGURE 20: KOMODO CXP WITH JTAG CONNECTION................................................................................. 47
Tables
TABLE 1: KOMODO CXP BOARD COMPONENTS .............................................................................................. 12
TABLE 2: CLOCKS PIN ASSIGNMENTS,SIGNAL NAME AND FUNCTIONS........................................................... 14
TABLE 3: GENERAL PURPOSE INPUT /OUTPUT PIN ASSIGNMENTS,SIGNAL NAME AND FUNCTIONS FOR J1.... 17
TABLE 4: GENERAL PURPOSE INPUT /OUTPUT PIN ASSIGNMENTS,SIGNAL NAME AND FUNCTIONS FOR J2.... 18
TABLE 5: GENERAL PURPOSE LEDS PIN ASSIGNMENTS,SIGNAL NAME AND FUNCTIONS ............................... 19
TABLE 6: PCIE PIN ASSIGNMENTS,SIGNAL NAME AND FUNCTIONS ................................................................ 21
TABLE 7: ON BOARD SDRAM PIN ASSIGNMENTS,SIGNAL NAME AND FUNCTIONS........................................ 27
TABLE 8: SODIMM PIN ASSIGNMENTS,SIGNAL NAME AND FUNCTIONS ........................................................ 30
TABLE 9: COAXPRESS CONNECTOR PIN ASSIGNMENTS,SIGNAL NAME AND FUNCTIONS ............................... 32
TABLE 10: COAXPRESS LEDS PIN ASSIGNMENTS,SIGNAL NAME AND FUNCTIONS........................................ 34
TABLE 11: FAN PIN ASSIGNMENTS,SIGNAL NAME AND FUNCTIONS................................................................ 35
Figures and Tables

Komodo CXP Reference Guide
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TABLE 12: ABSOLUTE MAXIMUM RATINGS ..................................................................................................... 36
TABLE 13: POWER INPUT................................................................................................................................. 37
TABLE 14: MAXIMUM AND MINIMUM INPUT VOLTAGES FROM PCIE.............................................................. 37
TABLE 15: POWER RAILS ON THE KOMODO CXP BOARD................................................................................ 38
TABLE 16: LVDS OUTPUT DC SPECIFICATIONS (DRIVER OUTPUTS)............................................................. 38
TABLE 17: LVDS INPUT DC SPECIFICATIONS (RECEIVER INPUTS)................................................................. 39
TABLE 18: LVTTL INPUT SPECIFICATIONS...................................................................................................... 39
TABLE 19: LVTTL OUTPUT SPECIFICATIONS .................................................................................................. 39
TABLE 20: TTL INPUT SPECIFICATIONS........................................................................................................... 39
TABLE 21: TTL OUTPUT SPECIFICATIONS........................................................................................................ 39
TABLE 22: ABSOLUTE MAXIMUM RATINGS FOR GPIO.................................................................................... 40
TABLE 23 :AVAILABLE CONFIGURATIONS ..................................................................................................... 41
TABLE 24 :LINK SETUP FOR EACH AVAILABLE CONFIGURATION.................................................................... 41
TABLE 25 :IP ADDRESS................................................................................................................................... 45
TABLE 26: LEDS DESCRIPTION........................................................................................................................ 46
Figures and Tables

Komodo CXP Reference Guide
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Safety Precautions
With your Komodo CXP in hand, please take a minute to read carefully the precautions
listed below in order to prevent unnecessary injuries to you or other personnel or cause
damage to property.
Before using the product, read these safety precautions carefully to assure correct
use.
These precautions contain serious safety instructions that must be observed.
After reading through this manual, be sure to act upon it to prevent misuse of
product.
Caution
In the event of a failure, disconnect the power supply.
If the product is used as is, a fire or electric shock may occur. Disconnect the power supply
immediately and contact our sales personnel for repair.
If an unpleasant smell or smoking occurs, disconnect the power supply.
If the product is used as is, a fire or electric shock may occur. Disconnect the power supply
immediately. After verifying that no smoking is observed, contact our sales personnel for repair.
Do not disassemble, repair or modify the product.
Otherwise, a fire or electric shock may occur due to a short circuit or heat generation. For
inspection, modification or repair, contact our sales personnel.
Do not touch a cooling fan.
As a cooling fan rotates in high speed, do not put your hand close to it. Otherwise, it may cause
injury to persons. Never touch a rotating cooling fan.
Do not place the product on unstable locations.
Otherwise, it may drop or fall, resulting in injury to persons or failure.
If the product is dropped or damaged, do not use it as is.
Otherwise, a fire or electric shock may occur.
Do not touch the product with a metallic object.
Otherwise, a fire or electric shock may occur.
Do not place the product in dusty or humid locations or where water may splash.
Otherwise, a fire or electric shock may occur.
Do not get the product wet or touch it with a wet hand.
Otherwise, the product may break down or it may cause a fire, smoking or electric shock.
Do not touch a connector on the product (gold-plated portion).
Otherwise, the surface of a connector may be contaminated with sweat or skin oil, resulting in
contact failure of a connector or it may cause a malfunction, fire or electric shock due to static
electricity.
Introduction

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Do not use or place the product in the following locations.
● Humid and dusty locations
● Airless locations such as closet or bookshelf
● Locations which receive oily smoke or steam
● Locations close to heating equipment
● Closed inside of a car where the temperature becomes high
● Static electricity replete locations
● Locations close to water or chemicals
Otherwise, a fire, electric shock, accident or deformation may occur due to a short circuit or heat
generation.
Do not place heavy things on the product.
Otherwise, the product may be damaged.
Be sure to drain static electricity from body before you touch any electronics component
The electronic circuits in your computer and the circuits on Komodo CXP board are sensitive to
static electricity and surges. Improper handling can seriously damage the circuits. In addition, do
not let your clothing come in contact with the circuit boards or components.
Otherwise, the product may be damaged.
Disclaimer
Even if the product is used properly, KAYA Instruments assumes no responsibility for any
damages caused by the following:
- Earthquake, thunder, natural disaster or fire resulting from the use beyond our
responsibility, acts caused by a third party or other accidents, the customer’s willful or
accidental misuse or use under other abnormal conditions.
- Secondary impact arising from use of this product or its unusable state (business
interruption or others).
- Use of this product against the instructions given in this manual or malfunctions due to
connection to other devices. KAYA Instruments assumes no responsibility or liability for:
- Erasure or corruption of data arising from use of this product.
- Any consequences or other abnormalities arising from use of this product, or damage of
this product not due to our responsibility or failure due to modification.
Repair of this product is carried out by replacing it on a chargeable basis, not repairing the
faulty devices. However, non-chargeable replacement is offered for initial failure if such
notification is received within two weeks after delivery of the product.
Introduction

Komodo CXP Reference Guide
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Overview
Komodo CXP is high-performance yet low-cost FPGA card supporting up to 8 CoaXPress standard
interfaces. Each link supports standard CoaXPress bitrate of up to 6.25 Gbps. The card is based on
Arria V GZ powerful FPGA that offers up to 400K flexible logic elements, 1K DSP blocks and
28Mbit of embedded memory. The board offers a flexible DDR3 memory system with up to 144 Gb
of memory and 16 GByte/s throughput. A high speed x8 lane Gen 3.0 PCI express interface allows
fast data transfers between CXP links and computer memory while a versatile GPIO with multi-
standard support enables connection to external devices. The Komodo CXP uses standard DIN
connectors as a CoaXPress interface to the camera and standard 100 mil headers for general
purpose I/O.
All of these features combine make the Komodo CXP ideal for a wide range of applications,
including network processing and security, compute and storage, instrumentation, broadcast,
defense and aerospace.
Features
8 x CoaXPress channels at 6.25 Gbps each
PCIe Gen3 x8 Half-length card
Up to 144 Gb of DDR3 memory
On-board 16Gb DDR3 64bit wide
SODDIMM of up to 128Gb DDR3 64bit wide
DDR3 1066 rate compatible
Altera Arria V GZ FPGA with:
400K equivalent LEs
1092 DSP blocks
28Mbit of embedded memory
Hard IP PCIe Gen 3.0 block
Supports Altera’s PCIe IP
Supports KAYA CoaXPress IP
Supports Memory controller IPs
Flexible machine I/O:
8 TTL configurable I/Os
8 LVCMOS configurable I/Os
Key Features

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4 LVDS inputs
4 LVDS outputs
8 opto-isolated outputs
8 opto-isolated inputs
Transfer Rate of up to 60 Gbps through PCIe
Transfer Rate of up to 50 Gbps (8 x 6.25 Gbps) through the CoaXPress interfaces
Authentication device for design security
Temperature control
Fan control
4 general purpose indication LEDs and 8 CoaXPress dedicated LEDs
0°C to 50°C operating environment temperature
Product Applications
Machine Vision
Networking
Algorithm Acceleration
Broadcasting and sports analytics
High-speed DVRs
Related documents and accessories
Documents:
Hardware User Manual
Reference design
Accessories:
CoaXPress cables (DIN to BNC)
CoaXPress cables (DIN to DIN)
GPIO extension panel
Key Features

Komodo CXP Reference Guide
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Ordering Codes
4 0 0
0-8
0 - 8
0: 16 Gb
1: 48 Gb
2: 80 Gb
3: 144Gb
KY-FGK-
Notes:
1. Maximum of Receiver and Transmitter channels together is 8
2. Custom models available on request
Key Features

Komodo CXP Reference Guide
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Board component Blocks
One Arria V GZ 5AGZME5HF35C4 FPGA in an 1152-pin BGA (FBGA)
400K LEs
1092 DSP blocks
28 Mbit on-die block memory
3276 9x9 multipliers
2184 18x18 multipliers
1092 27x27 multipliers
546 36x36 multipliers
534 general purpose input/output
FPGA configuration circuitry
JTAG header
EPCQ256 programmable flash memory
Clocking circuitry
125-MHz LVDS oscillator for transceiver reference clock
100-MHz reference clock from the PCIe edge connector
25-MHz single-ended oscillator for DDR3 memory
Memory
16Gb DDR3, 64 bit data width
up to 128Gb DDR3, 64 bit data width SODIMM (optional)
General user I/O
Four user LEDs
GPIO headers with up to 40 possible I\O connections
CoaXPress interface
Up to 8 DIN connector for CoaXPress interface
Up to 8 CoaXPress interface LED (dual-color)
Power supply
PCI Express edge connector power
External power connector for PoCXP
Board Components

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Board Block diagram
GPIO
PCIe 3.0
×8
(up to 64 Gbps)
Bank A
DDR3 ×64
16 Gb
Bank B
SODIMM DDR3 ×64
up to 128 Gb
Oscillators
JTAG
EPCQ Flash
FAN
4 green user
LEDs
DIN connector 1
DIN connector 8
8 dual color
LEDs
Equalizer/Driver
1
Equalizer/Driver
8
Figure 1: Board block diagram
External View of the Board
Up to 128Gb
SODIMM
Connector
(J11)
User LEDs
(D1-D4)
16 Gb SDRAM
(U14,U18,U22,U26)
Power
Connector (J5)
GPIO
(J2)
125MHz
Oscillator
(U2) JTAG
(J3)
EPCQ
Connector
(J4)
CoaXPress LEDs
(D1-D8) 25MHz
Oscillator
(U29)
25MHz
Oscillator
(U33)
PCle edge
Connector
(J17)
Arria V GZ
Altera FPGA
(P1)
GPIO
(J1)
CoaXPress
DIN Connectors
Figure 2: Komodo CXP front view
Board Components

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Komodo CXP Board components
Board reference
Type
Description
FPGA
P1
FPGA
Arria V GZ 5AGZME5HF35, 1152-pin FBGA
Configuration, Status and setup elements
J3
JTAG header
Provide access to the JTAG chain
J4
EPCQ programming
header
Provide access to the EPCQ using Active Serial
protocol
D1 –D8
CoaXPress LEDs
Located on a daughter board above the DIN
connectors, dedicated LEDs for showing
CoaXPress status of each CoaXPress link
Clocking Circuitry
U2
125 MHz oscillator
125 MHz oscillator for transceiver reference clock
J17
100 MHz reference clock
100 MHz reference clock from the PCIe edge
connector
U29 , U33
25 MHz oscillator
25 MHz oscillators for DDR3 memory
Memory devices
U14,U18,U22,U26
DDR3 x64 memory
16Gb DDR3 SDRAM with 64 bit data bus. The
64 bit data bus consists of 4 x16 devices with
single address or command bus
J11
DDR3 x64 SODIMM
memory
Up to 128Gb DDR3 SODIMM with 64 bit data
bus.
General User Input\Output
D1 –D4
User LEDs
Four user LEDs. Active low.
Communication Ports
J17
PCIe edge connector
Gold-plated edge fingers connector for up to x8
signaling in Gen 2 or Gen 3
J1 , J2
GPIO
General purpose input\output connector
Power supply
J17
PCIe edge connector
Interface to a PCIe root port such as an
appropriate PC motherboard
J5
External power supply
External power supply directly from computer
PSU using connector located on the right up side
of the board (standard PC power connector). Used
to provide PoCXP to CXP interface.
Table 1: Komodo CXP board components
Featured device: Arria V GZ FPGA
The Komodo CXP features Arria V GZ 5AGZME5HF35 device (P1) in an 1152-pin FBGA
package. For more information about Arria V device family refer to the Arria V device Handbook.
FPGA Configuration
The Komodo CXP FPGA can be configured using the JTAG header (J3) or by using the on board
EPCQ256 Flash that can be programmed using flash programing header (J4) with Active Serial
protocol.
Board Components

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4.6.1 FPGA configuration via JTAG
The JTAG programming header provides a method for configuring the FPGA using an external
USB-Blaster device with the Quartus II Programmer running on a PC. The external USB-Blaster
connects to the board through standard Altera JTAG header (J3).
Figure 3: JTAG connector
4.6.2 FPGA configuration via on board flash memory
The Komodo CXP has an on board EPCQ256 flash memory. Upon the power up, the FPGA tries to
fetch the configuration from that flash. The EPCQ256 flash can be programmed using an external
USB-Blaster device with the Quartus II Programmer running on a PC in Active Serial mode. The
external USB-Blaster connects to the board through the flash programming header (J4).
Figure 4: FLASH connector
Board Components

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Clocking
The Komodo CXP has a variety of on board oscillators, as described in the table and figure below:
cxp_clkp/n
7A 7B 7C 7D 8E 8D 8C 8B 8A
4A 4B 4C 4E 3E 3C 3B 3A
B2L
B0L
B1L
B2R
B0R
B1R
25 MHz
Oscillator
clk25[1]
7E
3D4D
25 MHz
Oscillator
clk25[0]
125 MHz
Oscillator
100 MHz
From PCIe edge
connector
pcie_refclk_p/n
Figure 5: Clocks pin assignments, signal name and functions
Board
reference
Signal Name
Arria V
GZ Pin
Number
Arria V
GZ Clock
Name
I/O
Standard
Description
U2
cxp_clkp
W6
REFCLK0Rp
LVDS
125 MHz oscillator for
transceiver reference clock
cxp_clkn
W5
REFCLK0Rn
U29
clk25[0]
AE16
CLK7p
SSTL-135
25 MHz oscillators for DDR3
memory
U33
clk25[1]
J19
CLK19p
J17
pcie_refclk_p
U28
REFCLK1Lp
HCSL
100 MHz clock coming from
the PCI express edge connector
pcie_refclk_n
U29
REFCLK1Ln
Table 2: Clocks pin assignments, signal name and functions
Board Components

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I/O and Transceivers
The Komodo CXP utilizes several I/O banks out of the possible 26 I\O or transceiver banks
available on the Arria V GZ FPGA. The following figure describes what each bank is used for:
7A 7B 7C 7D 7E 8E 8D 8C 8B 8A
4A 4B 4C 4E 4D 3D 3E 3C 3B 3A
B2R
B0R
B1R
B2L
B0L
B1L
CoaXPress
transceirers
PCIe_Tx
PCIe_Rx
DDR3 SDRAM + GPIO + PCIe control + CoaXPress (low speed)
DDR3 SODIMM
Rx
Tx
CoaXPress
transceirers
Rx
Tx
(0 – 3)
(4 – 7)
Figure 6: I/O and transceiver usage
Board Components

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4.8.1 General purpose I\O
The Komodo CXP supports 40 different I\O connections (on the FPGA), as described in the figure
and table below:
Figure 7: General purpose Inputs and outputs
Board Components

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Board
reference (J1)
Signal Name
Arria V
GZ Pin
Number
I/O Standard
Description
1
rout[0]
AH26
3.3-V LVTTL
Pin 1 of this header is the positive
signal and pin 2 in the negative
signal of this LVDS. The
differential pair is converted to a
single input on the FPGA
2
3
rout[1]
AK28
3.3-V LVTTL
Pin 3 of this header is the positive
signal and pin 4 in the negative
signal of this LVDS. The
differential pair is converted to a
single input on the FPGA
4
5
din[0]
AK27
3.3-V LVTTL
Pin 5 of this header is the positive
signal and pin 6 in the negative
signal of this LVDS. The
differential pair is converted to a
single output on the FPGA
6
7
din[1]
AM26
3.3-V LVTTL
Pin 7 of this header is the positive
signal and pin 8 in the negative
signal of this LVDS. The
differential pair is converted to a
single output on the FPGA
8
9
io_out[0]
AF26
3.3-V LVTTL
Optically isolated outputs
10
io_out[1]
AE26
3.3-V LVTTL
Optically isolated outputs
11
io_out[2]
AD26
3.3-V LVTTL
Optically isolated outputs
12
io_out[3]
AC26
3.3-V LVTTL
Optically isolated outputs
13
io_in[0]
Y24
3.3-V LVTTL
Optically isolated inputs
14
io_in[1]
U25
3.3-V LVTTL
Optically isolated inputs
15
io_in[2]
U26
3.3-V LVTTL
Optically isolated inputs
16
io_in[3]
Y25
3.3-V LVTTL
Optically isolated inputs
17
OptoCoupled
GND
-
-
Ground signal for opto-isolated
signals on this connector
18
GND
-
-
Reference ground signal - Board
GND
19
gpio_vt[0]
AM11
TTL
General Purpose IO
20
gpio_vt[1]
AL11
TTL
21
gpio_vt[2]
AM10
TTL
22
gpio_vt[3]
AL10
TTL
23
gpio[0]
AA30
3.3-V LVTTL
24
gpio[1]
AE28
3.3-V LVTTL
25
gpio[2]
AD28
3.3-V LVTTL
26
gpio[3]
AB27
3.3-V LVTTL
Table 3: General purpose Input / output pin assignments, signal name and functions for J1
Board Components

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Board
reference (J2)
Signal Name
Arria V
GZ Pin
Number
I/O Standard
Description
1
rout[2]
AJ27
3.3-V LVTTL
Pin 1 of this header is the positive
signal and pin 2 in the negative
signal of this LVDS. The
differential pair is converted to a
single input on the FPGA
2
3
rout[3]
AK26
3.3-V LVTTL
Pin 3 of this header is the positive
signal and pin 4 in the negative
signal of this LVDS. The
differential pair is converted to a
single input on the FPGA
4
5
din[2]
AL26
3.3-V LVTTL
Pin 5 of this header is the positive
signal and pin 6 in the negative
signal of this LVDS. The
differential pair is converted to a
single output on the FPGA
6
7
din[3]
AM25
3.3-V LVTTL
Pin 7 of this header is the positive
signal and pin 8 in the negative
signal of this LVDS. The
differential pair is converted to a
single output on the FPGA
8
9
io_out[4]
AF25
3.3-V LVTTL
Optically isolated outputs
10
io_out[5]
AE25
3.3-V LVTTL
Optically isolated outputs
11
io_out[6
AH25
3.3-V LVTTL
Optically isolated outputs
12
io_out[7]
AG25
3.3-V LVTTL
Optically isolated outputs
13
io_in[4]
W25
3.3-V LVTTL
Optically isolated inputs
14
io_in[5]
V25
3.3-V LVTTL
Optically isolated inputs
15
io_in[6]
AA27
3.3-V LVTTL
Optically isolated inputs
16
io_in[7]
Y26
3.3-V LVTTL
Optically isolated inputs
17
OptoCoupled
GND
-
-
Ground signal for opto-isolated
signals on this connector
18
GND
-
-
Reference ground signal - Board
GND
19
gpio_vt[4]
AP9
TTL
General Purpose IO
20
gpio_vt[5]
AN9
TTL
21
gpio_vt[6]
AP10
TTL
22
gpio_vt[7]
AN10
TTL
23
gpio[4]
AA28
3.3-V LVTTL
24
gpio[5]
AH27
3.3-V LVTTL
25
gpio[6]
AG27
3.3-V LVTTL
26
gpio[7]
AJ26
3.3-V LVTTL
Table 4: General purpose Input / output pin assignments, signal name and functions for J2
Board Components

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The “diff_en[0]” signal coming from the FPGA (pin AL25), enables (when set to logic 1) data
transfer from pins 1 - 4 on the GPIO header, to pins AH26 and AK28 on the FPGA. This signal also
enables data transfer from pins AK27 and AM26 on the FPGA to pins 5 –8 on the GPIO header.
The “diff_en[1]” signal coming from the FPGA (pin AP32), enables (when set to logic 1) data
transfer from pins 1 - 4 on the GPIO header, to pins AJ27 and AK26 on the FPGA. This signal also
enables data transfer from pins AL26 and AM25 on the FPGA to pins 5 –8 on the GPIO header.
4.8.2 General purpose LEDs
On the Komodo CXP there are four user-define LEDs, all are green light and active low.
Board
reference
Signal
Name
Arria V GZ
Pin Number
I/O Standard
Description
D1
led[0]
AC32
3.3 V LVTTL
User-defined LEDs. Driving logic
0 on the I\O port turns the LED on;
driving high-z on the I\O turns the
LED off
D2
led[1]
AF29
3.3 V LVTTL
D3
led[2]
AG30
3.3 V LVTTL
D4
led[3]
AB29
3.3 V LVTTL
Table 5: General purpose LEDs pin assignments, signal name and functions
LED 0
(D1)
LED 1
(D2)
LED 2
(D3)
LED 3
(D4)
Figure 8: General purpose LED’s location
Board Components