Kenwood TR-7625 User manual

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INTRODUCTION/CONTENTS
INTRODUCTION
Your
KENWOOD
Model
TR-7625
is
an
advanced
2-meter
transceiver
for
amateur
mobile,
and
optional
fixed
station
operation.
The
TR-7625
features:
x
Memory
channel
(simplex
and
repeater
mode).
ve
Memory
TX
and
+600
kHz
repeater
TX
for
repeater
operation.
sx
800
channe}!
PLL
circuit.
¢
Digital
frequency
display.
vv
Dual
concentric
frequency
selector
switches.
sx
PLL
UNLOCK
and
ON
AIR
indicators.
ve
Subaudible
ON/OFF
switch
(Encoder
user
installed).
vv
Powered
tone
pad
connector
with
9V
DC
on
one
pin.
xy
Pin
Mic
connector
with
9V
DC
on
one
pin.
sx
TX
HI-LOW
(Power)
switch.
x
Having
25W
RF
output
power.
CONTENTS
GENERAL/CIRCUIT
DESCRIPTION
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PC
BOARD
VIEWS
TXERX
Unit
(X44-13
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Unit
(XB2-1
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1
Control
Unit
(X54-1440-10),
Indicator,
Switch
PC
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12
PARTS
LIST
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Control
Unit
(X54-1440-1O)
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Unit
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BRACKET
INSTALLATION,
EXPLODED
VIEWS
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Tast
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21
PC
BOARD
ALIGNMENT
AND
TEST
POINT
LOCATIONS
PLE
Unit
(XB0-1580-4
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TR-7625
GENERAL/CIRCUIT
DESCRIPTION
GENERAL
The
TR-7625
is
a
25W.
multi-channel
(800
channels)
FM
transceiver
covering
144~
147.995
MHz.
It
features
a
built-in
repeater
shift
circuit
and
memory
circuit,
and
provision
for
connection
of
an
optional
(micro-processor)
remote
control.
PLL CIRCUIT BLOCK DIAGRAM
OUTPUT
vcT
IF
TA TOGOP,
28C460
PLL CIRCUIT
The
TR-7625
employs
a
PLL
circuit
using
SM5111A
IC
for
programmable
counter,
reference
oscillator,
frequency
divider
and
phase
detector.
Frequency
division
ratio.
memory
and
remote
indication
functions
are
all
controlled
by
BCD
codes.
Qs
PLL OUL
SM SIIIA
10 ae ty
$C1815 ORO
*
—_ x] a
x
5
m
© 5 S
?
eo
? <
‘o
A A
OS
Fig. 1 PLL Circuit

TR-7625
CIRCUIT DESCRIPTION
1. Phase Locked Loop
The
130
MHz
signal
from
Q27
passes
through
the
buffer
circuit
Q28
and
is
then
divided
into
a
synthesizer
output
by
Q11
and
a
loop
output
by
Q12
respectively.
The
output
from
Q12
is
mixed
with
the
local
oscillator
output,
tripled
by
Q6,
D21
and
Q20
to
obtain
IF
frequency.
The
IF
output
is
amplified
by
Q19
and
is
fed
to
Q15
where
the
output
is
frequency
divided
as
specified
by
the
BCD
code
and
compared
with
the
10
kHz
reference
frequency
(1/1024
of
10,240
MHz)
The
DC
output
thus
obtained
passes
through
the
low-pass
filter
to
control
the
VCO
vari-cap
diode
182208
D26.
The
output
from
Q26
controls
the
transmit
frequency
bandwidth.
When
the
signal
is
un-
locked,
output
is
shut
off
by
Q17
and
indicated
by
Q18.
Q16
shuts
off
output
when
the
rotary
switch
is
between
channel
setting
positions.
Rx Tx Freq. | Simplex Output Osc Xtal Freq. IF Freq.
144.00 MHz 133.3 MHz 43.7667 MHz 2 MHz
134.3 MHz 3 MHz
43.7667 MHz
145.00 MHz
145.99 MHz} 135.29 MHz 399 43.7667 MHz 3.99 MHz
135.3 MHz 200 44.4333 MHz 2 MHz
146.00 MHz
44.4333 MHz 3 MHz
147.00 MHz 136.3 MHz
137.29 MHz 44.4333 MHz 3.99 MHz
147.99 MHz
Table 1 Division and Frequency
2. +5 kHz Circuit
In the PLL circuit, the reference frequency is controlled
in
10
kHz
steps.
The
+5
kHz
signal
is
controlled
by
varying
the
local
oscillator
crystal
frequency
vari-cap
diode, so the frequency division remains unchanged
even when the +5 kHz circuit is operated.
The memory circuit also includes the same bit and func-
tions even when the +5 kHz circuit is operating.
3. Shift Circuit
Transmit frequencies can be shifted by changing the
local
oscillator
crystal
frequency,
as
shown
below.
144 and 145 MHz bands:
[—]
shift
43.5667
MHz
(S]
43.7667
MHz
The [+] shift is not available for 144 and 145 MHz
bands,
[S]
occurs
at
the
[+]
position.
146 and 147 MHz Bands:
[—] shift 44.2333 MHz
[+] shift 44.6333 MHz
(s] 44,4333 MHz
4. Memory Shift Circuit
The memory shift (M) is a circuit to shift to the memory
frequency during transmission.
CONTROL UNIT
Frequency settings are accomplished by the MHz, 100 kHz
and 10 kHz rotary switches. The relationship between the
frequency and frequency division is shown below.
Frequency Frequency division
144,000 MHz 200
145.000 MHz 300
145.990 MHz 399
146.000 MHz 200
147.000 MHz 300
147.990 MHz 399
The local oscillator kHz order frequency can be (switch)
shifted. Frequency division, set by the rotary switch, is stored
in the latch IC’s 1, 2 and 3 by pressing the memory input
switch. The output from the latch circuit is fed through .IC’s
4,5 and 6 in the selector circuit to the PLL circuit by pressing
the memory call switch. When this switch is not pressed, the
output is fed directly to the PLL circuit. Memory function Is
effected by latching each switch: The information from each
switch is stored by pressing the memory switch.
The stored information remains the same unless the memory
switch is pressed once again. Selection of memory output
and rotary output is accomplished by the selector circuit. A
latched output is obtained by pressing the memory output
switch.
The signal to the PLL circuit passes through the LED driver
circuit and is digitally indicated by LED.
baton
164035 BP x3
MEMORY
swiTCH
SELECTOR
Te 4019 OF
SYNTHESIZE BCO CORD OUTPUT
O MEMORY OUTPUT
Fig. 2 Block Diagram of Frequency Memory Circuit
© ROTARY Switch ovrpur *

TR-7625
CIRCUIT
DESCRIPTION
TRANSMITTER
UNIT
The
microphone
signal
passes
through
the
limiter
amplifier
and
FM
modulates
the
10.7
MHz
oscillator.
This
is
mixed
with
the
loca!
oscillator
signal
to
obtain
114
~
146
MHz
sig-
nal.
The
(variable)
B.P.F.
provides
excellent
power
and
spu-
LT +8
rious
characteristics
by
the
use
of
VCO
voltage.
The
RF
power
stage
uses
an
M57712H
power
module
manufac-
tured
by
the
Mitsubishi
Electric
Co..
providing
high
reliability.
RI5
1S 2208
O TO RF AMP
FROM VCT
Fig. 3 Variable Transmitter Band Pass Filter Circuit
RECEIVER UNIT
The
signal
from
the
transmit/receive
matching
circuit
passes
through
the
diode
switch
and
is
fed
to
the
2-stage
antenna
tuning
circuit,
3-stage
herical
tuning
circuit
and
(MOS
FET}
RF
amplifier.
This
signal
is
further
fed
to
the
mixer
MOS
FET
where
it
ig
converted
to
a
10.7
MHz
signal.
The
signal
thus
converted
passes
through
the
2-stage
filter
and
is
fed
to
the
2nd
mixer
where
it
is
converted
to
a
455
kHz
signal.
The 2nd
iF
signal
from
the
455
kHz
ceramic
filter
passes
through
the
limiter
circuit
where
it
is
converted
to
an
AF
signal
by
the
ceramic
discriminator.
This
signal
is
amplified
by
the
audio
power
amplifier
to
drive
the
speaker.
The
receiver
unit
includes
a
noise
amplification
type
squelch
circuit.
This
circuit
picks
up
the
noise
component
in
the
squelch
signal
from
the
discriminator
which
is
amplified
and
rectified
to
contro!
the
1st
stage
AF
amplifier.
The
characteristic
of
the
discriminator
is
opposite
that
of
conventional
ones
to
permit
connection
of
a
remote
control.
DC+
DC -
Fig. 4 Discriminator Characteristics

TR-7625
SPECIAL SEMICONDUCTOR DATA
CAUTION
SM5111A
Electrostatic Breakdown Protection
This
item
contains
built-in
input
protection
circuit
to
prevent
a
gate
breakdown
due
to
normal
ambient
static
presence
to
protect
the
input
circuit
from
damage
due
to
high
static
or,
voltage
(in
excess
of
permissible
circuit
limit),
the
following
points
must
be
observed:
1.
When
the
product
is
not
in
use,
keep
all
terminals
in
contact
with
insulating
material
(this
is
done
at
the
factory
prior
to
shipment).
2. Soldering iron, testing instruments and other tools
should be grounded while in use.
3. Do not insert or remove IC from the socket without tur-
ning off the power.
4. Do not apply signal voltage to the input terminal when
power is OFF.
5. Do not apply a voltage exceeding the power voltage to
the input terminal.
OPERATING SYSTEM
This
product
has
been
developed
with
C
MOS
LSI
used
for
PLL
circuit.
As
shown
in
the
block
diagram
in
Fig.
1,
it
consists
of
OSC:
reference
oscillator
circuit,
DIVIDER:
reference
fre-
quency
dividing
circuit,
PC:
programmable
counter, PD:
phase
comparator,
and
INV:
inverter.
A
high
accuracy
feed-
back
type
crystal
oscillator
circuit
can
be
formed
by
adding
a
crystal
oscillating
element.
resistor
and
capacitor
between
the
Qin
and
Qout
terminals
of
the
reference
oscillator
circuit.
This
also
permits
an
external
signal
to
be
fed
to
the
Qin
terminal.
The
oscillator
output
is
applied
to
the
reference
frequency
dividing
circuit
where
it
is
divided
into
the
desired
frequen-
cies
of
fr1
(1/2048)
and
fr2
(1/1024)
which
are
the
reference
signals
for
the
digital
phase
comparator
in
the
next
stage.
The
comparison
signal
(frequency
f1)
fed
to
the
input
ter-
minal
FIN
of
the
AMP
is
amplified
and
wave
shaped,
then
fed
to
the
input
of
the
programmable
counter.
The
frequency
“{1"
is
frequency
converted
(fpc)
through
the
program
ter-
minals
PO1
...
P33
(for
example,
when
PQ1
...
P33
=
1,
the
programmable
counter
output
is
1/999),
and
is
fed
to
the
phase
comparator
where
it
is
compared
with
the
reference
signal
in
phase
so
that
a
pulse
signal,
shown
below,
proportional
to
the
phase
difference
between
the
two
signal
is
fed
to
the
output
terminal
DO.
fpc Pt LY
Do _Lu Hing eee eer Bak ee ee DR qor-
uJ
Fig. 5
The table below shows the maximum operation limit and en-
vironmental conditions. If any of these values exceeds the
given limits, it can be cause of damage to the product or
deterioration of quality.
Item Symbol
Power Supply Voltage Vop -Vss
Input Voltage
Operating Temperature TA —30~ +70
Storage Temperature
TsTG —40 ~ +125
Power Consumption Po
Soldering Temperature
Soldering Time
Table 2 SM5111A Absolute Maximum Ratings
TOP VIEW
VDD Pio
FIN P11
QiN P12
QoutT P13
Do g P20
amPIN [6 = Pat
AMP ouT|7| = P22
FR2 P23
FR 1 P30
F12 IN P31
Lb P32
VoD P33
DATE CODE
Fig.6 SM5111A Pin Outline

3SK74
TR-7625
SPECIAL
SEMICONDUCTOR
DATA
SPECIFICATIONS
Application
VHF RF Amplifier {Mixer}
Construction
N-Channel * MOS FET (Dual Gate)
Drain + Source Voltage
Vosx 20V
Gate 1» Source Voltage
Veis +10V
Gate 2 + Source Voltage
Veos +10V
Drain Current
25 mA
Allowable Loss
200 mw
Channel Temperature
125°C
Storage Temperature
Maximum Specifications
—5.6 ~ +125°C
TEST
CONDITION
Item
Condition
Drain » Source Voltage
Vois= — 3V, Vo2s= 3V, lo= 500nA
Orain Current
Vos= 6V, Vois= 0, Vo2zs=3V
Cut-Off Voltage (Gate 1)
Vos= 6V, Va2s=0. to= 500nA
Cut-Off Voltage (Gate 2)
Vos= 6V. Ve1s=0, lo= 500nA
Gate Leak Current (Gate 1)
Vos=0, Vois=+10V, Vais=0
Gate Leak Current (Gate 2)
Vos=0. Vois=0, Vezs= + 10V
Smail Signal Transfer Admittance
Vos=6V. Vo2s= 3V, 1o=10mA, f= 1 0 kHz
Smali Signat Input Capacity
Vos= 6V. Vc2s = 3V, jlo= 10mA, f= 1.0 MHz
Small Signai Output Capacity
Vos=6V. Vozs= 3V, lo=10mA, f= 1.0 MHz
Small Signal Feedback Capacity
Vos= BV. Vaas=3V, lo= 10mA. f= 1.0 MHz
Output Power Gain
Voo= 10V, lo= 10mA, f= 200 MHz
Noise Figure
Item Symbol
Voo= 10V, lo= 10mA, f= 200 MHz
Maximum Rating of M57712H
(TA = 25°C. unless otherwise noted)
Condition
Operating
Voltage
oc
Current
Operating
Temperature
—30~ +110
Storage
—40~ +110 °C
Electrical Characteristic of M57712H
(TA = 25°C unless otherwise noted)
Condition
Output
Power
f= 144~ 148 MHz, Vec= 12V
Pin=0.15W, Z6=Zt= 500
Total
Efficiency
2nd
Harmonic
Radiation
Greater than
3rd Harmonic
Radiation
f=144~ 148 MHz, Vcc= 12V
Pin=0.15W, Zg=Zt= 500
f=144~ 148 MHz, Vec=12V
Pin=0.15W, Z6=Zi= 502
f= 144~ 148 MHz, Vcc= 12V
Pin=0.15W, Za=ZL= 500
f= 144~ 148 MHz, Vcc=12V
‘| Pin=0.15W, Z6=Z.= 502
f= 144~ 148 MHz, Vec= 12V
Pin=0.15W, Zo =ZL= 502
Impedance
Note
GATE 2
DRAIN
SOURCE
Fig. 7 3SK74 Outline
APpwn>
Input Terminal (RFI)
Power Supply of Drive Stage (DRB)
Power Supply of Output Stage (F1B)
Output Terminal (RFQ)
GND
Fig. 8 M57712H Outline

Knob
(SQU)
ey
feo
Front
Glass
S-Meter
Push
Knob
(K21-0724-04)
(B
10-061
5-04)
(B31-0616-05)
(K29-0712-04)
|
atic R ni
Knob (VOL)
(K23-0717-04)
‘Push Knob
(K29-07 13-04)
%:
ae
SS
Ri
goes
Mating Connector
(EO07-0551-05) (K)
5P Metal Socket
(EO6-0552-05) (K)
4P Metal Socket
Knob (Mode)
(K21-0731-03) (K)
oy
oc
yh
(K21-0741-03)
(W.7)
|
b(B}
Push
knob
Power
switch
03) (K29-0713-04) ($36-2402-05)
M-Type
Receptacie
Heat
Sink
(E04-0152-05)
(FO1-0731-05)
2P Connector
24P Connector
(EQ6-0252-05)
(E08-247 1-05)
vy (EO9-247 1-05)
(E11-0003-15) 4P Socket
(EC8-047 1-05) (K)
sx (EO9-047 1-05) (K)
Mating Connector Slide Switch
($31-1402-05)

TOP VIEW
TONE
Unit
RE
Pawer
Module
(X52-1110-51)
{T)
TX-RX
Unit
(X52-1110-62)
(W)
(X44-1320-10)
Low Power Adj. Protection Adj RF-Meter Adj
Control Unit
(X54-1440-10) (K)}
(X54-1440-6 1) (W), (7)
Pon
(X50- 1580-10) (K)
(X50- 1580-61) (W), (T)

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