Kenwood TR-9000 User manual

NL
KENWOOD
~ Model TR-9000
PS-20 BO-9
KENWOOD
PO ROWER BUERLY PEW RO
CONTENTS
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SPECIFICATIONS...
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CIRCUIT DESCRIPTION
RX Section
The front end unit is comprised of a dual gate MOS FET and
helical resonator. The 2-stage MCF (Monolithic Crystal
Filter) following the 1st mixer Q2 (3SK74) provides excellent
2-signal characteristic and high sensitivity.
The IF signal from the MCF is divided and applied to the SSB
and FM circuits. The SSB signal passes through the NB
(Noise Blanker) gate crystal filter (10H2.2SD) and is
amplified by the transmit/receive IF amplifier. Q27, Q28 and
29, and is then demodulated into an audio signal by the
product detector.
In the NB circuit, the signal from the MCF passes through the
buffer amplifier Q6 and is fed to the 2nd mixer Q7. This
signal is converted 455 kHz and the noise is amplified by two
stages for switching the NB gate. The NB is front panel con-
trolled.
In the AGC circuit, the signal from the final IF stage is
detected and amplified, and the time constant is automatical-
ly select according to the mode of operation, FAST in CW
mode and SLOW in SSB mode. The AGC signal is applied to
the 3-stage IF amplifier, Q27, 28 and 29 (3SK74), and the
RF amplifier Q1. The AGC voltage is also used for meter
indication.
In the FM circuit. the signal from the ceramic filter CFW-
455E is amplified by the IF amplifier Q13 (TA7302P). The
auto scan stop signal is applied to the micro-computer from
the squelch circult.
The detected AF signal is amplified by the AF amplifier Q18,
a 2SC1815(Y). The amplified signal passes through the LPF
(Low Pass Filter) Q19. a 2SC1815(Y) and is power-amplified
by Q26, (HA1366W) via the AF GAIN control to drive the
speaker.
TR-9000
Item
Rating
Nominal center frequency
455 kHz
6 dB bandwidth
+7.5 kHz or more
50 dB bandwidth
+15 kHz or less
Ripple (within 455 +5 kHz)
3 dB or Jess
Loss
6 dB or less
Guaranteed attenuation
(within 455 +100 kHz)
35 dB or more
Input and output impedance
1.5 kQ
Table 2. Ceramic filter (L72-0316-05) CFW455E
(RX Unit : CF1)
Item Rating
Nominal center frequency (fo) 10.695 MHz
Center frequency
Within fo +200 Hz at 6dB
Pass bandwidth
2.2 kHz or less at 6 dB
Attenuation bandwidth
+1.5 kHz or less at 20dB
+2.4 kHz or less at 60dB
Ripple
Less than 2 dB
Loss
Less than 5 dB
Guaranteed attenuation
60 dB or more within +40 kHz
Input and output impedance
6002 +10%/15 pF +10%
Table 3. Crystal filter (L71-0215-05) 10H2.28D
(RX Unit : XF2)
Item Rating
Nominal center frequency (fo) 10.695 MHz
Pass bandwidth
+7.5 kHz or more at 3 dB
Attenuation bandwidth
+25 kHz or less at 40 dB
+465 kHz or less at 60 dB
Guaranteed attenuation
1. 70 dB or more within +] MHz
2. Spurious level = 40 dBor more
at fo ~ fo +500 kHz
3. Spurious level = 80 dBor more
at fo — (910 kHz +10 Hz)
. iat Rating
Item Sym Condition Unit
bol | (Ta=25°C) | in | TYP [MAX
DE current with la | Vin=0 — |30.0]60.0|ma
no input
Gain in voltage Gv | Vin = —50d8 | 50.0 |52.5 | 55.0 | dB
Output power Po | THD = 10% 45) 55) —
Distortion THD | Po = 0.5W - - 15] %
Rg = 10k2,
Noise level WBN | BW=20 Hz ~ - — 2.0 | mV
20 kHz
Hum ratio HR | f = 500 Hz 28.0 | — — | dB
= 500 Hz
Voltage allowance fr _ _ _
with a shorted load Vin = 10 mV, 16.0 Vv
t= 5sec.
Rank 1 2 3
Gv (dB) 50.0 ~ 52.2 51.4 ~ 53.6 52.8 ~ 55.0
Table 1. HA1366W (RX Unit : Q26)
Ripple 1.0 dB or less
Loss 1.5 dB or less
Impedance 3 kQ/0 pF
Table 4. MCF (L71-0216-05)
(RX Unit : XF1)
TX Section
The microphone signal
is amplified by the
microphone amplifier Q1, a 2S5C2240 (GR).
{S B/FM
Thisjs then
divided and fed to the SSB and FM circuits. SS} signal
passes through the MIC GAIN control and is fed tct he RX

TR-9000
CIRCUIT DESCRIPTION
unit where the signal is amplified by two stages and ts then
applied to the balanced modulator together with the carrier Item Symbol | Te (°C) Rating
signal (10.695 MHz). The DSB (Double Side Band) signal Operating voltage Vee 25 17V
from the buffer amplifier Q37, a 2SK61 (GR) is fed to the
: . . , : DC current lec 25 6A
transmit/receive crystal filter to produce an SSB signal. This
signal is amplified and applied to the transmit balanced mix- Operating case temperature | Tc (op) = 730 ~ + 110°C
er, O5 and Q6, 2SK61 (GR), in the TX unit. The FM signal is Storage temperature Tstg = —40 ~+110°C
limiter-amplified by Q2 (TA7O61AP) and is directly Base bias voltage Veep 25 10V
modulated by a 182208 diode. The modulated signal is
applied to the mixer through the oscillator circuit Q3 (10,695
MHz) and buffer amplifier Q4 a 2SC460 (B). The remaining
circuits are common to all the operating modes. The 4-stage
BPF (Band Pass Filter) next to the mixer ts used to eliminate
unwanted spurious signals. After filtering, the signal is
amplified by Q7, a 3SK74 (L) to drive the final unit via Q8
(2SC2538).
In the ALC circuit, the drive output from O8 is amplified by
Q9, a 2SC2603 (E) and is applied to the 2nd gates of the
predriver Q7 and IF amplifier Q27.
The HI/LOW selection and protection in the FM and CW
modes is accomplished by changing the source voltage of
Q7, the predriver. In CW mode, the keying circuit controls
the transmit balanced mixer B+ line and the base circuit of
Table 5. Power module (V30-1 131-06) M57713
MAX Rating (Final Unit : Q5)
the predriver Q8 by the switching action of Q10, a 2SC1015 1: INPUT 4: Veep
(Y). This signal, fed to the final unit. is power-amplified by 2: Vee 5: OUT
the power module (M57713). and is then output to the 3: BASE BIAS 6: GND
antenna through. the LPF (Low Pass Filter). The M57713 is
designed to provide excellent power, idle current, IMD and
f characteristics, thus insuring stabilized performance. Fig. 1 Power module (V30-1131-06) Equivalent Circuit
PLL Unit (X50-1620-11} VCO FREO
PF | MODE FREQ (MHz)
sw 133.305
FMt
Ton ~ 135.285
2SC1775 133.305
Yel FM2
~ 135.3049
mL USB | 133.3065
Ler F CONT RXUILR) cw | ~435.3064
133.
og Qs ot Lsp 3085
. 22240 28C2240} ef 1SV50S ~ 135.3034
(GR) (GR)
HET OSC FREQ fHO
seer MOOE | FREQ (MHz)
FMi | 14.20
L—__ tcsost 055
5.5
749MHz
em
|
'4:20058
DIVID I P.C BUFF AMP BUFF LPF. MIX ~14.20165
10.24MH2
|
Q17
|
a8
aio
Qu
12
usB
|
14.20072
RO —#| TC5082 TC9122 2sc46o0 28¢460 28C460 \ cw | ~14.20182
FROM p-cL | tOKH2 1OKHr} —p (8) (8) 1B) 14.20038
RX UNIT LSB .
N+
550.749
~14.20149
DC BUFF F. CONT - F. CONT osc PLL HET FREQ fH
Q7 06 DS 06 D4 MODE | FREQ (MHz)
2SK30A 1$2208 HOH 4SV50S 2SC460 1SS16
(GR)
iB}
FM1
|
427.805
Fo 427.805
FM2
~ 127.8149
~~ USB | 127.8065
— ~ 127.8164
10K ~IMHz DATE 0 ~9.9KH2 DATE gor cw 127-816
Lerom conTRot unit tga | 1278039
~ 127.8134
Fig.2 PLL Unit Block Diagram

TR-9000
CIRCUIT DESCRIPTION
PLL Unit (X50-1620-11)
Fig. 2 shows a basic block diagram of PLL circuit. The signal
from the VCO (Q1, a 2SK19 (GR)) passes through the buffer
amplifier formed by Q2, a 2SC1923 (O) and O5, a 3SK74
(L), and is then mixed with the HET (Heterodyne) signal by
Q13, a 2SC1923 (O) to produce 5.5 ~ 7.49 MHz signal.
This signal is amplified by Q10, 11 and Q12, 2SC460 (B)
and is frequency-divided by Q18 (TC9122P) according to the
BCD data (MHz, 100 kHz and 10 kHz order) from the control
unit, to produce 10 kHz comparison signa!. Simultaneously,
the 10.24 MHz signal from the RX unit is frequency-divided
to 1/1024 by Q17 (TC5O082P-GL) to produce 10 kHz
reference signal. These signals are phase-compared by Q16
(TC5081P) and fed to the LPF formed by Q8 and QQ, and the
resulting control voltage is applied to the VCO vari-cap tuning
diode.
The 14.2 MHz VCO HET signal is generated by crystal oscil-
lator 06, a 2SC460 (B), and is then multiplied 9 times by D4
(1$S16) to produce a 127.8 MHz signal. This signal is then
applied to the mixer, Q13, a 2$C1923 (O).
The crystal oscillator circuit has two vari-cap diodes to con-
trol frequency. A DC signal. corresponding to 0 ~ 9.9 kHz
produced by the control unit (X53-1160-00),. is voltage con-
verted by Q7, a 2SK30A (GR) and is fed to the vari-cap D6
(1$2208) to control the frequency. The other vari-cap D5
(1SV50S) is used to shift the frequency (fuse = frm + 1.5
kHz. fiss = fem — 1.5 kHz) according to the operating mode
and to afford RIT (Receive Incremental Tuning) frequency.
ey ee eee ee
w—!
LS
Lt
LI
|
Pout —
maser U LJ
Fig. 3 TC5081P (PLL Unit : Q16)
Phase comparator timing chart
Voo
R ——
| Pout
‘O>-D. ie Piase
am @—P>o—O Aout
Fig. 4 TC5081P (PLL Unit : Q16)
GND Pout 02 D1 C4
fel ft tel sl Gel fa fl
GND OUT
o
Vop Pin Ai A2 AZ A4 B11 B2 B3
Fig. 5 TC9122P (PLL Unit : Q18)
Symbol Name Content and operation Remarks
Pin Programmable counter Programmable counter input terminal to which the signal tobe | Build-in bias
input terminal divided ia input. circuit
counter
F counter output terminal. Output is 1/N of the
‘output terminal.
input frequency. The output pulse width aquals 5 bit of
the input.
Ai~wAe | 7 Terminal to sat the dividing ratio. The fotiowing input Built-in
&~B, | «10 Program input | combination is prohibited. pull-down
Ci~C. | x 100 terminals Ar Ay Ay Ac B, Bi By Bs Cy Cr Cs Ce Di Dj cesistor
Di~De | x 1000 1060 600 6006060 0060060 0 0
0 10 000000 00 0 0 0
1 10 00 0000060 0060 0 06
60 1000 00000 00 0
1 0 10600 0060000 000 0
o 1 1 0060 0600000060 0600 0
1 1 1 0 0 0 60 0 0 80 0 0 0 0
Table 6. Functions of TC 9122P (PLL Unit: 018)
CONTROL Unit (X53-1160-11)
Fig. 8 shows the basic configuration of contro! unit. Utilizing
the micro-computer to it’s full advantage, this control circuit
has been designed for a minimum of peripheral control cir-
cuits.
@ Indicator
The indicator is a dynamic lighting (scanning) type, using
5-digit LED's. The BCD code data available at the
micro-computer D port (pins 8-11) is converted into
7-segment data by the decoder driver Q18 (TC5)22BP),
so that transistors Q5-9, 25C1815 (Y) are switched
(scanned) in sequence by the digit signa! from theE and F
ports (pins 12-16) and light the LEDs.
e@ PLL Data Output
The PLL MHz, 100 kHz and 10 kHz order data outputs are
available directly from the BCD code at the G,H and |
ports (pins 22-32). For the 1 kHz and 100 Hz order data,
only the indicator data (1 kHz and 100 Hz orler) are
stored in the dual latch, Q16 (MN1201A) to produce the.
data for each digit.
This 2-digit data is converted to a corresponding DC
voltage by the D/A converter, a combination of solid
resistors (R6-20).
The MHz, 100 kHz and 10 kHz order data are&50 at
4.00, 650 at 5.00 and 749 at 5.99, respectively( 3-digit
BCD code).
@ Reset Circuit
The reset circuit is a voltage detecting type. Wren the
source voltage of the micro-computer is increasedasnd ex-
ceeds about 3.5V, a current flows into D20, causigg Q11,
5

TR-9000
CIRCUIT DESCRIPTION
a 2SC1815 (Y) to turn ON, which in turn sets the collector / point of clicks
of Q10, a 2SC1815 (Y) high, and a reset pulse is input to | |
the micro-computer through the CR differentiation circuit. Y Y Y Y
@ Encoder and UP/DOWN Inputs | ——
Fig. 7 shows the output signal from the encoder # (50 UP Clock signal | | | |
steps per rotation). This signal is used to discriminate UP (Clockwise __]
and DOWN counts within the micro-computer. The UP direction) UP/DOWN signal rT
count starts when U/D is H level at the down edge of the
clock signal, and the DOWN count when U/D is L level. | ’ | —
@ Tone Oscillator Circuit DOWN Clock signal | | |
When the output for the micro-computer tone oscillator is (Counter clockwise
H level, Q12, a 2SC1815 (Y) is energized, allowing a cur- direction) UP/DOWN signal
rent to flow into the piezo-electric buzzer oscillator, Q13, a — —
2SC1815 (Y), producing a tone. !
@ Switching Circuit Fig. 6
Each of the switches in the control unit are used to select Terminal
the control pulses output from the micro-computer. Fig. 8 symbols
shows a block diagram of the control unit. For actual “a —_— ? “O Vcc Vv
Operation of this unit, the micro-computer input and out: = 6 CLOCK output C
put terminals must be connected. The diodes (see circuit AMP
diagram) are used to prevent control pulses from entering Sensor I —? U/D output ———— U
the wrong circuits. + © GND G
Fig. 7 Rotary encoder (W02-0308-05)}
5
Digit
LED
4
bit
AAS
Decoder
100
Hz
Data
sof]
/
av]
.
Wd
atrver
Latch
D/A
Ae
a
a
Q18
Q16
|
Convertor
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switch
(F300)
8
8.
9.
10.
11
DC
signal
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D
.
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E
6
LT
10
kz
data
(
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4bit
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PLL
L
F
4
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100
kHz
data
4
bit
q
a
Ich
19-37
micro
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ch
19
computer
=|
|
wv
Y
Memory
2ch
19-38
Q1
ie
3
poe
“M
switch
1438
channel
3ch
19-39
+
MR
switch
14937
switch
4ch
19-40
INT
“SCAN
switch
13437
\
Sch
1937.38
_
*
HOLD
switch
13-40
M
8
+
DS
switch
15-440
>
RES
*
A/B
switch
15-39
R
+
MODE
switch
-
aS
circuit
FM1
15-37
4
1537
2
FM2
(18
34
2
33.34
35.36
Tone
Rotary
UP/DOWN!
j
j
oscillator
encoder
switch
2
circuit
(
Mic
5
8
PLL
Stop
signal
(UL)
.
DC
voltage
4
0
Transmit
signal
(9T)
for
back
up
|"
O Squelch
stop
signal
(SS)
rN
Other
circuit
DC
voltage
Q17
POWER SW
Fig. 8 Block diagram of control unit

CIRCUIT DESCRIPTION
@ Scan Circuit
This
circuit
is
active
when
the
SCAN
switch
is
depressed.
TR-9000
During
operation,
counting
and
all
other
functions
are
foRVER
|
effected
within
the
micro-computer.
The
scan
stops
by
®
vo
pressing
the
HOLD
switch
or
by
setting
the
transmit
s@®
Sj
-@>
|
|
signal
(9T)
to
H
level.
The
scan
stops
for
a
brief
period
of
2®
aep
re
=
5:
L.
le
time
when
the
squelch
stop
signal
(SS
terminal)
becomes
5®
7
Seowen
SM.
|
Py
H
level.
This
signal
is
used
to
stop
the
scan
in
10
kHz
or
DECODER
Se:
|!
a
|
>O-
S+-O«
|
|
20
kHz
step.
The
changes
in
the
10
kHz
PLL
data
each
Lo
I
4
are
differentiated
as
is
or
are
inverted
by
Q19,
20
to
ob-
.
ve
Fig.
9
TC5022BP
(Control
unit
:
Q18)
tain
OR
data
so
that
pulses
are
output
each
time
the
data
is
changed.
These
pulses
are
applied
to
the
micro-
Te
LL
Te
Sa
A
H
a * * * e
L L L L
L L
L
tr
computer
scan
stop
terminal
(4)
to
slow
down
the
scan
Hof
ee
EET
Operation.
ppeerepoutyreperlatuyu
iy
HPA
Toe
TL
.
.
L
*
H
L
L.
L
L
H H
L
L L
L
L
Contro!
Power
Circuit
L
*
L H L L
B
H
L
H H
L
H
L
.
.
. .
L
H
H L L
H H H
H
L L
H
L
The
indicator
operates
on
5V
available
at
transistor
Q14,
a
TTL
25C496
{(Y).
The
micro-computer
operates
on
6V
wpe
Pap
ee
supplied
by
the
AVR
(Automatic
Voltage
Regulator)
IC.
pope
Pe
Tet
7
Q17
(NJM78LO6K),
supplied
through
a
reverse
current
ete
pe
fe
pepe
ts
papa
Pa
|e
Pa
a
.
:
L
*
L H
L
H
H
H
8
H
Hq
H
L
L
blocking
diode,
D11.
Lpefyelape
Pa
Pe
pa
pe
fp
ae
Pe
Pp
eek
+
.
L
*
L
1.
H
H H
H L H H
L
H
L
Backup
Circuit
L
*
u
L
n
Hu
H
H
u H
L
L
H
L
When
the
POWER
SW
is
turned
OFF,
the
micro-computer
pope
fe
fe
tf
eo
Ho
Operates
from
the
backup
power
source
when
the
micro-
Table
8
Truth
table
of
TC5022BP
3.
Ledeen
computer
INT
terminal
(pin
6)
is
at
Llevel.
At
this
time.
all
(Control
unit
:
Q18)
Pin
.
(nput
|
Output
_
Pin
.
Input
|
Output
a
No.
Pin
signal
signal
Description
Pulse
No.
Pin
signal
signal
Description
Pulse
1
|
cLI1
Clock
signal
400
kHz
22
|PGO
°
A
2
|Pco
ral
Normaily
L.
H
at
23
PGI
o
B
10
kHz
order
data
prohibited
transmitting
24
PG2
fo)
c
output
for
PLL
3
|
PC1
re)
Normally
L,
H
at
Tone
ON
25
PG3
e)
D
4
|
PC2
1@)
Squeich
signal,
H
at
Busy
stop
26
PHO
oO
A
5
|
PCc3
ce)
Normally
L,
H
at
transmit
27
PH1
ie}
B
100
kHz
order
data
6
|
INT
O
Normatly
H
28
|
PH2
Oo
|c
{
ovtput
for
PLL
7
|
RES
(e)
H
at
reset
29
PH3
ie)
D
8
|
PDO
ce)
fe)
ce)
30
|
PIO
e)
A
Call
channel
input
MHz
order
data
9
|PD1
o
signal.
°
317
PH
©
BT
output
for
PLL
10.
|
PD2
°
100
Hz,
1
kHz
order
Oo
32
|
PI2
Oo
|c
data
output.
11
PD3
e)
1@)
33
PAO
1o)
Encoder
input,
clock
12
|
PEO
O
1
kHz
order
data
output.
0
34
|
PAI
O
Encoder
input,
UP/DOWN
latch
pulse
35
PA2
O
aoe
aeMc
UP
10
kHz
order
data
output
13
|
Pet
©
|
SCAN,
HOLD
output
°
Noma
4
Lat
Mic
36
|
PAS
fo)
ormally
hed
14
|
PE2
O
100
kHz
order
data
output
O
DOWN
operation
M.
MR
output
MR,
SCAN,
MODE-FM1
37
|
PBO
(e)
: ‘
uae
re)
1
MHz
order
data
output
MEMORY
1.
SCH
pulse
input
15
|
PES
°
DS,
A/B,
MODE
output
©
38
|
PBI
O
M.
MODE-FM2,
MEMORY
2
lo
100
Hz
order
data
output
pulse
input
16
|
PFO
ro)
°
Latch
pulse
39
|
pro
0
VFO-B,
MEMORY
0
17
+|
PFI
Oo
Not
used
(open)
3CH
pulse
input
18
|
PF2
oO
Not
used
(open)
40
PB3
6
SEARCH.
MEMORY.
5
19
|
PF3
fe)
CALL,
MEMORY
output
°
4CH
pulse
input
20
|
TEST
[e)
Normally
H
41
Vss
Grounded
21
|
Vcc
ie)
5V
DC
supply
42
|
CLO
Clock
signal
400
kHz
Table 7. Functions of «PD650C-021 (Control Unit: Q15) 7

TR-9000
output ports become L level, minimizing power consump-
tion. When the POWER SW is turned ON, the INT ter-
minal and UP/DOWN input terminal become H level. and
the micro-computer resumes at its original condition.
The input port B (pins 37-40} is momentarily set to L jevel
CIRCUIT DESCRIPTION
by Q2 and Q4 to insure backup operation even when a ODpi Dp2
other switches remain ON. Backup operation is also
assured during scan operation, since the scan is stopped Di D2 D3 D4 DS
by Q3 when the POWER SW is turned OFF.
Symboi Pin Description Pin No. Address Pin No. Address
INT ~ IN4 | Input 4-bit input terminal 1 D5, Dp2 Cathode 9 Je Anode
AO1 ~ AQ4 | Output Output terminal for data latched 2 D4 Cathode 10 d Anode
P
by
clock
pulse
CKA
3
D3
Cathode
1
c
Anode
i 4 D2 Cathode 12
BO1
~
B04
|
Output
by
clock
cuee
CKE
data
latched
g
Anode
5 D1, Dp1 Cathode 13 b Anode
Clock signal termina! for latching 6 Open 14 a Anode
4-bit input signal in 4-bit flip flop A.
CKA
Clock
A
Input
signal
is
latched
at
the
rising
of
7
|
Dp1,
Dp2
Anode
15
|f
Anode
clock signal. 8 Dp1, Dp2 Anode
Clock signal terminal for latching
CKB Clock B 4-bit input signal in 4-bit flip flop B.
Input signal is latched at the rising of
clock signal.
Table 9. Function of MN 1201A
(Control Unit : Q16)
a A Oo
f=]
oO
xz
b
fw]
Zz
bh
fe]
=
Oo fT
[
EE]
leo] te}
ul
=A) [eA
——Pa
bp
!
Le] La]
@Q <
2 8
neoee
L |
<
on oO
[~]
|
oa oF
|
Ls]
> ° i
oo on
[
Le]
@ 3
i]
tt
oa
Pe im
fra
a
[
Ey)
oO °
oo o™
[
b
°
Py
> 2
rl
ie?
| —
I
ra
8
Nn
Fig. 10 MN1201A (Control unit : Q16)
14 1S 1110 915126
+—-+-4 t+ 4
Fig. 11 5 digit LED D101 : SL1502

< FRONT PANEL > TR-9000 (K)
Case (upper)
TR-9000
OUTSIDE VIEWS
(AQ1-0762-13)
Knob (C)
(K21-0750-04)
Knob (D)
(K23-0729-04)
Panel
(A20-2372-05)
Knob (A)
(K23-0727-04)
Push Knob (A)
aa Fc aan.
| POWER/ VOL
(K27-0408-04)
Knob (B)
~“
\
“\ y.
(K23-0728-04)
Main knob
5-digit LED (SL-1502)
(V11-6172-26)
S meter
(B31-0625-05)
Side escutcheon
(BO7-0621-03)
Panel escutcheon
cna —(BO1-0626-02)(K)(X)
ISCRVER
on
i
(BO1-0627-02)(W)
aie | ree — Ss (BO1-0628-02)(T)
LE
as
——
Push
knob
(C)
(K29-0733-04)
Knob (E)
(K23-0733-04)
Push knob (B)
(K27-0409-04)
6P metal socket (MIC)
(E06-0651-05)
*(EO07-0651-05)
Push knob (D)
(K21-0749-03)
Case (lower)
Meta! foot
a (K27-0412-04)
4
(JO2-0416-04)
(AO1-0763- 12)
<
REAR
PANEL>
TR-9000
(K)
STBY jack
(E11-0406-05)
* (E12-0401-05)
TONE PAD Socket (K)
(E08-047 1-05)
*(E09-047 1-05)
KEY jack
(E1 1-0405-05)
* (E12-0001-05)
Power jack
(EO8-0304-05)
3P power cord
* (E30-1657-05)
2P connector
(EO8-0203-25)
DC cord ass’y
* (E30-1648-05)
Earphone jack EXT. SP
(E11-0409-05)
* (E12-0001-05)
*
Mating
connector
Heatsimk (K)
(FO10744-05)
UHF Typere ceptacle
(E04-0101-O5)
* Mating connector.

TR-9000
PC BOARD VIEWS
V
SWITCH
UNIT
(X41-1290-11)
PARTS
LIST:
Page
19
(14)
|
1
— WN
Ow
3
Q1~4:2SC1815(Y) D1 ~4, 12~15:1N60 D5~11: 181555
Vv FINAL UNIT (X45-1140-00) (W)(T)(X) PARTS LIST: Page 20
(X45-1140-11) (K)
Q1.2.4:2SC1815(Y) Q3:2SA1015(Y) Q5:M57713 D1:MI402 D2:1S2588 D3.4:1N60 D5:151555 D6U05B
< Wiring on the Heat Sink > C32
0.8¢ wire ,
<Attachment direction of L2> (others are 0.5¢) |/.4¢
2SA1015(Y)
2SC 1815(Y) =
ws
|
5
7]
——~
=
+
———
.
Attachment
method
\
Attachment
method
of
|
of
D6
and
C31
»
C32
and
L8
mene’
»
y
| Power
C31 module
Solder the leads of the power
module without applying
stress to them.
10