Lapis ML610Q111 User manual

ML610Q111/ML610Q112
User’s Manual
Issue Date: Nov. 16, 2016
FEUL610Q111-05

ML610Q111/ML610Q112 User’s Manual
FEUL610Q111 1
NOTES
1) The information contained herein is subject to change without notice.
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Copyright 2013-2016 LAPIS Semiconductor Co., Ltd.
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http://www.lapis-semi.com/en/

ML610Q111/ML610Q112 User’s Manual
FEUL610Q111 2
Preface
This manual describes the operation of the hardware of the 8-bit microcontroller ML610Q111 /
ML610Q112.
The following manuals are also available. Read them as necessary.
nX-U8/100 Core Instruction Manual
Description on the basic architecture and the each instruction of the nX-U8/100 Core.
MACU8 Assembler Package User’s Manual
Description on the method of operating the relocatable assembler, the linker, the librarian,
and the object converter and also on the specifications of the assembler language.
CCU8 User’s Manual
Description on the method of operating the compiler.
CCU8 Programming Guide
Description on the method of programming.
CCU8 Language Reference
Description on the language specifications.
DTU8 Debugger User’s Manual
Description on the method of operating the debugger DTU8.
IDEU8 User’s Manual
Description on the integrated development environment IDEU8.
uEASE User’s Manual
Description on the on-chip debug tool uEASE.
uEASE connection Manual for ML610QXXX
Description about the connection between uEASE and ML610Q111 and ML610Q112.
FWuEASE Flash Writer Host Program User’s Manual
Description on the Flash Writer host program.

ML610Q111/ML610Q112 User’s Manual
FEUL610Q111 3
Notation
Classification Notation Description
♦Numeric value xxh, xxH Indicates a hexadecimal number. x: Any value in the range of 0 to F
xxb Indicates a binary number; “b” may be omitted. x: A value 0 or 1
♦Unit word, W 1 word = 16 bits
byte, B 1 byte = 8 bits
nibble, N 1 nibble = 4 bits
maga-, M 106
kilo-, K 210 = 1024
kilo-, k 103= 1000
milli-, m 10-3
micro-, µ 10-6
nano-, n 10-9
second, s (lower case) second
♦Terminology “H” level, “1” level Indicates high voltage signal levels VIH and VOH as specified by the electrical
characteristics.
“L” level, “0” level Indicates low voltage signal levels VIL and VOL as specified by the electrical
characteristics.
♦Register description
R/W: Indicates that Read/Write attribute. “R” indicates that data can be read and “W” indicates that data can be written. “R/W”
indicates that data can be read or written.
MSB
LSB
FCON0 OUTC1 OUTC0 OSCM1 OSCM0 SYSC1 SYSC0
R/W
 
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
1
1
0
1
0
1
Bit name
Register name
Initial value after reset
Invalid bit: This bit reads “0” when read. Write to this bit is ignored.

ML610Q111/ML610Q112 User’s Manual
Contents
FEUL610Q111 Contents - 1
Contents
Chapter 1
1 Overview .....................................................................................................................................................1-1
1.1 Features..................................................................................................................................................1-1
1.2 Configuration of Functional Blocks.......................................................................................................1-4
1.2.1 Block Diagram .............................................................................................................................1-4
1.3 Pins.........................................................................................................................................................1-5
1.3.1 Pin Layout ....................................................................................................................................1-5
1.3.2 List of Pins....................................................................................................................................1-6
1.3.3 Description of Pins.......................................................................................................................1-8
1.3.4 Termination of Unused Pins.......................................................................................................1-11
Chapter 2
2 CPU and Memory Space .............................................................................................................................2-1
2.1 Overview................................................................................................................................................2-1
2.2 Program Memory Space.........................................................................................................................2-1
2.3 Data Memory Space...............................................................................................................................2-3
2.4 Instruction Length..................................................................................................................................2-5
2.5 Data Type...............................................................................................................................................2-5
2.6 Description of Registers.........................................................................................................................2-6
2.6.1 List of Registers............................................................................................................................2-6
2.6.2 Data Segment Register (DSR)......................................................................................................2-7
Chapter 3
3 Reset Function.............................................................................................................................................3-1
3.1 Overview................................................................................................................................................3-1
3.1.1 Features ........................................................................................................................................3-1
3.1.2 Configuration................................................................................................................................3-1
3.1.3 List of Pin.....................................................................................................................................3-1
3.2 Description of Registers.........................................................................................................................3-2
3.2.1 List of Registers............................................................................................................................3-2
3.2.2 Reset Status Register (RSTAT).....................................................................................................3-2
3.3 Description of Operation........................................................................................................................3-3
3.3.1 Operation of System Reset Mode.................................................................................................3-3
Chapter 4
4 MCU Control Function................................................................................................................................4-1
4.1 Overview..................................................................................................................................................4-1
4.1.1 Features ........................................................................................................................................4-1
4.1.2 Configuration................................................................................................................................4-1
4.2 Description of Registers...........................................................................................................................4-2
4.2.1 List of Registers............................................................................................................................4-2
4.2.2 Stop Code Acceptor (STPACP)....................................................................................................4-3
4.2.3 Standby Control Register (SBYCON)..........................................................................................4-4
4.2.4 Block Control Register 2 (BLKCON2)........................................................................................4-5
4.2.5 Block Control Register 4 (BLKCON4)........................................................................................4-6
4.2.6 Block Control Register 6 (BLKCON6)........................................................................................4-7
4.2.7 Block Control Register 7 (BLKCON7)........................................................................................4-9
4.3 Description of Operation .......................................................................................................................4-10
4.3.1 Program Run Mode ....................................................................................................................4-10
4.3.2 HALT Mode ...............................................................................................................................4-10
4.3.3 STOP Mode................................................................................................................................4-11
4.3.3.1 STOP Mode When CPU Operates with Low-Speed Clock............................................................4-11
4.3.3.2 STOP Mode When CPU Operates with High-Speed Clock........................................................... 4-12
4.3.3.3 Note on Return Operation from STOP/HALT Mode..................................................................... 4-13
4.3.4 Block Control Function..............................................................................................................4-14

ML610Q111/ML610Q112 User’s Manual
Contents
FEUL610Q111 Contents - 2
Chapter 5
5 Interrupts (INTs)..........................................................................................................................................5-1
5.1 Overview................................................................................................................................................5-1
5.1.1 Features ........................................................................................................................................5-1
5.2 Description of Registers.........................................................................................................................5-2
5.2.1 List of Registers............................................................................................................................5-2
5.2.2 Interrupt Enable Register 0 (IE0) .................................................................................................5-3
5.2.3 Interrupt Enable Register 1 (IE1) .................................................................................................5-4
5.2.4 Interrupt Enable Register 2 (IE2) .................................................................................................5-6
5.2.5 Interrupt Enable Register 3 (IE3) .................................................................................................5-7
5.2.6 Interrupt Enable Register 4 (IE4) .................................................................................................5-8
5.2.7 Interrupt Enable Register 5 (IE5) .................................................................................................5-9
5.2.8 Interrupt Enable Register 6 (IE6) ...............................................................................................5-10
5.2.9 Interrupt Enable Register 7 (IE7) ...............................................................................................5-11
5.2.10 Interrupt Request Register 0 (IRQ0) ..........................................................................................5-12
5.2.11 Interrupt Request Register 1 (IRQ1) ..........................................................................................5-13
5.2.12 Interrupt Request Register 2 (IRQ2) ..........................................................................................5-15
5.2.13 Interrupt Request Register 3 (IRQ3) ..........................................................................................5-16
5.2.14 Interrupt Request Register 4 (IRQ4) ..........................................................................................5-17
5.2.15 Interrupt Request Register 5 (IRQ5) ..........................................................................................5-18
5.2.16 Interrupt Request Register 6 (IRQ6) ..........................................................................................5-19
5.2.17 Interrupt Request Register 7 (IRQ7) ..........................................................................................5-21
5.3 Description of Operation......................................................................................................................5-22
5.3.1 Maskable Interrupt Processing ...................................................................................................5-23
5.3.2 Non-Maskable Interrupt Processing...........................................................................................5-23
5.3.3 Software Interrupt Processing ....................................................................................................5-23
5.3.4 Notes on Interrupt Routine.........................................................................................................5-24
5.3.5 Interrupt Disable State................................................................................................................5-27
Chapter 6
6 Clock Generation Circuit.............................................................................................................................6-1
6.1 Overview................................................................................................................................................6-1
6.1.1 Features ........................................................................................................................................6-1
6.1.2 Configuration................................................................................................................................6-1
6.1.3 List of Pins....................................................................................................................................6-2
6.2 Description of Registers.........................................................................................................................6-2
6.2.1 List of Registers............................................................................................................................6-2
6.2.2 Frequency Control Register 0 (FCON0) ......................................................................................6-3
6.2.3 Frequency Control Register 1 (FCON1) ......................................................................................6-4
6.3 Description of Operation........................................................................................................................6-5
6.3.1 Low-Speed Clock.........................................................................................................................6-5
6.3.1.1 Low-Speed Clock Generation Circuit (built-in RC oscillating circuit) ........................................... 6-5
6.3.1.2 Operation of Low-Speed Clock Generation Circuit ........................................................................ 6-6
6.3.2 High-Speed Clock ........................................................................................................................6-7
6.3.2.1 Built-in PLL Oscillation Mode........................................................................................................ 6-7
6.3.2.2 High-Speed External Clock Input Mode ......................................................................................... 6-8
6.3.2.3 Operation of High-Speed Clock Generation Circuit........................................................................ 6-9
6.3.3 Switching of System Clock ........................................................................................................6-10
6.4 Specifying port registers ......................................................................................................................6-11
6.4.1 Functioning PB7 (LSCLK) as the low speed clock output.........................................................6-11
6.4.2 Functioning PB0 (OUTCLK) as the High speed clock output...................................................6-12
6.4.3 Functioning PA2 (CLKIN) as the External clock input..............................................................6-13
Chapter 7
7 Time Base Counter......................................................................................................................................7-1
7.1 Overview................................................................................................................................................7-1
7.1.1 Features ........................................................................................................................................7-1
7.1.2 Configuration................................................................................................................................7-1
7.2 Description of Registers.........................................................................................................................7-3

ML610Q111/ML610Q112 User’s Manual
Contents
FEUL610Q111 Contents - 3
7.2.1 List of Registers............................................................................................................................7-3
7.2.2 Low-Speed Time Base Counter (LTBR) ......................................................................................7-4
7.2.3 High-Speed Time Base Counter Divide Register (HTBDR)........................................................7-5
7.3 Description of Operation........................................................................................................................7-6
7.3.1 Low-Speed Time Base Counter....................................................................................................7-6
7.3.2 High-Speed Time Base Counter...................................................................................................7-7
Chapter 8
8 Timers..........................................................................................................................................................8-1
8.1 Overview................................................................................................................................................8-1
8.1.1 Features ........................................................................................................................................8-1
8.1.2 Configuration................................................................................................................................8-2
8.1.3 List of Pins....................................................................................................................................8-4
8.2 Description of Registers.........................................................................................................................8-5
8.2.1 List of Registers............................................................................................................................8-5
8.2.2 Timer 8 Data Register (TM8D)....................................................................................................8-6
8.2.3 Timer 9 Data Register (TM9D)....................................................................................................8-7
8.2.4 Timer A Data Register (TMAD)...................................................................................................8-8
8.2.5 Timer B Data Register (TMBD)...................................................................................................8-9
8.2.6 Timer E Data Register (TMED).................................................................................................8-10
8.2.7 Timer F Data Register (TMFD)..................................................................................................8-11
8.2.8 Timer 8 Counter Register (TM8C).............................................................................................8-12
8.2.9 Timer 9 Counter Register (TM9C).............................................................................................8-13
8.2.10 Timer A Counter Register (TMAC)............................................................................................8-14
8.2.11 Timer B Counter Register (TMBC)............................................................................................8-15
8.2.12 Timer E Counter Register (TMEC)............................................................................................8-16
8.2.13 Timer F Counter Register (TMFC).............................................................................................8-17
8.2.14 Timer 8 Control Register 0 (TM8CON0)...................................................................................8-18
8.2.15 Timer 9 Control Register 0 (TM9CON0)...................................................................................8-19
8.2.16 Timer A Control Register 0 (TMACON0)..................................................................................8-20
8.2.17 Timer B Control Register 0 (TMBCON0)..................................................................................8-21
8.2.18 Timer E Control Register 0 (TMECON0)..................................................................................8-22
8.2.19 Timer F Control Register 0 (TMFCON0) ..................................................................................8-23
8.2.20 Timer 8 Control Register 1 (TM8CON1)...................................................................................8-24
8.2.21 Timer 9 Control Register 1 (TM9CON1)...................................................................................8-25
8.2.22 Timer A Control Register 1 (TMACON1)..................................................................................8-26
8.2.23 Timer B Control Register 1 (TMBCON1)..................................................................................8-27
8.2.24 Timer E Control Register 1 (TMECON1)..................................................................................8-28
8.2.25 Timer F Control Register 1 (TMFCON1) ..................................................................................8-29
8.2.26 Timer E Control Register 2 (TMECON2)..................................................................................8-30
8.2.27 Timer F Control Register 2 (TMFCON2) ..................................................................................8-31
8.2.28 Timer E Control Register 3 (TMECON3)..................................................................................8-33
8.2.29 Timer F Control Register 3 (TMFCON3) ..................................................................................8-34
8.3 Description of Operation......................................................................................................................8-35
8.3.1 Timer basic operation.................................................................................................................8-35
8.3.2 The external timer start/stop operation.......................................................................................8-37
8.3.3 The external timer operation ......................................................................................................8-37
8.4 Restriction of timer ..............................................................................................................................8-39
8.4.1 Restriction 1 ...............................................................................................................................8-39
8.4.1 Restriction 2 ...............................................................................................................................8-39
8.4.1 Restriction 3 ...............................................................................................................................8-39
8.5 Specifying port registers ......................................................................................................................8-40
8.5.1 Functioning PA0 (TM9OUT) as the timer output ......................................................................8-40
8.5.2 Functioning PC3 (TMFOUT) as the timer output......................................................................8-41
Chapter 9
9 Watchdog Timer ..........................................................................................................................................9-1
9.1 Overview................................................................................................................................................9-1
9.1.1 Features ........................................................................................................................................9-1

ML610Q111/ML610Q112 User’s Manual
Contents
FEUL610Q111 Contents - 4
9.1.2 Configuration................................................................................................................................9-1
9.2 Description of Registers.........................................................................................................................9-2
9.2.1 List of Registers............................................................................................................................9-2
9.2.2 Watchdog Timer Control Register (WDTCON)...........................................................................9-3
9.2.3 Watchdog Timer Mode Register (WDTMOD).............................................................................9-4
9.3 Description of Operation........................................................................................................................9-5
9.3.1 Handling example when you do not want to use the watchdog timer..........................................9-7
Chapter 10
10 PWM..........................................................................................................................................................10-1
10.1 Overview..............................................................................................................................................10-1
10.1.1 Features ......................................................................................................................................10-1
10.1.2 Configuration..............................................................................................................................10-2
10.1.3 List of Pins..................................................................................................................................10-3
10.2 Description of Registers.......................................................................................................................10-4
10.2.1 List of Registers..........................................................................................................................10-4
10.2.2 PWMC Period Registers (PWCPL, PWCPH)............................................................................10-5
10.2.3 PWMC Duty Registers (PWCDL, PWCDH).............................................................................10-6
10.2.4 PWMC Counter Registers (PWCCH, PWCCL).........................................................................10-7
10.2.5 PWMC Control Register 0 (PWCCON0)...................................................................................10-8
10.2.6 PWMC Control Register 1 (PWCCON1)...................................................................................10-9
10.2.7 PWMC Control Register 2 (PWCCON2).................................................................................10-10
10.2.8 PWMC Control Register 3 (PWCCON3).................................................................................10-11
10.2.9 PWMD Period Registers (PWCPL, PWCPH)..........................................................................10-12
10.2.10 PWMD Duty Registers (PWDDL, PWDDH) ..........................................................................10-13
10.2.11 PWMD Counter Registers (PWDCH, PWDCL)......................................................................10-14
10.2.12 PWMD Control Register 0 (PWDCON0)................................................................................10-15
10.2.13 PWMD Control Register 1 (PWDCON1)................................................................................10-16
10.2.14 PWMD Control Register 2 (PWDCON2)................................................................................10-17
10.2.15 PWMD Control Register 3 (PWDCON3)................................................................................10-18
10.2.16 PWME Period Registers (PWEPL, PWEPH)...........................................................................10-19
10.2.17 PWME Duty Registers (PWEDL, PWEDH)............................................................................10-20
10.2.18 PWME Counter Registers (PWECH, PWECL) .......................................................................10-21
10.2.19 PWME Control Register 0 (PWECON0).................................................................................10-22
10.2.20 PWME Control Register 1 (PWECON1).................................................................................10-23
10.2.21 PWME Control Register 2 (PWECON2).................................................................................10-24
10.2.22 PWME Control Register 3 (PWECON3).................................................................................10-25
10.2.23 PWMF Period Registers (PWFPL, PWFPH) ...........................................................................10-26
10.2.24 PWMF0 Duty Registers (PWF0DL, PWF0DH) ......................................................................10-27
10.2.25 PWMF1 Duty Registers (PWF1DL, PWF1DH) ......................................................................10-28
10.2.26 PWMF2 Duty Registers (PWF2DL, PWF2DH) ......................................................................10-29
10.2.27 PWMF Counter Registers (PWFCH, PWFCL)........................................................................10-30
10.2.28 PWMF Control Register 0 (PWFCON0)..................................................................................10-31
10.2.29 PWMF Control Register 1 (PWFCON1)..................................................................................10-32
10.2.30 PWMF Control Register 2 (PWFCON2)..................................................................................10-33
10.2.31 PWMF Control Register 3 (PWFCON3)..................................................................................10-34
10.2.32 PWMF Control Register 4 (PWFCON4)..................................................................................10-35
10.2.33 PWMF Control Register 5 (PWFCON5)..................................................................................10-36
10.3 Description of Operation....................................................................................................................10-37
10.3.1 Start, Stop, and Clear Operations of PWM by External Input Control.....................................10-39
10.3.2 Emergency Stop Operation.......................................................................................................10-39
10.3.3 PWMF Operation .....................................................................................................................10-40
10.3.4 Interrupt of PWM.....................................................................................................................10-42
10.4 Specifying port registers ....................................................................................................................10-43
10.4.1 Functioning PA0 (PWMC) as the PWM output.......................................................................10-43
10.4.2 Functioning PB0 (PWMC) as the PWM output.......................................................................10-44
10.4.3 Functioning PB7 (PWMC) as the PWM output.......................................................................10-45

ML610Q111/ML610Q112 User’s Manual
Contents
FEUL610Q111 Contents - 5
Chapter 11
11 Synchronous Serial Port ............................................................................................................................11-1
11.1 Overview..............................................................................................................................................11-1
11.1.1 Features ......................................................................................................................................11-1
11.1.2 Configuration..............................................................................................................................11-1
11.1.3 List of Pins..................................................................................................................................11-2
11.2 Description of Registers.......................................................................................................................11-3
11.2.1 List of Registers..........................................................................................................................11-3
11.2.2 Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH)..............................................11-4
11.2.3 Serial Port Control Register (SIO0CON)...................................................................................11-5
11.2.4 Serial Port Mode Register 0 (SIO0MOD0)................................................................................11-6
11.2.5 Serial Port Mode Register 1 (SIO0MOD1)................................................................................11-7
11.3 Description of Operation......................................................................................................................11-8
11.3.1 Transmit Operation.....................................................................................................................11-8
11.3.2 Receive Operation......................................................................................................................11-9
11.3.3 Transmit/Receive Operation.....................................................................................................11-10
11.4 Specifying port registers ....................................................................................................................11-11
11.4.1 Functioning as the SSIO master mode ..................................................................................... 11-11
11.4.2 Functioning as the SSIO slave mode........................................................................................11-12
Chapter 12
12 UART ........................................................................................................................................................12-1
12.1 Overview............................................................................................................................................12-1
12.1.1 Features ......................................................................................................................................12-1
12.1.2 Configuration..............................................................................................................................12-1
12.1.3 List of Pins..................................................................................................................................12-2
12.2 Description of Registers.....................................................................................................................12-2
12.2.1 List of Registers..........................................................................................................................12-2
12.2.2 UART0 Transmit/Receive Buffer (UA0BUF)............................................................................12-3
12.2.3 UART1 Transmit/Receive Buffer (UA1BUF)............................................................................12-3
12.2.4 UART0 Control Register (UA0CON)........................................................................................12-4
12.2.5 UART1 Control Register (UA1CON)........................................................................................12-4
12.2.6 UART0 Mode Register 0 (UA0MOD0).....................................................................................12-5
12.2.7 UART1 Mode Register 0 (UA1MOD0).....................................................................................12-6
12.2.8 UART0 Mode Register 1 (UA0MOD1).....................................................................................12-7
12.2.9 UART1 Mode Register 1 (UA1MOD1).....................................................................................12-8
12.2.10 UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH)....................................................12-9
12.2.11 UART1 Baud Rate Registers L, H (UA1BRTL, UA1BRTH)..................................................12-10
12.2.12 UART0 Status Register (UA0STAT)........................................................................................12-11
12.2.13 UART1 Status Register (UA1STAT)........................................................................................12-12
12.3 Description of Operation..................................................................................................................12-13
12.3.1 Transfer Data Format................................................................................................................12-13
12.3.2 Baud rate...................................................................................................................................12-14
12.3.3 Transmitted Data Direction ......................................................................................................12-15
12.3.4 Transmit Operation...................................................................................................................12-16
12.3.5 Receive Operation....................................................................................................................12-17
12.3.5.1 Detection of Start Bit................................................................................................................... 12-18
12.3.5.2 Sampling Timing ......................................................................................................................... 12-18
12.3.5.3 Reception Margin........................................................................................................................ 12-19
12.4 Specifying port registers...................................................................................................................12-20
12.4.1 Functioning PB1(TXD0) and PB0(RXD0) as the UART.........................................................12-20
12.4.2 Functioning PB4(TXD0) and PB5(RXD0) as the UART.........................................................12-21
12.4.3 Functioning PB1(TXD1) and PB2(RXD1) as the UART.........................................................12-22
12.4.4 Functioning PB3(TXD1) and PB2(RXD1) as the UART.........................................................12-23
12.4.5 Functioning PB4(TXD1) and PB2(RXD1) as the UART.........................................................12-24
12.4.6 Functioning PB1(TXD1) and PB7(RXD1) as the UART.........................................................12-25
12.4.7 Functioning PB3(TXD1) and PB7(RXD1) as the UART.........................................................12-26
12.4.8 Functioning PB4(TXD1) and PB7(RXD1) as the UART.........................................................12-27

ML610Q111/ML610Q112 User’s Manual
Contents
FEUL610Q111 Contents - 6
Chapter 13
13 I2C Bus Interface Master...........................................................................................................................13-1
13.1 Overview..............................................................................................................................................13-1
13.1.1 Features ......................................................................................................................................13-1
13.1.2 Configuration..............................................................................................................................13-1
13.1.3 List of Pins..................................................................................................................................13-1
13.2 OverviewDescription of Registers.......................................................................................................13-2
13.2.1 List of Registers..........................................................................................................................13-2
13.2.2 I2C Bus 0 Receive Register (I2C0RD).......................................................................................13-3
13.2.3 I2C Bus 0 Slave Address Register (I2C0SA).............................................................................13-4
13.2.4 I2C Bus 0 Transmit Data Register (I2C0TD).............................................................................13-5
13.2.5 I2C Bus 0 Control Register (I2C0CON) ....................................................................................13-6
13.2.6 I2C Bus 0 Mode Register (I2C0MOD) ......................................................................................13-7
13.2.7 I2C Bus 0 Status Register (I2C0STAT)......................................................................................13-8
13.3 Description of Operation......................................................................................................................13-9
13.3.1 Communication Operating Mode...............................................................................................13-9
13.3.1.1 Start Condition............................................................................................................................... 13-9
13.3.1.2 Repeated Start Condition............................................................................................................... 13-9
13.3.1.3 Slave Address Transmit Mode....................................................................................................... 13-9
13.3.1.4 Data Transmit Mode...................................................................................................................... 13-9
13.3.1.5 Data Receive Mode ....................................................................................................................... 13-9
13.3.1.6 Control Register Setting Wait State............................................................................................... 13-9
13.3.1.7 Stop Condition............................................................................................................................... 13-9
13.3.2 Communication Operation Timing...........................................................................................13-10
13.3.3 Operation Waveforms...............................................................................................................13-12
13.4 Specifying port registers ....................................................................................................................13-13
13.4.1 Functioning PB5(SCL) and PB6(SDA) as the I2C...................................................................13-13
Chapter 14
14 I2C Bus Interface Slave.............................................................................................................................14-1
14.1 Overview..............................................................................................................................................14-1
14.1.1 Features ......................................................................................................................................14-1
14.1.2 Configuration..............................................................................................................................14-1
14.1.3 List of Pins..................................................................................................................................14-2
14.2 Description of Registers.......................................................................................................................14-3
14.2.1 List of Registers..........................................................................................................................14-3
14.2.2 I2C Bus 1 Receive Register (I2C1RD).......................................................................................14-4
14.2.3 I2C Bus 1 Slave Address Register (I2C1SA).............................................................................14-5
14.2.4 I2C Bus 1 Transmit Data Register (I2C1TD).............................................................................14-6
14.2.5 I2C Bus 1 Control Register (I2C1CON) ....................................................................................14-7
14.2.6 I2C Bus 1 Mode Register (I2C1MOD) ......................................................................................14-8
14.2.7 I2C Bus 1 Status Register (I2C1STAT)......................................................................................14-9
14.3 Description of Operation....................................................................................................................14-11
14.3.1 Communication Operating Mode.............................................................................................14-11
14.3.1.1 Start Condition..............................................................................................................................14-11
14.3.1.2 Slave Address Receive Mode .......................................................................................................14-11
14.3.1.3 Communication Wait State ...........................................................................................................14-11
14.3.1.4 Data Transmit Mode.....................................................................................................................14-11
14.3.1.5 Data Receive Mode ......................................................................................................................14-11
14.3.1.6 Stop Condition..............................................................................................................................14-11
14.3.2 Communication Operation Timing...........................................................................................14-12
14.3.3 Operation Waveforms...............................................................................................................14-13
14.4 Specifying port registers ....................................................................................................................14-14
14.4.1 Functioning PB5(SCL) and PB6(SDA) as the I2C...................................................................14-14
Chapter 15
15 Port A.........................................................................................................................................................15-1
15.1 Overview..............................................................................................................................................15-1
15.1.1 Features ......................................................................................................................................15-1