Lattice Semiconductor HW-USBN-2B User manual

Programming Cables
User Guide
FPGA-UG-02042-26.2
May 2019

Programming Cables
User Guide
© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-UG-02042-26.2
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely
with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been
subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the
same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s
product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this
document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any
products at any time without notice.

Programming Cables
User Guide
© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02042-26.2 3
Contents
1. Features.........................................................................................................................................................................5
2. Programming Cables .....................................................................................................................................................5
3. Programming Cable Pin Definitions...............................................................................................................................6
4. Programming Software .................................................................................................................................................8
5. Target Board Design Considerations .............................................................................................................................8
6. Programming Flywire and Connection Reference.........................................................................................................9
7. Connecting the Programming Cable............................................................................................................................12
8. Programming Cable TRST Pin ......................................................................................................................................12
9. Programming Cable ispEN Pin .....................................................................................................................................12
10. Ordering Information ..................................................................................................................................................13
Appendix A. Troubleshooting the USB Driver Installation..................................................................................................14
Technical Support ...............................................................................................................................................................18
Revision History ..................................................................................................................................................................18

Programming Cables
User Guide
© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-UG-02042-26.2
Figures
Figure 1.1. USB Cable –HW-USBN-2B ..................................................................................................................................5
Figure 3.1. Programming Cable In-System Programming Interface for the PC (HW-USBN-2B)* .........................................6
Figure 3.2. Programming Cable In-System Programming Interface for the PC (HW-USB-1A or HW-USB-2A)* ...................7
Figure 3.3. Programming Cable In-System Programming Interface for the PC (HW-DLN-3C and Equivalents)*..................7
Figure 3.4. Programming Cable In-System Programming Interface for the PC (pDS4102-DL2 or pDS4102- DL2A) .............7
Figure 3.5. Programming Cable In-System Programming Interface for the PC (HW7265-DL2 or HW7265-DL2A)*.............7
Figure A.1. Device Manager................................................................................................................................................14
Figure A.2. Unknown Device Properties .............................................................................................................................14
Figure A.3. Update Driver Software....................................................................................................................................15
Figure A.4. Lattice EzUSB Driver .........................................................................................................................................15
Figure A.5. FTDI FTUSB Driver.............................................................................................................................................15
Figure A.6. Windows Security .............................................................................................................................................16
Figure A.7. USB Installation Completed..............................................................................................................................16
Figure A.8. Installation Completed .....................................................................................................................................17
Figure A.9. Installation Completed .....................................................................................................................................17
Tables
Table 3.1. Programming Cable Pin Definitions .....................................................................................................................6
Table 6.1. Pin and Cable Reference ......................................................................................................................................9
Table 10.1. Programming Cable Feature Summary ............................................................................................................13
Table 10.2. Ordering Information.......................................................................................................................................13

Programming Cables
User Guide
© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02042-26.2 5
1. Features
Support for all Lattice programmable products
1.2 V to 3.3 V programming (HW-USBN-2B)
1.2 V to 5 V programming (All other cables)
Ideal for design prototyping and debugging
Connect to multiple PC interfaces
USB (v.1.0, v.2.0)
PC Parallel Port
Easy-to-use programming connectors
Versatile flywire, 2 x 5 (.100”) or 1 x 8 (.100”) connectors
6 feet (2 meters) or more of programming cable length (PC to DUT)
Lead-free/RoHS compliant construction
Figure 1.1. USB Cable –HW-USBN-2B
2. Programming Cables
Lattice Programming Cable products are the hardware connection for in-system programming of all Lattice devices.
After you complete your logic design and create a programming file with the Lattice Diamond®/ispLEVER® Classic
development tools, you can use Diamond Programmer or ispVM™ System software to program devices on your board.
The ispVM System/Diamond Programmer software automatically generates the appropriate programming commands,
programming addresses and programming data based on information stored in the programming file and parameters
you set in Diamond Programmer/ispVM System. Programming signals are then generated from the USB or parallel port
of a PC and directed through the programming cable to the device. No additional components are required for
programming.
Diamond Programmer/ispVM System software is included with all Lattice design tool products and is available for
download from the Lattice web site at www.latticesemi.com/software.

Programming Cables
User Guide
© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-UG-02042-26.2
3. Programming Cable Pin Definitions
The functions provided by the programming cables correspond with available functions on Lattice programmable
devices. Since some devices contain different programming features, the specific functions provided by the
programming cable may depend on the selected target device. ispVM System/Diamond Programmer software
automatically generates the appropriate functions based on the selected device. See Table 3.1 for an overview of the
programming cable functions.
Table 3.1. Programming Cable Pin Definitions
Programming Cable Pin
Name
Programming Cable Pin Type
Description
VCC
Programming
Voltage
Input
Connect to VCC or VCCJ plane of the target device.
Typical ICC = 10 mA. Your board design supplies
the power for VCC. Note: This may not be the
same as a target device’s VCCO plane.
TDO/SO
Test Data
Output
Input
Used to shift data out via the IEEE1149.1 (JTAG)
programming standard.
TDI/SI
Test Data Input
Output
Used to shift data in via the IEEE1149.1
programming standard.
ispEN/PROG/SN
Enable
Output
Enable device to be programmed.
SN = SSPI Chip select for HW-USBN-2B
TRST
Test Reset
Output
Optional IEEE 1149.1 state machine reset.
DONE
DONE
Input
DONE indicates status of configuration
TMS
Test Mode
Select Input
Output
Used to control the IEEE1149.1 state machine.
GND
Ground
Input
Connect to ground plane of the target device
TCK/SCLK
Test Clock Input
Output
Used to clock the IEEE1149.1 state machine
INIT
Initialize
Input
Indicates device is ready for configuration to
begin. INITN is only found on some devices.
I2C: SCL*
I2C SCL
Output
Provides the I2C signal SCL
I2C: SDA*
I2C SDA
Output
Provides the I2C signal SDA.
5 V Out*
5 V Out
Output
Provides a 5 V signal for the iCEprogM1050
Programmer.
*Note: Only found on the HW-USBN-2B cable.
TRST
GND *
TMS *
TDI/SI *
TDO/SO *
ISPEN/PROG/SN
VCC *
5 V OUT
I2C: SCL
TCK/SCLK*
I2C: SDA
DONE
* Indicates flywire connections required formost basicJTAGprogramming.
Figure 3.1. Programming Cable In-System Programming Interface for the PC (HW-USBN-2B)*
*Note: Requires Diamond Programmer 3.1 or later.

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© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02042-26.2 7
To System
Board
To PC
61
Function
VCC
SDO/TDO
SDI/TDI
ispEN/Enable/PROG
TRST/DONE
MODE/TMS
GND
SCLK/TCK
INIT
Color
Red
Brown
Orange
Yellow
Green
Purple
Black
White
Blue
HW-USB-1A
®
Figure 3.2. Programming Cable In-System Programming Interface for the PC (HW-USB-1A or HW-USB-2A)*
*Note: Lattice PAC-Designer®software does not support programming with USB cables. To program ispPAC devices with these cables,
use the Diamond Programmer/ispVM System software.
Function
VCC
SDO/TDO
SDI/TDI
ispEN/Enable/Prog
TRST
MODE/TMS
GND
SCLK/TCK
To
System
Board
Color
Red
Brown
Orange
Yellow
Green
Purple
Black
White
61
25-pin
Parallel
Port
Adapter
HW7265-DL3 and HW7265-DL3A –Grey Housing with RJ-45 Connector
Other Cables are Labeled with Part Number
To PC
Figure 3.3. Programming Cable In-System Programming Interface for the PC (HW-DLN-3C and Equivalents)*
*Note: HW7265-DL3, HW7265-DL3A, HW-DL-3B, HW-DL-3C and HW-DLN-3C are functionally equivalent products.
6'
1
2
3
4
5
Function Pin #
6
7
8
.01f*
Capacitor
End View
Note: Capacitor Recommended on System Board
25-pin
Parallel
Port
Adapter
RJ-45 Connector
Eight Positions
pDS4102-DL2 –Blue Housing
pDS4102-DL2A –GreyHousing
.100" Center-Spacing
Eight Positions
VCC
SDO/TDO
SDI/TDI
ispEN/Enable/PROG
TRST
MODE/TMS
GND
SCLK/TCK
To PC To System
Board
Figure 3.4. Programming Cable In-System Programming Interface for the PC (pDS4102-DL2 or pDS4102- DL2A)
Figure 3.5. Programming Cable In-System Programming Interface for the PC (HW7265-DL2 or HW7265-DL2A)*
*Note: For reference purposes, the 2 x 10 connector on the HW7265-DL2 or HW7265-DL2A is equivalent to Tyco 102387-1. This will
interface to standard 100-mil spacing 2 x 5 headers, or a 2 x 5 keyed, recessed male connector such as the 3M N2510-5002RB.

Programming Cables
User Guide
© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-UG-02042-26.2
4. Programming Software
Diamond Programmer and ispVM System for Classic devices is the preferred programming management software tool
for all Lattice devices and download cables. The latest version of Lattice Diamond Programmer or ispVM System
software is available for download from the Lattice web site at www.latticesemi.com/software.
5. Target Board Design Considerations
A 4.7K pull-down resistor is recommended on the TCK connection of the target board. This pull-down is recommended
to avoid inadvertent clocking of the TAP controller induced by fast clock edges or as VCC ramps up. This pull-down is
recommended for all Lattice programmable families.
The I2C signals SCL and SDA are open drain. A 2.2K pull-up resistor to VCC is required on the target board.
For Lattice device families that feature low power, it is recommended to add a 500 Ωresistor between VCCJ and GND
during the programming interval when a USB programming cable is connected to a very low power board design. A
FAQ is available that discusses this in more depth at:
http://www.latticesemi.com/en/Support/AnswerDatabase/2/2/0/2205
The JTAG programming port speed may need to be governed when using the programming cables connected to
customer PCBs. This is especially important when there is long PCB routing or with many daisy-chained devices. The
Lattice programming software can adjust the timing of TCK applied to the JTAG programming port from the cable. This
low-precision port setting of TCK depends on many factors, including the PC speed and the type of cable used (parallel
port, USB or USB2). This software feature provides an option to slow the TCK for debug or noisy environments. A FAQ is
available that discusses this in more depth at: http://www.latticesemi.com/en/Support/AnswerDatabase/9/7/974.aspx
The USB download cable can be used to program Power Manager or ispClock products with Lattice programming
software. When using the USB cable with the Power Manager I devices, (POWR604, POWR1208, POWR1208P1), you
must slow do TCK by a factor of 2. A FAQ is available that discusses this in more depth at:
http://www.latticesemi.com/en/Support/AnswerDatabase/3/0/306.aspx

Programming Cables
User Guide
© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02042-26.2 9
6. Programming Flywire and Connection Reference
Refer to Table 6.1 to identify, per Lattice device, how to connect various Lattice programming cable flywires. JTAG, SPI and I2C configuration ports are
unambiguously identified. Legacy cables and hardware are included for reference. In addition, various header configurations are tabulated.
Table 6.1. Pin and Cable Reference
HW-USBN-2B
Flywire color
TDI/SI
TDO/SO
TMS
TCK/SCLK
ISPEN/PROG
DONE
TRST(OUTPUT)
VCC
GND
I2C: SCL
I2C: SDA
5 V Out
Orange
Brown
Purple
White
Yellow
Blue
Green
Red
Black
Yellow/White
Green/White
Red/White
HW-USBN-2A
Flywire color
TDI
TDO
TMS
TCK
ispEN/PROG
INIT
TRST(OUTPUT)/DONE(INPUT)
VCC
GND
na
Orange
Brown
Purple
White
Yellow
Blue
Green
Red
Black
HW-DLN-3C
Flywire color
TDI
TDO
TMS
TCK
ispEN/PROG
na
TRST(OUTPUT)
VCC
GND
na
Orange
Brown
Purple
White
Yellow
Green
Red
Black
Programming cable pin type
Target Board Recommendation
Output
Input
Output
Output
Output
Input
Input/Output
Input
Input
Output
Output
Output
—
—
4.7 kΩ
Pull-Up
4.7kΩ
Pull-Down
(Note 1)
—
—
(Note 2)
—
(Note 3)
(Note 3)
—
Connect the programming cable wires (above) to the corresponding device or header pins (below).
JTAG Port Devices
ECP5™
TDI
TDO
TMS
TCK
Optional connections to device ispEN, PROGRAMN,
INITN, DONE and/or TRST signals
(Define in Custom I/O settings in ispVM System
or Diamond Programmer software.
Not all devices have these pins available)
Required
Required
—
—
—
LatticeECP3™/LatticeECP2M™
LatticeECP2™/LatticeECP™/
LatticeEC™
TDI
TDO
TMS
TCK
Required
Required
—
—
—
LatticeXP2™/LatticeXP™
TDI
TDO
TMS
TCK
Required
Required
—
—
—
LatticeSC™/LatticeSCM™
TDI
TDO
TMS
TCK
Required
Required
—
—
—
MachXO2™/MachXO3™/MachXO3D™
TDI
TDO
TMS
TCK
Required
Required
—
—
—
MachXO™
TDI
TDO
TMS
TCK
Required
Required
—
—
—
ORCA®/FPSC
TDI
TDO
TMS
TCK
Required
Required
—
—
—
ispXPGA®/ispXPLD™
TDI
TDO
TMS
TCK
Required
Required
—
—
—
ispMACH® 4000/ispMACH/ispLSI® 5000
TDI
TDO
TMS
TCK
Required
Required
—
—
—
MACH®4A
TDI
TDO
TMS
TCK
Required
Required
—
—
—
ispGDX2™
TDI
TDO
TMS
TCK
Required
Required
—
—
—
ispPAC®/ispClock™ (Note 4)
TDI
TDO
TMS
TCK
Required
Required
—
—
—
Platform Manager™/Power Manager/
Power Manager II/Platform Manager II
(Note 4)
TDI
TDO
TMS
TCK
Required
Required
—
—
—

Programming Cables
User Guide
© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-UG-02042-26.2
Table 6.1. Pin and Cable Reference (Continued)
HW-USBN-2B
Flywire color
TDI/SI
TDO/SO
TMS
TCK/SCLK
ISPEN/PROG
DONE
TRST(OUTPUT)
VCC
GND
I2C: SCL
I2C: SDA
5 V Out
Orange
Brown
Purple
White
Yellow
Blue
Green
Red
Black
Yellow/White
Green/White
Red/White
HW-USBN-2A
Flywire color
TDI
TDO
TMS
TCK
ispEN/PROG
INIT
TRST(OUTPUT)/DONE(INPUT)
VCC
GND
na
Orange
Brown
Purple
White
Yellow
Blue
Green
Red
Black
HW-DLN-3C
Flywire color
TDI
TDO
TMS
TCK
ispEN/PROG
na
TRST(OUTPUT)
VCC
GND
na
Orange
Brown
Purple
White
Yellow
Green
Red
Black
Programming cable pin type
Target Board Recommendation
Output
Input
Output
Output
Output
Input
Input/Output
Input
Input
Output
Output
Output
—
—
4.7 kΩ
Pull-Up
4.7kΩ
Pull-Down
(Note 1)
—
—
(Note 2)
—
(Note 3)
(Note 3)
—
Connect the programming cable wires (above) to the corresponding device or header pins (below).
Slave SPI Port Devices
ECP5
MOSI
MISO
—
CCLK
SN
Optional connections to device
PROGRAMN, INITN and/or DONE signals
Required
Required
—
—
—
LatticeECP3
MOSI
MISO
—
CCLK
SN
Required
Required
—
—
—
MachXO2/MachXO3/MachXO3D
SI
SO
—
CCLK
SN
Required
Required
—
—
—
CrossLink™ LIF-MD6000
MOSI
MISO
—
SPI_SCK
SPI_SS
Opt.
CDONE
CRESET_B
Required
Required
—
—
—
iCE40™/iCE40LM/iCE40 Ultra™/
iCE40 UltraLite™
SPI_SI
SPI_SO
—
SPI_SCK
SPI_SS_B
Opt.
CDONE
CRESET_B
Required
Required
—
—
—
I2C Port Devices
MachXO2/MachXO3/MachXO3D
—
—
—
—
Optional connections to device PROGRAMN, INITN
and/or DONE signals
Required
Required
SCL
SDA
—
Platform Manager II
—
—
—
—
Required
Required
SCL_M + SCL_S
SDA_M + SDA_S
—
L-ASC10
—
—
—
—
—
—
—
Required
Required
SCL
SDA
—
CrossLink LIF-MD6000
—
—
—
—
—
Opt.
CDONE
CRESET_B
Required
Required
SCL
SDA
—
Headers
1 x 10 conn (various cables)
3
2
6
8
4
9 or 10
5 or 9
1
7
—
—
—
1 x 8 conn (see Figure 3.4)
3
2
6
8
4
—
5
1
7
—
—
—
2 x 5 conn (see Figure 3.5)
5
7
3
1
10
—
9
6
2, 4,or 8
—
—
—
Programmers
Model 300
5
7
3
1
10
—
9
6
2, 4,or 8
—
—
—
iCEprog™iCEprogM1050
8
5
—
7
9
3
1
6
10
—
—
4 (Note 5)

Programming Cables
User Guide
© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02042-26.2 11
Notes:
1. For older Lattice ISP devices, a 0.01 μF decoupling capacitor is required on ispEN/ENABLE of the target board.
2. For HW-USBN-2A/2B, the target board supplies the power - Typical ICC = 10 mA. For devices that have a VCCJ pin, the VCCJ must be connected to the cable’s VCC. For other
devices, connect the appropriate bank VCCIO to the cable's VCC. A 0.1 μF decoupling capacitor is required on VCCJ or VCCIO close to the device. Please refer to the device data
sheet to determine if the device has a VCCJ pin or what VCCIO bank governs the target programming port (this may not be the same as a target device’s core VCC/VSS plane).
3. Open drain signals. External pull-up ~2.2 kΩresistor to the appropriate bank VCCIO or VCCJ is required.
4. When using PAC-Designer® software to program ispPAC or ispClock devices, do not connect TRST/DONE.
5. If using a cable older than HW-USBN-2B, connect a +5 V external supply between iCEprogM1050 pin 4 (VCC) and pin 2 (GND).

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© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-UG-02042-26.2
7. Connecting the Programming Cable
The target board must be unpowered when connecting, disconnecting, or reconnecting the programming cable. Always
connect the programming cable’s GND pin (black wire) before connecting any other JTAG pins. Failure to follow these
procedures can result in damage to the target programmable device.
8. Programming Cable TRST Pin
Connecting the board TRST pin to the cable TRST pin is not recommended. Instead, connect the board TRST pin to Vcc.
If the board TRST pin is connected to the cable TRST pin, instruct ispVM/Diamond Programmer to drive the TRST pin
high.
To configure ispVM/Diamond Programmer to drive TRST pin high:
Select the Options menu item.
Select Cable and I/O Port Setup.
Select the TRST/Reset Pin Connected checkbox.
Select the Set High radio button.
If the proper option is not selected, the TRST pin is driven low by ispVM/Diamond Programmer. Consequently, the
BSCAN chain does not work because the chain is locked into RESET state.
9. Programming Cable ispEN Pin
The following pins should be grounded:
BSCAN pin of the 2000VE devices
ENABLE pin of MACH4A3/5-128/64, MACH4A3/5-64/64 and MACH4A3/5-256/128 devices.
However, you have the option of having the BSCAN and ENABLE pins driven by the ispEN pin from the cable. In this
case, ispVM/Diamond Programmer must be configured to drive the ispEN pin low as follows:
To configure ispVM/Diamond Programmer to drive ispEN pin low:
Select the Options menu item.
Select Cable and I/O Port Setup.
Select the ispEN/BSCAN Pin Connected checkbox.
Select the Set Low radio button.
Each programming cable ships with two small connectors that help you keep the flywires organized. The following
manufacturer and part number is one possible source for equivalent connectors:
1 x 8 Connector (for example, Samtec SSQ-108-02-T-S)
2 x 5 Connector (for example, Samtec SSQ-105-02-T-D)
The programming cable flywire or headers are intended to connect to standard 100-mil spacing headers (pins spaced
0.100 inch apart). Lattice recommends a header with length of 0.243 inches or 6.17 mm. Though, headers of other
lengths may work equally well.

Programming Cables
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© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02042-26.2 13
10. Ordering Information
Table 10.1. Programming Cable Feature Summary
Feature
HW-USBN-2B
HW-USBN-2A
HW-USB-2A
HW-USB-1A
HW-DLN-3C
HW7265-DL3,
HW7265-DL3A,
HW-DL-3B,
HW-DL-3C
HW7265-DL2
HW7265-DL2A
PDS4102-DL2
PDS4102-DL2A
USB
X
X
X
X
—
—
—
—
—
—
PC-Parallel
—
—
—
—
X
X
X
X
X
X
1.2 V Support
X
X
X
—
—
—
—
—
—
—
1.8 V Support
X
X
X
X
X
X
—
X
—
X
2.5-3.3 V
Support
X
X
X
X
X
X
X
X
X
X
5.0 V Support
—
X
X
X
X
X
X
X
X
X
2 x 5 Connector
—
X
X
X
X
X
X
X
—
—
1 x 8 Connector
X
X
X
X
X
—
—
X
X
Flywire
X
X
X
X
X
X
—
—
—
—
Lead-free
Construction
X
X
—
—
X
—
—
—
—
—
Available for
order
X
—
—
—
X
—
—
—
—
—
Table 10.2. Ordering Information
Description
Ordering Part Number
China RoHS Environment- Friendly
Use Period (EFUP)
Programming cable (USB). Contains 6' USB cable, flywire
connectors, 8-position (1 x 8) adapter and 10-position (2 x 5)
adapter, lead-free, RoHS compliant construction.
HW-USBN-2B
Programming cable (PC only). Contains parallel port adapter, 6'
cable, flywire connectors, 8-position (1 x 8) adapter and 10-
position (2 x 5) adapter, lead-free, RoHS compliant construction.
HW-DLN-3C
Note: Additional cables are described in this document for legacy purposes only, these cables are no longer produced. The cables
currently available for order are fully equivalent replacement items.

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User Guide
© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14 FPGA-UG-02042-26.2
Appendix A. Troubleshooting the USB Driver Installation
It is essential that you install the drivers before connecting your PC to the USB cable. If the cable is connected before
installing the drivers, Windows will try to install its own drivers that may not work.
If you have attempted to connect the PC to the USB cable without first installing the appropriate drivers, or have
trouble communicating with the Lattice USB cable after installing the drivers, follow the steps below:
Plug in the Lattice USB cable. Choose Start > Settings > Control Panel > System.
In the System Properties dialog box, click the Hardware tab and Device Manager button. Under Universal Serial
Bus controllers, you should see Lattice USB ISP Programmer. If you do not see this, look for the Unknown Device
with the yellow flag. Double click on the Unknown Device icon.
Figure A.1. Device Manager
In the Unknown device Properties dialog box, click Reinstall Driver.
Figure A.2. Unknown Device Properties
Select Browse my computer for driver software.

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User Guide
© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02042-26.2 15
Figure A.3. Update Driver Software
Browse to the isptools\ispvmsystem directory for the Lattice EzUSB driver.
Figure A.4. Lattice EzUSB Driver
Browse to the isptools\ispvmsystem\Drivers\FTDIUSBDriver directory for the FTDI FTUSB driver.
Figure A.5. FTDI FTUSB Driver

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User Guide
© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16 FPGA-UG-02042-26.2
For Diamond installations, browse to lscc/diamond/data/vmdata/drivers. Click Next.
Select Install this Driver software anyway. The system updates the driver.
Figure A.6. Windows Security
Click Close and finish installing the USB driver.
Figure A.7. USB Installation Completed
Under Control Panel >System >Device Manager > Universal Serial Bus Controllers should include the following:
For the Lattice EzUSB Driver: Lattice USB ISP Programmer device installed.

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© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02042-26.2 17
Figure A.8. Installation Completed
For the FTDI FTUSB Driver: USB Serial Converter A and Converter B devices installed.
Figure A.9. Installation Completed
If you are experiencing problems or need additional information, contact Lattice Technical Support.

Programming Cables
User Guide
© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18 FPGA-UG-02042-26.2
Technical Support
For assistance, submit a technical support case at www.latticesemi.com/techsupport.
Revision History
Revision 26.2, May 2019
Section
Change Summary
—
Added Disclaimers section.
Programming Flywire and
Connection Reference
Updated Table 6.1. Pin and Cable Reference.
Added MachXO3D
Added CRESET_B to Crosslink I2C.
Updated items under I2C Port Devices
Added Platform Manager II.
Changed order of ispPAC.
Updated items under I2C Port Devices.
Changed Power Manager II to Platform Manager II and updated I2C: SDA value.
Changed ASC to L-ASC10
Updated footnote 4 to include ispClock devices.
Adjusted trademarks.
Revision History
Updated format.
Back cover
Updated template.
—
Minor editorial changes
Revision 26.1, May 2018
Section
Change Summary
All
Corrected entries in the Slave SPI Port Devices section of Table 6.1.
Revision 26.0, April 2018
Section
Change Summary
All
Changed document number from UG48 to FPGA-UG-02024.
Updated document template.
Programming Cables
Removed redundant information and changed link to www/latticesemi.com/software.
Programming Cable Pin
Definitions
Updated Programming Cable Pin names in Table 3.1. Programming Cable Pin Definitions.
Programming Flywire and
Connection Reference
Replaced Table 2. Flywire Conversion Reference and Table 3 Recommended Pin Connections
with a single Table 6.1 Pin and Cable Reference.
Ordering Information
Moved Table 10.1. Programming Cable Feature Summary under Ordering Information.
Revision 25.0, November 2016
Section
Change Summary
Programming Flywire and
Connection Reference
Revised Table 3, Recommended Pin Connections. Added CrossLink device.

Programming Cables
User Guide
© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02042-26.2 19
Revision 24.9, October 2015
Section
Change Summary
Programming Flywire and
Connection Reference
Revised Table 3, Recommended Pin Connections.
Added CRESET-B column.
Added iCE40 UltraLite device.
Technical Support Assistance
Updated Technical Support Assistance information.
Revision 24.8, March 2015
Section
Change Summary
Programming Cable Pin
Definitions
Revised description of INIT in Table 1, Programming Cable Pin Definitions.
Revision 24.7, January 2015
Section
Change Summary
Programming Cable Pin
Definitions
In Table 1, Programming Cable Pin Definitions, ispEN/Enable/PROG changed to
ispEN/Enable/PROG/SN and its description revised.
Updated Figure 2, Programming Cable In-System Programming Interface for the PC
(HW-USBN-2B).
Programming Cable ispEN Pin
In Table 4, Programming Cable Feature Summary, HW-USBN-2B marked as available for
order.
Ordering Information
HW-USBN-2A changed to HW- USBN-2B.
Revision 24.6, July 2014
Section
Change Summary
All
Changed document title from ispDOWNLOAD Cables to Programming Cables User’s Guide.
Programming Cable Pin
Definitions
Updated Table 3, Recommended Pin Connections. Added ECP5, iCE40LM, iCE40 Ultra, and
MachXO3 device families.
Target Board Design
Considerations
Updated section. Updated FAQ link on ispVM tool control of TCK duty cycle and/or
frequency.
Technical Support Assistance
Updated Technical Support Assistance information.
Revision 24.5, October 2012
Section
Change Summary
Programming Flywire and
Connection Reference
Added iCE40 configuration port pin names to the Flywire Conversion Reference table.
Programming Flywire and
Connection Reference
Added iCE40 information to Recommended Cable Connections table.
Revision 24.4, February 2012
Section
Change Summary
All
Updated document with new corporate logo.

Programming Cables
User Guide
© 2009-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20 FPGA-UG-02042-26.2
Revision 24.3, November 2011
Section
Change Summary
All
Document transferred to user’s guide format.
Features
Added Figure USB Cable –HW-USBN-2A.
Programming Flywire and
Connection Reference
Updated Recommended Cable Connections table for MachXO2 devices.
Target Board Design
Considerations
Updated section.
Appendix A
Added section.
Revision 24.2, October 2009
Section
Change Summary
All
Added information related to the physical specifications of the flywire connectors.
Revision 24.1, July 2009
Section
Change Summary
All
Added Target Board Design Considerations text section.
Programming Flywire and
Connection Reference
Added section heading.
Previous Revisions
Section
Change Summary
—
Previous Lattice releases.