Linear Analog Devices DC2984A User manual

1
DEMO MANUAL DC2984A
Rev. 0
DESCRIPTION
LT3383
Multioutput Power Management Solution
with 4 Buck Switching and 3 LDO Linear Regulators
DC2984A is a multi-output power management solution
demonstration circuit, featuring the LT
®
3383. It contains
two 2.5A synchronous step-down DC-DC regulators, two
1.5A synchronous step-down DC-DC regulators and three
300mA LDO regulators. All the regulators can be enabled All registered trademarks and trademarks are the property of their respective owners.
PERFORMANCE SUMMARY
BOARD PHOTO
via its corresponding enable pins. The startup sequence of
the regulators can be programmed by connecting the out-
puts of the regulators to the enable pins in desired order.
Design files for this circuit board are available.
Specifications are at TA= 25°C
Figure1. DC2984A Board Photo
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Voltage Range 2.7 5.5 V
VBUCK1 BUCK1 Output Voltage BUCK1 enabled, I(BUCK1) = 0~2.5A 1.20 V
VBUCK2 BUCK2 Output Voltage BUCK2 enabled, I(BUCK2) = 0~2.5A 1.50 V
VBUCK3 BUCK3 Output Voltage BUCK3 enabled, I(BUCK3) = 0~1.5A 1.81 V
VBUCK4 BUCK4 Output Voltage BUCK4 enabled, I(BUCK4) = 0~1.5A 3.31 V
VLDO1 LDO1 Output Voltage LDO1 enabled, I(LDO1) = 0~300mA 1.20 V
VLDO2 LDO2 Output Voltage LDO2 enabled, I(LDO2) = 0~300mA 0.80 V
VLDO2 LDO3 Output Voltage LDO3 enabled, I(LDO3) = 0~300mA 1.80 V

2
DEMO MANUAL DC2984A
Rev. 0
QUICK START PROCEDURE
Follow the procedure below to familiarize yourself with
the DC2984A.
1. Refer to Figure2, configure the jumpers on the demo
board as follows:
JP1 = VIN
JP2 = VIN
JP3 = VIN
JP4-JP10 = DFT
JP11 = ON
JP12 = ON
2. Set PS1 to 5V, with 5A current limit. Turn on PS1. All
the regulators should come up in a default sequence:
B2 & B3 -> L2 -> B1 & B4 -> L1 & L3
3. The PGOOD LED D2 should stay off, indicating all out-
puts are in regulation. Check the output voltage of all
the regulators, they should read close to the following
values:
VVM1 = 1.2V
VVM2 = 1.5V
VVM3 = 2.48V
VVM4 = 1.81V
VVM5= 1.2V
VVM6= 0.8V
VVM7 = 1.8V
4. Set each electronic load to its corresponding current
level indicated in Figure2. Turn on each load. The
PGOOD LED D2 should stay off, indicating all the out-
puts are still in regulation under loads. Note that if there
are not enough electronic loads for all the regulators,
this test can be done sequentially.
5. Optional:The default input of the three LDOs are from
VIN. To increase the efficiency, the LDOs can be pow-
ered from BUCK3 by configuring JP1-JP3 to V(B3).
They can also be powered from external source by
configuring these jumpers to EXT and connecting an
external supply to the corresponding VIN_LDOX.
6. Optional:The power up sequence can be programmed
by configuring JP4-JP10 to PGM/OFF. Referring to
Power Up Sequence Programming Section shown
in Figure2, connect the SEQ_START (TP21) to the
enable test point of the first regulators to power
up. Then connect the subsequent regulators enable
test points (TP5-TP11) to the corresponding VX_
SEQ (TP14-TP20) according to the desired startup
sequence. If the enable test point of a regulator is not
connected and the jumper is at PGM/OFF position, this
regulator is turned off.

3
DEMO MANUAL DC2984A
Rev. 0
JUMPER DESCRIPTIONS
JUMPER NAME FUNCTION POSITION DESCRIPTION
JP1-JP3 LDOXVIN Input for the LDOs V(B3) Input from BUCK3
EXT Input from external source connected to VIN_LDOXturret
VIN Input from VIN turret
JP4-JP10 BX_SEQ or
LX_SEQ
Power up sequence for the regulators DFT Default power up sequence
PGM/OFF Programmed sequence/Regulator off
JP11 PWR_ON_CTRL Power On master enable and disable
status selection
ON PWR_ON allows enable pin operation
EXT PWR_ON status controlled by external source connected to
PWR_ON turret
OFF PWR_ON inhibits enable pin operation
JP12 PGOOD LED Enable/disable Power Good LED indicator
(indicating output not in regulation)
ON Power Good LED indicator enabled
OFF Power Good LED indicator disabled

4
DEMO MANUAL DC2984A
Rev. 0
PERFORMANCE SUMMARY
Specifications are at TA= 25°C
BUCK2
BUCK1
BUCK3
BUCK4
LOAD CURRENT (A)
0.0
0.5
1.0
1.5
2.0
2.5
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
DC2984A G01
1.5A
100mA
BUCK3
BUCK4
50µs/DIV
I
OUT
1A/DIV
V
OUT
200mV/DIV
V
OUT
200mV/DIV
DC2984A G02
1.5A
100mA
BUCK3
BUCK4
50µs/DIV
I
OUT
1A/DIV
V
OUT
200mV/DIV
V
OUT
200mV/DIV
DC2984A G02
300mA
5mA
LDO1
LDO2
LDO3
50µs/DIV
V
OUT
200mA/DIV
V
OUT
50mV/DIV
V
OUT
50mV/DIV
V
OUT
50mV/DIV
DC2984A G04
500µs/DIV
V
PWR_ON
V
BUCK2
V
BUCK3
V
LDO2
V
BUCK1
V
BUCK4
V
LDO1
V
LDO3
DC2984A G05
BUCK1-BUCK4 Efficiency BUCK1-BUCK2 Load Transient Response
BUCK3-BUCK4 Load Transient Response LDO1-LDO3 Load Transient Response
Default Regulators Power-Up Sequencing

5
DEMO MANUAL DC2984A
Rev. 0
TEST SETUP
+
+
−
−+
−
+
−
+
−
+
+
−
−
+ −
+
−
+
−
+
−
+
−
+
+
+
–
−
−
Figure2. Test Setup for DC2984A Demo Board

6
DEMO MANUAL DC2984A
Rev. 0
OPERATION
Introduction to the DC2984A
The DC2984A a multi-output power management solu-
tion featuring the LT3383. It contains four synchronous
buck regulators and three LDO regulators. Among the
four buck regulators, BUCK1 and BUCK2 deliver up to
2.5A output current, while BUCK3 and BUCK4 deliver
up to 1.5A output current. All three LDOs deliver up to
300mA output current. BUCK1-BUCK4 have default out-
put voltages of 1.2V, 1.5V, 2.48V and 1.81V, respectively.
LDO1 and LDO2 have default output voltages of 1.2V and
0.8V respectively. These voltages are configured by volt-
age dividers on the corresponding FB pins and can be
changed by the user. LDO3 has a fixed voltage of 1.8V.
Power Up Sequencing
The LT3383 regulators can be powered up in any order by
pin-strapping outputs to enable pins. The enable pins have
a 0.75V (typical) input voltage threshold. If any enable is
driven high, the remaining enable input thresholds switch
to an 400mV threshold. There is a built-in 450µs delay
from the enable pin threshold crossing to the internal
enable of the regulator.
The DC2984A has a default power up sequence. User
can also program the power up sequence by selecting
JP4-JP10 to PGM/OFF position and connecting the out-
put rails to the enable pins at the Power Up Sequence
Programming Section shown in Figure2. The start of the
sequence is the rising edge of the PWR_ON pin. PWR_ON
pin can be pulled up to VIN, pulled down to ground, or
connected to an external command source by selection
JP13, PWR_ON_CTRL jumper.
Figure3 illustrates the output voltage of the buck regula-
tors when BUCK1-BUCK4 is programmed to start in an
ascending order. The demo board connection is shown
as follows:
SEQ_START -> EN_B1
VB1_SEQ -> EN_B2
VB2_SEQ -> EN_B3
VB3_SEQ -> EN_B4
Regulator Enables
When JP4-JP10 is at PGM/OFF position, and no connec-
tion is made at the Power Up Sequence Programming
Section, all the regulators are disabled. Each regulator can
be individually enabled by its corresponding enable turret.
LDO Input Selection
The default input of each LDO is the general input of the
demo circuit, VIN. To reduce power loss on the LDOs, the
input source of each LDO can be changed to the output
of BUCK3 by connection corresponding LDO
X
VIN jumper
to V(B3). Each LDO can also be powered externally by
selecting the corresponding LDOXVIN jumper to EXT and
connecting a separate source to VIN_LDOXturret. Note
that the voltage of this external LDO source must not
exceed VIN voltage.
Power Good Indicator
Power Good LED D2 is turned on when PGOOD pin on
LT3383 is pulled low. It indicates one or multiple output
voltages of the enabled regulators are low. It is also on
when no regulator is enabled.
1ms/DIV
V
PWR_ON
5V/DIV
V
BUCK1
2V/DIV
V
BUCK2
2V/DIV
V
BUCK3
2V/DIV
V
BUCK4
2V/DIV
DC2984A F03
Figure3. Program BUCK1-BUCK4 Power Up
Sequence in Ascending Order

7
DEMO MANUAL DC2984A
Rev. 0
PARTS LIST
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
Required Circuit Components
1 5 C1, C8-C11 CAP., 10uF, X5R, 10V, 20%, 0603, AEC-Q200 TAIYO YUDEN, LMK107BBJ106MAHT
2 6 C2-C7 CAP., 1uF, X5R, 25V, 10%, 0402, AEC-Q200 MURATA, GRT155R61E105KE01D
3 4 C12, C15, C17, C19 CAP., 47uF, X5R, 6.3V, 20%, 0805, AEC-Q200 MURATA, GRT21BR60J476ME13L
4 4 C14, C16, C18, C20 CAP., 10pF, C0G, 50V, 5%, 0402, AEC-Q200 MURATA, GCM1555C1H100JA16D
5 2 L1, L2 IND., 0.82UH, POWER, 20%, 14A, DCR 1515,
AEC-Q200
COILCRAFT, XGL4020-821MEC
6 2 L3, L4 IND., 1.5UH, PWR, SHIELDED, 20%, 11.1A,
AEC-Q200
COILCRAFT, XGL4020-152MEC
7 2 Q1, Q2 XSTR., NPN, 40V, 200MA, SOT23-3 ON SEMICONDUCTOR, MMBT3904LT1G
8 1 R1 RES., 102K OHMS, 1%, 1/16W, 0402, AEC-Q200 STACKPOLE ELECTRONICS INC, RMCF0402FT102K
9 6 R2, R4, R6, R9, R13,
R16
RES., 1M OHMS, 1%, 1/16W, 0402, AEC-Q200 STACKPOLE ELECTRONICS INC, RMCF0402FT1M00
10 2 R3, R15 RES., 649K OHMS, 1%, 1/16W, 0402 NIC, NRC04F6493TRF
11 4 R5, R8, R11, R14 RES., 20 OHMS, 1%, 1/16W, 0402, AEC-Q200 NIC, NRC04F20R0TRF
12 1 R7 RES., 665k OHMS, 1%, 1/16W, 0402, AEC-Q200 NIC, NRC04F6653TRF
13 1 R10 RES., 412K OHMS, 1%, 1/16W, 0402 NIC, NRC04F4123TRF
14 1 R12 RES., 1.07M OHMS, 1%, 1/16W, 0402, AEC-Q200 VISHAY, CRCW04021M07FKED
15 9 R18, R20-R26, R63 RES., 10K OHMS, 5%, 1/16W, 0402, AEC-Q200 NIC, NRC04J103TRF
16 1 R31 RES., 1K OHM, 5%, 1/16W, 0402, AEC-Q200 NIC, NRC04J102TRF
17 8 R33-R39, R61 RES., 10K OHMS, 1%, 1/16W, 0402, AEC-Q200 VISHAY, CRCW040210K0FKED
18 7 R40-R46 RES., 10K OHMS, 1%, 1/10W, 0603, AEC-Q200 PANASONIC, ERJ3EKF1002V
19 7 R54-R60 RES., 5.11M OHMS, 1%, 1/10W, 0603, AEC-Q200 VISHAY, CRCW06035M11FKED
20 1 R62 RES., 100K OHMS, 5%, 1/16W, 0402, AEC-Q200 NIC, NRC04J104TRF
21 1 U1 IC, MULTI-OUTPUT POWER, 40QFN ANALOG DEVICES, LT3383EUJM#PBF
Additional Demo Board Circuit Components
1 1 D2 LED, RED, WATER CLEAR, 0603 WURTH ELEKTRONIK, 150060RS75000
Hardware: For Demo Board Only
1 17 E1, E2, E4, E5, E7, E8,
E10-E12, E22-E29
TEST POINT
, TURRET, 0.064" MTG. HOLE, PCB
0.062" THK
MILL-MAX, 2308-2-00-80-00-00-07-0
2 12 E3, E6, E9, E13-E21 CONN., HDR., MALE, 1x4, 2mm, THT, STR SULLINS CONNECTOR SOLUTIONS,
3 4 JP1-JP3, JP13 NRPN041PAEN-RC
4 8 JP4-JP10, JP11 CONN., HDR, MALE, 1x3, 2mm, VERT, STR, THT WURTH ELEKTRONIK, 62000311121
5 4 MP1-MP4 STANDOFF, NYLON, SNAP-ON, 0.25" (6.4mm) KEYSTONE, 8831
6 12 XJP1-XJP7,
XJP9-XJP13
CONN., SHUNT
, FEMALE, 2 POS, 2mm WURTH ELEKTRONIK, 60800213421

8
DEMO MANUAL DC2984A
Rev. 0
SCHEMATIC DIAGRAM
5
5
4
4
3
3
2
2
1
1
D D C C B B A A
1.20V
300mA
ON
NOTES: UNLESS OTHERWISE SPECIFIED - ALL RESISTORS ARE ±1%, 0402 ALL CAPACITORS ARE ±10%, 50V, 0402 ALL INDUCTORS ARE ±20%
0.80V
2.35V - VIN
2.5A
1.50V
1.5A
1.7V - VIN
300mA
LDO3VIN
EXT
OFF
1.20V
2.48V
300mA
VIN
EXT
1.5A
2.5A
1.80V
LDO2VIN
2.7V - 5.5V
VIN
1.81V
EXT
VIN
LDO1VIN
1.7V - VIN
GND
GND GND GND
V (B4)
V (B3)
V (B2)
V (B1)
PGOOD
PWR_ON
EN_B4
EN_B3
EN_B2 EN_B1
EN_L2
EN_L3
VIN
VIN_LDO2
V (LDO2)
VIN_LDO3 V (LDO3)
GND
GND
VIN_LDO1
V (LDO1)
GND
EN_L1
INJ4
INJ3
INJ2 INJ1
PGOOD LED
PGOOD
REVISION HISTORY
APPROVED DATEREVECO DESCRIPTION
OFF
ON
PWR_ON_CTRL
EXT
03 03 PRODUCTION 12-19-19
GND
GND
V(B3)
V(B3)
V(B3)
WL
5A
MULTIOUTPUT POWER MANAGEMENT SOLUTION WITH 4 BUCK
SWITCHING AND 3 LDO LINEAR REGULATORS
VLDO1
VIN
VLDO2 VLDO3
VIN
EN_L1
VBUCK4
VBUCK3
VBUCK2
VBUCK1
EN_B4 EN_B3 EN_B2 EN_B1 EN_L2 EN_L3
VIN VBUCK3
VIN VBUCK3
VIN VBUCK3
PWR_ON
VIN
PWR_ON
DATE:
SHEET OF
TITLE: SCHEMATIC
APPROVALS
PCB DES. APP ENG.
SIZE:
SCHEMATIC NO. AND REVISION:
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
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SKU NO. IC NO.
12
NJC
WL
LT3383
DC2984A
710-DC2984A_REV03
N/A 12-19-19DATE:
SHEET OF
TITLE: SCHEMATIC
APPROVALS
PCB DES. APP ENG.
SIZE:
SCHEMATIC NO. AND REVISION:
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
www.analog.com
SKU NO. IC NO.
12
NJC
WL
LT3383
DC2984A
710-DC2984A_REV03
N/A 12-19-19DATE:
SHEET OF
TITLE: SCHEMATIC
APPROVALS
PCB DES. APP ENG.
SIZE:
SCHEMATIC NO. AND REVISION:
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
www.analog.com
SKU NO. IC NO.
12
NJC
WL
LT3383
DC2984A
710-DC2984A_REV03
N/A 12-19-19
TP1
R26 10k 5%
C13
OPT
0805
E7
R24 10k 5%
E2
L3 1.5uH XGL4020-152MEC
R7 665k
E20
R22 10k 5%
E6
C8 10uF 0603
E5
E26
E17
TP2
R18 10k 5%
JP2
R20 10k 5%
C6 1uF
C17
47uF
0805
20%
E14
C7 1uF
R13
1M
E4
E12 D2
RED
E3
C20
10pF
5%
E24
E9
U1
LT3383-UJM
VIN
27
GND
41
FB_L1
8
SW1 11
GND
26
PVIN1 15
GND
14
GND
12
GND
13
PVIN2 16
FB_B1 23
SW2 20
FB_B2 22
PVIN3 35
SW3 31
FB_B3 25
PVIN4 36
SW4 40
FB_B4 24
EN_B1
17 EN_B2 18 EN_B3 34 EN_B4 37
GND
28
EN_L1
9
VIN_L2
2
EN_L2
30
LDO2
3
FB_L2
1
EN_L3
10
VIN_L3
5
LDO3
4
LDO1
6
GND
38
GND
32
VIN_L1
7
GND
33
PGOOD
39
GND
29
PWR_ON
21
GND
19
R9
1M
E28
E11
JP1
R14 20
L4 1.5uH XGL4020-152MEC
JP12
C2 1uF
E19
C11 10uF 0603
C16
10pF
5%
R11 20
C5 1uF
R25 10k 5%
E22
E29
R6
1M
R31
1k 5%
E16
JP3
C4 1uF
R23 10k 5%
L1 0.82uH XGL4020-821MEC
E27
R15
649k
R8
20
C14
10pF
5%
R3
649k
TP3
C12
47uF
0805
20%
C1 10uF 0603
R5 20
E1
C19
47uF
0805
20%
R10
412k
L2 0.82uH XGL4020-821MEC
R21 10k 5%
C10 10uF 0603
E21
E13 E25
R12
1.07M
R4 1M
C3 1uF
E18
R16
1M
R62 100k
5%
E15
E10
R2
1M
C15
47uF
0805
20%
R63 10k 5%
C9 10uF 0603
R1 102k
E8
C18
10pF
5%
E23
TP4
JP11

9
DEMO MANUAL DC2984A
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
SCHEMATIC DIAGRAM
5
5
4
4
3
3
2
2
1
1
D D C C B B A A
PWR_ON - > B2 &B3 - > L2 - > B1 & B4 - > L1 & L3DEFAULT POWER UP SEQUENCE
DFT
PGM/OFF
DFT DFT DFT DFT DFT DFT
EN_B2
Move JP4-JP10 into the PGM/OFF and connect TP14-TP21 with TP5-TP11 to program the startup sequence.
EN_B3 EN_L2 EN_B4 EN_B1 EN_L3 EN_L1 VL1_SEQ VL2_SEQ VL3_SEQ VB1_SEQ VB2_SEQ VB3_SEQ VB4_SEQ SEQ_START
PGM/OFF PGM/OFF PGM/OFF PGM/OFF PGM/OFF PGM/OFF
B2_SEQ B3_SEQ L2_SEQ B4_SEQ B1_SEQ L3_SEQ L1_SEQ
PCA ADDITIONAL PARTS
SWITCHING AND 3 LDO LINEAR REGULATORS
MULTIOUTPUT POWER MANAGEMENT SOLUTION WITH 4 BUCK
VIN
PWR_ON VBUCK2 VLDO2 VBUCK1
EN_B2 EN_B3 EN_L2 EN_B4 EN_B1 EN_L3 EN_L1
VLDO1 VLDO2 VLDO3 VBUCK1 VBUCK2 VBUCK3 VBUCK4 VINPWR_ON
DATE:
SHEET OF
TITLE: SCHEMATIC
APPROVALS
PCB DES. APP ENG.
SIZE:
SCHEMATIC NO. AND REVISION:
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
www.analog.com
SKU NO. IC NO.
22
NJC
WL
LT3383
DC2984A
710-DC2984A_REV03
N/A 12-19-19DATE:
SHEET OF
TITLE: SCHEMATIC
APPROVALS
PCB DES. APP ENG.
SIZE:
SCHEMATIC NO. AND REVISION:
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
www.analog.com
SKU NO. IC NO.
22
NJC
WL
LT3383
DC2984A
710-DC2984A_REV03
N/A 12-19-19DATE:
SHEET OF
TITLE: SCHEMATIC
APPROVALS
PCB DES. APP ENG.
SIZE:
SCHEMATIC NO. AND REVISION:
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
www.analog.com
SKU NO. IC NO.
22
NJC
WL
LT3383
DC2984A
710-DC2984A_REV03
N/A 12-19-19
MP4 STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm)
R57
5.11M 0603
R59
5.11M
0603
TP9
JP10
13
2
JP6
13
2
TP15 TP20
JP8
13
2
MP1 STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm)
R56 5.11M
0603
R44
10K 0603
TP7
R41
10K 0603
TP18
R36 10k
STNCL1 TOOL, STENCIL, 700-DC2984A REV03
TP14
R38 10k
Q2
MMBT3904LT1G
32
1
JP5
13
2
R45
10K 0603
R55 5.11M
0603
Q1 MMBT3904LT1G
32
1
TP5
R35 10k
TP19
R33 10k
JP4
13
2
TP10
MP3 STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm)
R40 10K 0603
R61
10k
TP8
R46
10K 0603
TP21
R42
10K 0603
LB1 BOARD S/N LABEL
JP7
13
2
R37
10k
JP9
13
2
TP6 TP17
R39 10k
R43
10K 0603
TP11
R34 10k
R58
5.11M 0603
R60 5.11M
0603
PCB1 PCB, DC2984A REV03
MP2 STANDOFF,NYLON,SNAP-ON,0.25" (6.4mm)
R51
OPT R52
OPT
R47 OPT R53
OPT
R48 OPT
TP16
R49 OPT
R50
OPT
R54 5.11M
0603

10
DEMO MANUAL DC2984A
Rev. 0
 ANALOG DEVICES, INC. 2020
05/20
www.analog.com
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions
By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and
conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation
Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”)
and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to
Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and
agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted
is expressly made subject to the following additional limitations:Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board;and (ii) permit any Third
Party to access the Evaluation Board. As used herein, the term “Third Party”includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is
NOT sold to Customer;all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all
be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of
use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile
or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited
to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS
Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF
LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS”AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY
DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS
LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING
BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE
HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States
federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts
(excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits
to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.