Lucent Technologies 5ESS-2000 Quick user guide

5ESS®-2000 Switch
3B21D Computer Hardware Reference Manual
Document: 235-105-510
Issue Date: July 1999
Issue Number: 3.00A
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Legal Notice
Copyright ©1999 Lucent Technologies, Inc. All Rights Reserved.
This electronic information product (IP) is protected by the copyright and trade secret laws of the United States and
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sections may be copied or printed with the utilities provided by the viewer software as set forth in the contract
between the copyright owner and the licensee to facilitate use by the licensee, but further distribution of the data is
prohibited.
For permission to reproduce or distribute, call:
1-888-LTINFO6 (1-888-584-6366) (From inside the continental United States)
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Notice
Every effort was made to ensure that the information in this IP was complete and accurate at the time of publication.
However, information is subject to change.
This IP describes certain hardware, software, features, and capabilities of Lucent Technologies products. This IP is
for information purposes; therefore, caution is advised that this IP may differ from any configuration currently
installed.
Lucent Technologies is the successor to the business and assets of AT&T Network Systems business unit.
Mandatory Customer Information
Interference Information: Part 15 of FCC Rules - Refer to the 5ESS®-2000 Switch Product Specification IP.
Trademarks
5ESS is a registered trademark of Lucent Technologies.
ESS is a trademark of Lucent Technologies.
Fastech is a registered trademark of Berg Technology, Inc.
Gandalf is a registered trademark of Mitel Corporation.
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Warranty
Warranty information applicable to the 5ESS®-2000 switch may be obtained from the Lucent Technologies Account
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Ordering Information
This IP is distributed by the Lucent Technologies Customer Information Center in Indianapolis, Indiana.
The order number for this IP is 235-105-510. To order, call:
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1-888-LUCENT8 (1-888-582-3688) or fax to 1-800-566-9568 (From inside the continental United States)
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Information Product Support Telephone Number: To report errors or ask nontechnical questions about this or
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Customer Technical Assistance Management (CTAM) Center:
1-800-225-4672 (From inside the continental United States)
1-630-224-4672 (From outside the continental United States).
The CTAM center is staffed 24 hours a day, 7 days a week.
Acknowledgment
Developed by Lucent Technologies Customer Training and Information Products.
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1. INTRODUCTION
1.1 PURPOSE
This Hardware Reference Manual describes the 3B21D computer, providing both physical and functional
information. It is part of a documentation set that supports the 3B21D computer. See Section 10 for other Lucent
Technologies documents that support the 3B21D computer.
1.2 UPDATE INFORMATION
Along with other network switching products, the 5ESS®switch product line is being positioned to support Service
Net-2000 (SN-2000). Therefore, the name of the switch has been changed to 5ESS®-2000 switch. However, these
name changes have not been carried forward into software-influenced items, such as input/output messages,
Master Control Center screens, Recent Change/Verify screens, etc.
This manual is reissued to add information about the UN376E and UN597 circuit pac s, and is a complete update
for the 5E13 software release. And Chapter 4 was reorganized into three chapters. (See Section 1.3 DOCUMENT
ORGANIZATION.)
The Lucent Technologies Network Systems organization reserves the right to revise this document for any reason.
The reasons for revision will include, but are not limited to: conformity with standards declared by ANSI, the
Electronic Industrial Association (EIA), International Telecommunications Union-Telecommunications
Standardization Sector (ITU-T), International Telegraph and Telephone Consultative Committee (CCITT),
International Standards Organization (ISO), or similar agencies; advances in the state of the technical arts; or
changes in the requirements of communications systems or equipment.
1.3 DOCUMENT ORGANIZATION
This manual is organized into the following sections and reference information (Table of Contents, Glossary, and
Index). Specific topics are referenced in the "Table of Contents" and in the "Index" with page number locations. The
"Glossary" defines the terms used in this manual.
This manual provides physical and functional descriptions of the 3B21D computer. The remainder of this document
is organized into the following sections:
Section 2 , System Overview
Section 3 , 3B21D Computer Configurations
Section 4 , 3B21D Computer Physical Description
Section 5 , System Overview and Control Unit Functional Description CC
Section 6 , Control Unit Functional Descriptions MAS, MASU, DMA, DSCH, UC, and EX
Section 7 , Peripheral Device Functional Descriptions DFC, IOP, PC, and PSSDB
Section 8 , Storage and Peripheral Devices
Section 9 , Power Distribution and Control
Section 10 , Documentation Roadmap
Section 11 , System Specifications
Section 12 , Connector and Cabling Information
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Glossary
Index.
1.4 USER FEEDBACK
The producers of this manual are constantly striving to improve quality and usability. The user feedback form is
located after the front cover page. Please use it for your comments and to advise us of any errors. If the form is
missing or your comments will not fit, you can write to the following address:
Lucent Technologies
Documentation Services
2400 Reynolda Road
Winston-Salem, NC 27106
Please include the issue number and/or date of the manual, your complete mailing address, and telephone number.
We will answer all correspondence, informing you of the disposition of your comments.
See Support Telephone Numbers on the back of the front cover page of this document.
1.5 DISTRIBUTION
This manual is distributed by the Lucent Technologies Customer Information Center in Indianapolis, Indiana. Most
operating telephone companies should place orders through their documentation coordinator. Some companies may
allow customers to order directly from the Customer Information Center; however, the majority do not. Companies
that use documentation coordinators to manage their orders receive a significant discount.
Customers not represented by a documentation coordinator and Lucent employees can order the documentation for
the 5ESS®-2000 switch directly from the Lucent Technologies Customer Information Center. Proper billing
information must be provided. These orders may be mailed to the following address:
Lucent Technologies Customer Information Center
Order Entry
2855 N. Franklin Road
Indianapolis, IN 46219
See Ordering Information on the back of the front cover page of this document.
1.6 TECHNICAL ASSISTANCE
Technical assistance for the 5ESS®-2000 switch can be obtained by calling the North American Regional Technical
Assistance Center (NARTAC) at 1-800- 5-RTAC. This telephone number is monitored 24 hours a day, 7 days a
week. During regular business hours, your call is answered by your local NARTAC. Outside of normal business
hours, all calls are answered at a centralized Technical Assistance Center where service-affecting problems are
immediately dispatched to your local NARTAC. All other problems are referred to your local NARTAC on the next
regular business day.
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2. SYSTEM OVERVIEW
2.1 GENERAL DESCRIPTION
The 3B21D computer is a high-speed, high-reliability, fault-tolerant, duplex computer. It is a bit-compatible version of
the 3B20D computer, which is used in various roles in Lucent Technologies switching products. All major functional
units are duplicated to ensure uninterrupted and reliable service.
The hardware contains self-checking and error-correction circuitry. The software detects faulty processes and
equipment, reconfigures or reinitializes the system, and diagnoses and identifies faulty equipment.
2.2 APPLICATIONS
The 3B21D computer is used as the administrative module (AM) in the 5ESS®-2000 switch.
2.3 SYSTEM ARCHITECTURE
The high-level architecture of the 3B21D computer is similar to that of the 3B20D computer except for the addition of
Expansion (EX) slots in the 3B21D computer Control Unit (CU) complex, the maximum main store memory
configuration is increased from 64 MB to 128 MB (see Note), and the support of Small Computer System Interface
(SCSI) peripheral devices. The 3B21D computer hardware is packaged differently.
NOTE: The current maximum configuration of the main store memory is 128 MB; however, the system buses and
registers support a 28-bit address to accommodate a future main store memory maximum of 256 MB.
The advantages of the 3B21D computer are reduced floor space and higher reliability because of a reduction in
integrated circuits.
The 3B21D computer hardware consists of the following cabinets:
Basic processor cabinet
Growth cabinet (optional).
Figure 2-1 is a block diagram of the 3B21D computer.
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Figure 2-1 3B21D Computer System Block Diagram
2.3.1 Control Unit (CU)
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Each Control Unit (CU) consists of the following functions:
Central Control (CC)
Cache Storage Unit (CSU)
Main Store (MAS) and Main Store Update (MASU)
Direct Memory Access (DMA 0 and DMA 1)
Expansion Slots (EX 0 and EX 1)
Utility Circuit (UC).
Each Control Unit is half of the duplexed Central Processing Unit (CPU) system. The CC, MAS, UC, EX, and
input/output (I/O) functions are duplicated for reliability. Local control of the 3B21D computer for normal operation
and manual recovery procedures is via the Emergency Action Interface (EAI) to a Maintenance TTY (MTTY) and
Receive-Only Printer (ROP).
2.3.1.1 Central Control (CC)
The 3B21D Central Control (CC) is a microprogram-driven machine modeled after the 3B20D CC. The CC contains
the following functional subsystems:
Circuit pack identification capability
MicroController (MC)
MicroInstruction Store (MIS)
Maintenance Channel (MCH)
Emergency Action Interface (EAI)
Data Manipulation Unit (DMU)
Special Registers (SREGs)
Store Address Interface (SAI)
Store Data Interface (SDI)
Store Address Translator (SAT)
Cache Storage Unit (CSU)
Micro Level Test Set (MLTS) Interface.
2.3.1.2 Expansion Slots (EX 0 and EX 1)
The Expansion (EX) slots provide an interface for new (future) hardware features to access the MAS and CC via the
Central Control Input/Output (CCIO) bus and the Main Store Bus (MASB). Each CU has two EX slots, EX 0 and EX
1.
2.3.1.3 Utility Circuit (UC)
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The Utility Circuit (UC) is an optional function that monitors operations between the CC and the main memory
(cache or main store) for the purpose of program debugging and testing. One UC circuit pack (UN379) is optionally
equipped in each CU.
2.3.1.4 Cache Storage Unit (CSU)
The Cache Storage Unit (CSU) provides a small, high-speed CC cache memory for the most recently accessed
MAS words. The CC accesses the CSU concurrently with the MAS access on the MASB. The CSU is part of the CC
circuit pack (KLW31).
2.3.1.5 Main Store (MAS) and Main Store Update (MASU)
The Main Store (MAS) provides a minimum of 32 MB to a maximum of 256 MBs of Dynamic Random Access
Memory (DRAM). One MAS circuit pack (KLW32, KLW40, KLW48, KLW64, or KLW128) is equipped in each CU.
The same size MAS circuit pack is used in each CU. The KLW32 circuit pack is initially equipped with 32 MB of
DRAM. The KLW40 circuit pack is initially equipped with 40 MB of DRAM. The KLW48 circuit pack is initially
equipped with 48 MB of DRAM. The KLW64 circuit pack is initially equipped with 64 MB of DRAM. The KLW128
circuit pack is initially equipped with 128 MB of DRAM. Additional memory is added to a MAS circuit pack in either 8
MB or 32 MB increments. The addition of three 32-MB Single In-line Memory Modules (SIMMs) to a KLW32 circuit
pack provides a current maximum of 128 MBs of DRAM. Twenty eight bits of address is designed into the system
buses and registers for future expansion to 256 MB. Store data is 36 bits (32 data bits and 4 parity bits). However, in
the MAS circuit pack, store data is 39 bits wide (32 data bits and 7 parity/check bits). The MASs in both CUs are
kept coherent using the Update Bus. If control must be switched from the on-line processor to the other processor,
the contents of both the off-line memory and the on-line memory must be identical. If the MASs are not coherent, the
on-line processor must copy its data to the off-line MAS before the switch takes place.
2.3.1.6 Direct Memory Access (DMA)
The Direct Memory Access (DMA) provides peripheral devices access to the MAS via the MASB and provides the
CC access to the peripheral devices through the CCIO bus. Each DMA supports connections for a maximum of 16
peripheral devices.
Peripheral devices are connected to the DMA through the Dual Serial Channel (DSCH). These devices have a
dual-ported DSCH interface that allows them to communicate with either CU 0 or CU 1. Two DMA circuit packs
(KBN15s) can be equipped in each CU. DMA 0 is standard and DMA 1 is optional.
The relationship of peripheral devices to DMA 0 and DMA 1 is as follows:
DMA 0 and DMA 1 each provide four channels. DMA 0 supports channels 11, 12, 13, and 14. DMA 1 supports
channels 16, 17, 18, and 19.
Each channel supports four DSCH interfaces.
2.3.2 Peripheral Devices
Figure 2-1 shows three types of peripheral devices:
Input/Output Processor (IOP)
Disk File Controller (DFC)
Communications Module/Communications Network Interface (CM/CNI).
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The IOP provides connections to terminals, networks, and some tape devices. The DFC provides connection to
peripherals with SCSI interfaces, which include disk and tape drives. The third device, CM/CNI, represents
application peripheral hardware. The term "DFC" is not accurate since support is not limited to disk peripherals;
however, the nomenclature is retained from the 3B20D computer.
Note that the 3B21D computer differs from the 3B20D computer in that 9-track tape is an SCSI peripheral device
supported by the DFC in the 3B21D computer while it is supported by the IOP in the 3B20D computer. Also note that
3B21D computer DFC channel and device allocations differ from the 3B20D computer in that there are fewer
devices per channel.
2.3.2.1 DFC Equipped with UN373 and TN2116
The 3B21D computer can have three DFCs (DFC 0 through DFC 2). DFC 0 is equipped in the Processor Cabinet,
Processor Unit 0 at EQuipment Location (EQL) 28-170 and EQL 28-178. DFC 1 is equipped in the Processor
Cabinet, Processor Unit 1 at EQL 53-170 and EQL 53-178. DFC 2 is equipped in the Processor Cabinet, Growth
Unit at EQL 11-172 and EQL 11-180. Each DFC provides two SCSI buses (SBUS A and SBUS B). A maximum of
seven SCSI peripheral devices can be equipped on an SCSI bus. Therefore, each DFC can support a maximum of
14 SCSI devices. DFC 0 provides two SCSI buses, SBUS 0(A) and SBUS 2(B). DFC 1 provides two SCSI buses,
SBUS 1(A) and SBUS 3(B). DFC 2 provides two SCSI buses, SBUS 4(A) AND SBUS 6(B).
2.3.2.2 DFC Equipped with UN580
The 3B21D computer can have three DFCs (DFC 0 through DFC 2). DFC 0 is equipped in the Processor Cabinet,
Processor Unit 0 at EQL 28-178. DFC 1 is equipped in the Processor Cabinet, Processor Unit 1 at EQL 53-178.
DFC 2 is equipped in the Processor Cabinet, Growth Unit at EQL 11-180. Each DFC provides two SCSI buses
(SBUS A and SBUS B). A maximum of seven SCSI peripheral devices can be equipped on an SCSI bus. Therefore,
each DFC can support a maximum of 14 SCSI devices. DFC 0 provides two SCSI buses, SBUS 0(A) and SBUS
2(B). DFC 1 provides two SCSI buses, SBUS 1(A) and SBUS 3(B). DFC 2 provides two SCSI buses, SBUS 4(A)
and SBUS 6(B).
2.3.2.3 Input/Output Processor (IOP)
The 3B21D computer can have four IOPs (IOP 0 through IOP 3) equipped in the Processor Cabinet. IOP 0 is
equipped in Processor Unit 0 at EQL 19-065. IOP 1 is equipped in Processor Unit 1 at EQL 45-065. IOP 2 is
equipped in the Growth Unit at EQL 11-011. IOP 3 is equipped in the Growth Unit at EQL 62-011.
Functionally, an IOP can support four peripheral controller communities with each community supporting four
peripheral controllers. Therefore, 16 peripheral devices can be supported by an IOP. IOP 0 and IOP 1 are
exceptions. IOP 0 and IOP 1 each support up to 15 Peripheral Controller (PC) slots. IOP 2 and IOP 3 each support
up to 16 PC slots. The maximum number of available PC slots in a Processor Unit is 15; the maximum number of
available PC slots in a Growth Unit is 16.
For IOP 0 and IOP 1, peripheral community 0, slot 0 (PC00) is always equipped with a TN983, UN583, or UN597
MTTY Controller (MTTYC) circuit pack. Also, IOP 0 and IOP 1, peripheral community 0, slot 2 (PC02) is reserved for
a UN33D or UN933 Scanner and Signal Distributor circuit pack, which provides scan and signal distributor point
interfaces for the 3B21D computer.
2.3.3 Port Switch and Scanner-Distributor Buffer (PSSDB)
The Port Switch and Scanner-Distributor Buffer (PSSDB) switches the MTTY and the local receive-only printer
(ROP) between the MTTY Controller (MTTYC) circuit pack (TN983, UN583, or UN597) in IOP 0 and IOP 1. The
PSSDB also buffers the scanner and signal-distributor controller from non-3B21D computer circuits such as office
alarms, smoke detectors, and security monitoring devices. One port switch is equipped in Processor Unit 1. In the
3B21D computer, the PSSBD is located in CU 1. (Note that in the 3B20D computer, the PSSBD is located in CU 0.)
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2.4 HARDWARE FEATURES
2.4.1 Reduced Floor Space
For Release 1, the 3B21D computer system is packaged in one, two, or three cabinets. The Processor Cabinet
(J3T060A-1) is always required. One or two Peripheral Growth Cabinets (J3T059A-1) are provided as necessary
when 9-track SCSI tape drives are required as part of the configuration. The Peripheral Growth Cabinets are always
located to the right of the Processor Cabinet.
Each cabinet measures about 72 inches (183 cm) high by 30 inches (76 cm) wide by 24 inches (60 cm) deep. A
three-cabinet lineup occupies an area about 90 inches (229 cm) wide by 24 inches (60 cm) deep.
2.4.2 Application Specific Integrated Circuit (ASIC) Technology and Packaging
The 3B21D computer uses Complementary Metal Oxide Semiconductor (CMOS) Gate Array Technology in the form
for Application Specific Integrated Circuits (ASICs). The ASICs are fabricated in a one-micron, two- or three-layer,
metal process.
All 3B21D computer gate arrays are in surface-mounted packages. The largest package is a 240-pin Plastic Quad
Flat Pack (PQFP). Plastic-Leaded Chip Carriers (PLCCs) are used for ASICs requiring 100 or fewer pins. Table 2-1
summarizes the 3B21D computer ASIC surface-mounted packages.
Table 2-1 3B21D Computer ASIC Summary
ASIC NAME PACKAGE
CENTRAL CONTROL CIRCUIT PACK (KLW31/KLWCC)
Cache Controller (CAC) 160 PQFP
Data Manipulation Unit (DMU) 240 PQFP
Maintenance Channel (MCH) 240 PQFP
MicroSequencer (MSEQ) 240 PQFP
Special Registers (SREGs) a 240 PQFP
Store Address Interface (SAI) b 240 PQFP
Store Address Translator (SAT) 240 PQFP
Store Data Interface (SDI) b 240 PQFP
MAIN MEMORY CIRCUIT PACK (KLW32/KLWMM)
Memory Controller with Error Regulation and Test (MCERT2) c 160 PQFP
DIRECT MEMORY ACCESS CIRCUIT PACK (KBN15/KBNDMA)
Direct Memory Access Controller (DMAC) 240 PQFP
INPUT/OUTPUT PROCESSOR 2 CIRCUIT PACK (KBN10/KBNIOP)
Duplex Dual Serial Bus Selector/Bus Interface Controller (DDSBS/BIC) 120 PQFP
Input/Output Microprocessor Interface (IOMI) 160 PQFP
Peripheral Interface Controller/Sequencer (PIC/SEQ) 160 PQFP
DISK FILE CONTROLLER CIRCUIT PACK (UN373/DFCA)
Duplex Dual Serial Bus Selector (DDSBS) 208 PQFP
Notes:
a. Two SREGs are used, SREG0 (Bits 15-00) and SREG1 (Bits 31-16).
b. Two Store Interfaces are used for the SAI and SDI function.
c. Modification of existing 0.9 CMOS code.
2.4.3 Circuit Pack Types
The functional blocks shown in Figure 2-1 are physically represented by the following circuit pack designs:
410AA DC-to-DC converter circuit pack provides +5 V DC from -48 V DC.
KBN10 Input/Output Processor (IOP) circuit pack contains the DSCH and IOMI interface functions.
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KBN15
Direct Memory Access (DMA) circuit pack contains the DMAC and Channel functions.
KLW31 Central Control (CC) circuit pack contains the CC and Cache Storage Unit (CSU) functions.
KLW32, KLW40, KLW48, KLW64, or KLW128 The Main Memory (MM) circuit pack contains the MAS and Update
functions. The KLW32 is initially equipped with 32 MB; KLW40 is initially equipped with 40 MB;
KLW48 is initially equipped with 48 MB; KLW64 is initially equipped with 64 MB; KLW128 is
initially equipped with 128 MB.
KLW__ The Expansion (EX) circuit pack is for future development.
TN74B Terminal Controller circuit pack.
TN75C Synchronous Data Link Controller circuit pack.
TN82B X.25 Synchronous Data Link Controller circuit pack.
TN983 Maintenance TTY Controller circuit pack.
TN1420 Synchronous Data Link Controller circuit pack.
TN1820 Input/Output Processor Power Switch (IOPPS) circuit pack is similar to the TN1821 circuit pack
with additional onboard DC-to-DC (12 V and -5 V) power converters.
TN1821 Control Unit Power Switch (CUPS) circuit pack contains power and control for the Central
Control fault group.
TN1839 Synchronous Link Peripheral ControllerX.25 Network Level 2 Interface (NET2) circuit pack.
TN2116 and UN373 Disk File Controller A (UN373) and Disk File Controller B (TN2116) circuit packs contain the
DSCH interface and SCSI host adapter functions.
UN33 Scanner and Signal Distributor circuit pack.
UN375 SCSI Disk circuit pack contains a 3.5-inch SCSI Moving Head Disk (MHD) drive, power
converters for the drive, and power control. This circuit pack provides the MHD functions for the
AM. On the UN375E series, an MHD with a single-ended SCSI interface is used. The UN375E
series requires the addition of a differential-to-single-ended translation circuit.
UN376 SCSI Tape circuit pack contains a 3.5-inch SCSI Digital Audio Tape (DAT) drive, power
converters for the drive, and power control.
UN377 Port Switch and Scanner-Distributor Buffer (PSSDB) circuit pack contains the PSSDB function.
UN379 Utility Circuit circuit pack contains the utility circuit function.
UN580 Disk File Controller circuit pack combines the functionality of TN2116 and UN373 into one
circuit pack. The UN580B does not use an external power converter.
UN582 The UN582 circuit pack is a Synchronous Data Link, High-Speed Synchronous Data Link, and
an Asynchronous Data Link Peripheral Controller that replaces the TN82B, TN74B, TN75C, and
TN1839 circuit packs.
UN583 Maintenance TTY Controller circuit pack that replaces the TN983.
UN597 Maintenance TTY Controller circuit pack that replaces the UN583.
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UN933 New Scanner and Signal Distributor circuit pack that replaces the UN33 with identical
functionality.
2.4.4 Configurability and Growth
The 3B21D computer system offers cost-effective configurations for small switching offices and can be grown from
a small office configuration to a large office configuration. The minimum configuration is packaged in one Processor
Cabinet. The maximum Release 1 configuration is packaged in one Processor Cabinet and two Peripheral Growth
Cabinets.
See Section 3 for a description of the 3B21D computer configuration and growth information.
The 3B21D computer is configured for manufacturability and orderability in J3T061A-1.
2.5 RELIABILITY AND MAINTENANCE FEATURES
The 3B21D computer is more reliable than the 3B20D computer because of a reduction in the number of integrated
circuits, circuit packs, backplanes, and cables. This reduction in the number of components and interconnections is
the result of extensive use of Application Specific Integrated Circuits (ASICs).
The 3B21D computer makes use of the following features that contribute to the reliability and maintainability of the
system:
Control Units are duplexed.
The standby memory is kept current via memory update.
Maintenance exercise routines are run on the standby Control Unit.
Various system sanity mechanisms with subsequent automatic recovery are used.
Duplexed circuitry with matchers is used in addition to parity checking.
Error detection and correction is used on main memory.
Standard equipment designation strips for power and circuit pack labeling.
Forced air cooling is used to keep components within their rated temperature ranges.
The 3B21D computer system is factory assembled and is following environmental stress ESSTM switch
screening to increase product reliability.
Except for the PC community circuit pack slots, all circuit pack slots are keyed to prevent the installation of a
wrong circuit pack. The PC community slots are keyed to accept the installation of several different circuit pack
types.
Cabling design follows specific rules to enhance the reliability and maintainability of the system as follows:
All cables are stamped with the appropriate cable EQuipment Location (EQL) information.
Total cable length for a differential SCSI bus is 20 meters (65.6 feet), because of internal circuit limits.
2.5.1 Fault Detection
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Fault detection algorithms make extensive use of local matching circuits, parity techniques on all buses, and
hamming detection with single-bit error correction on the main store. Technology-dependent fault
detection/correction strategies on disks, and numerous sanity timers throughout the control unit and peripherals are
used as the primary fault-detection techniques. In addition, routine diagnostics are used to detect failures in the
fault-detection hardware itself. Finally, system integrity checks catch certain subtle problems that are not caught by
unique detectors.
When any of the unique detectors determine an error condition, an error interrupt (or error report in the case of
certain peripherals) is registered in the processor. The most severe of these will result in automatic hardware
sequences that switch the activity of the processors (hard switch). Less severe errors result in microinterrupts that
enter microcode and software charged with recovery of the system.
2.5.1.1 Bus Parity
Self-checking is made possible by carrying a parity check bit per byte in the processor. Since each microinstruction
may involve a data transfer from one register to another via a common data bus, an effective parity check is done by
trapping the data off the bus and checking for correct parity during the next clock interval (that is, the source bus
parity error). This avoids added delay in the normal operation. The data in the destination register is not checked.
However, when used as the source, the data is then checked. For any arithmetic or logical operations, the data goes
through the DMU. The DMU is divided into two parts (DMU 0 and DMU 1) for checking purposes. The results from
one is used as data, whereas parity check bits derived from the result of the second is used with the data. As data
leaves the DMU, the common bus parity check is performed [that is, the Data Manipulation Unit (DMU) parity error].
In the microprogram store, additional bits are provided to check the control section of the processor (that is, the
microcontrol parity error).
2.5.1.2 Dynamic RAM Error Detection and Correction
The Main Memory (MM) detects and corrects one-bit errors. All data is checked when read. All data is continually
checked during refresh cycles. In a systematic way, all memory locations are checked over a time period dependent
on the amount of memory equipped. The MM detects most multiple bit errors (two-bit and greater errors). Both
classes of errors are recorded in the Error Register (ER) and generate a microinterrupt. Registers in the MM are
accessible via software to assist in fault recovery.
2.5.2 Fault Recovery
The microcode and recovery software provides a layered approach to the recovery architecture. Fault-recovery
strategies are based on the fault-tolerant architecture of the 3B20D computer. Major hardware units are fully
duplicated. This duplication provides a high probability that a combination of operational units can be retained in the
face of faults. The mate processors are only loosely coupled; interprocessor connections are limited to the
maintenance channel and memory update circuitry. This architecture forms the foundation of the hardware recovery
strategy used in the 3B21D computer, namely to isolate an entire faulty processor as opposed to attempting fault
resolution at the subunit level.
The UNIX®Real-Time Reliable (RTR) system is a modular operating system that provides a wide range of
protection from various types of classical errors. Examples include write-protected memory areas, memory ranges
that are used only for text execution, and protected virtual address spaces. Thus, much of the recovery from these
types of errors is built into the operating system. Recovery actions that are required are greatly simplified by the
underlying architecture. Hard faults and other conditions requiring recovery actions are treated according to their
severity. Fault categories that are described individually are: hard faults, Sanity Timer time-out, software-requested
recovery, and threshold-exceeded faults.
Different types of faults can result in different actions. The most severe action taken is a system initialization or boot.
The boot sequence is discussed later in this section.
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2.5.2.1 Hard Faults
The 3B21D computer has built-in self-checking circuitry designed to detect hard faults as soon as they occur. This
circuitry simplifies recovery since early fault detection limits the possible damage done by the fault. Faults in this
category indicate that the processor is no longer capable of proper operation and results in an immediate stop of the
currently running processor and a switch to the other processor (stop-and-switch). Since the other processor does
not match the active processor instruction by instruction, an initialization sequence is required to start execution
properly.
2.5.2.2 Sanity Timer Timeout
Each processor has a Sanity Timer (ST) that will result in an initialization if it times out and is not inhibited (disable
Sanity Timer request). The System Integrity Monitor process in the active processor maintains both its own and the
standby ST so that if the active processor is out of control, an initialization of the standby processor will be triggered
by a Sanity Timer time-out.
2.5.2.3 Software-Requested Recovery
The system provides an Operating System Trap (OST) for use by software to request an initialization. This capability
is used by critical system processes when they encounter errors that preclude performance of a critical system
function. Initializations occur when an error or fault has been detected that cannot be recovered without a change in
hardware and/or software status. A stop-and-switch to the other processor may or may not be associated with any
given initialization. All initializations include actions of varying severity, depending on what is required to deal with
various faults and errors.
2.5.2.4 Other Fault Sources
Some types of faults and errors are not severe enough to justify an immediate stop-and-switch recovery action.
Examples of errors of this kind are hardware faults, which are detected in the standby processor memory, and
software errors, such as write-protection violations. Another type of error in this category is hardware faults that are
handled by self-correcting circuitry. Although most faults are detected by self-checking, some units, such as main
memories, have fault rates that justify self-correcting capabilities. Disks are also self-correcting via cyclic
redundancy codes. All errors in this class are reported to the recovery system as error interrupts.
Recovery software classifies the interrupt by type, gathers and saves all available information about the interrupt,
and reports the error to the system configuration management package. If a particular software process is
suspected as the cause of the interrupt, such as in a software-triggered event, the process that was running at the
time of the interrupt is faulted and entered at its fault entry after a stable system configuration is guaranteed. The
fault entry of a process contains recovery and initialization sequences that are special to the process involved.
2.5.2.5 Threshold-Exceeded Faults
All error interrupts are reported to configuration management. Errors are logged against the failing unit and error
rates are compared to allowed error thresholds. If the affected threshold is exceeded, further action is required and
is based on several factors. If the faulty unit is essential to the system and a mate unit is available, the faulty unit will
be removed from service and scheduled for diagnostic testing. If there is no available mate unit, the faulty unit will be
initialized and returned to service since, in the case of essential units, it is better to have a faulty unit than no unit.
Nonessential units are removed and scheduled for diagnostic testing whenever their error thresholds are exceeded.
2.5.2.6 Boot Sequence
The following simplified description of the UNIX®RTR system boot sequence addresses the actions taken by the
hardware, micro-code, and system software during and after a boot.
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2.5.2.6.1 Hardware Actions
The first event in a hardware-initiated or manual initialization sequence is a hardware-supported transfer to a fixed
location [Maintenance Reset Function (MRF)] in the CU microstore. Software-requested initializations begin
executing at MRF without hardware assistance.
2.5.2.6.2 Microcode Actions
Data about the initialization trigger is first saved in temporary registers and later copied to Main Store. A decision is
made to bring this processor on-line or stop for the off-line initialization. If the current initialization is level two or
higher, the writable microstore, appropriate processes, and databases are loaded from the mass-storage device
(disk or tape). These and other boot time decisions that are made are supported by the System Status Register
(SSR).
2.5.2.6.3 System Software Actions
The UNIX®RTR system kernel initialization or bootstrap routine is then called to restart system processes or to fault
active processes as appropriate. The initialization is now complete and the system has returned to normal operation.
2.5.2.6.4 Reboot
If an initialization does not recover the system to an operational state, another and more severe initialization will
occur. Any initialization that occurs during a window of time following the previous initialization will escalate to the
next higher level. The length of the initialization interval is a system-generation parameter that is established by the
application.
In addition to the UNIX®RTR system-initialization levels, provision is made for an application to specify
software-controlled "application levels."
2.5.2.6.5 Post-Recovery Actions
Data about various recovery actions taken by the system is supplied to provide much information about what went
wrong. This information can be used by maintenance personnel to assist them in isolating difficult faults. Recovery
data is provided in several forms. Each error interrupt is accompanied by a printout containing available information
about the state of the processor when the interrupt occurred. A more difficult problem is presented by initializations.
Since they are more severe than interrupts and represent a discontinuity in processing, gathering and preserving
error data is more difficult. Initializations, as well as interrupts, can occur at a rate much too fast for data to be
printed. The solution is to save all pertinent data in a protected area of memory for printing after the system has
recovered.
Various kinds of error data are not generally printed as a part of the standard system output but instead are saved in
error files on the system disks. Examples of this data are device driver errors and failing memory data.
One piece of data output by the system that is not saved in error files are the Processor Recovery Messages
(PRMs). These are low-level one-line messages that are printed in real time. The PRMs thus represent progress
marks through the recovery sequences and are extremely useful in those cases where stability cannot be achieved
or postmortem data cannot be gathered.
2.5.3 Maintainability and Craft Interface
The maintainability of the 3B21D computer is a vital component that guarantees the overall high availability required
of the system. There are conditions where automatic recovery is unable to restore the system to a fully-functioning
state. This is where maintainability is critical to satisfying UNIX®RTR system's high availability requirements. The
hardware requirements imposed by the maintainability needs are not as obvious as those prescribed by other
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portions of the system. This section describes the maintenance capabilities provided by UNIX®RTR system. The
3B21D computer hardware has been designed to ease in the implementation of these features.
2.5.3.1 Maintainability Overview
The basic premise of maintainability is to provide basic data-gathering and data-analysis mechanisms as well as the
ability to act on the results of that analysis. These mechanisms must be able to collect and analyze diagnostic and
debugging information from various hardware and software components in the system to isolate the error. These
mechanisms must then allow the craft to control and modify the configuration of the system based on the diagnostic
and debugging information collected. Furthermore, these mechanisms must yield their information as quickly as
possible while disturbing the rest of the system as little as possible.
Maintainability includes such areas as diagnostics, transient error analysis, routine maintenance procedures, field
utilities, and plant measurements. Once an error has been isolated and analyzed, the problem must then be
corrected as quickly and benignly as possible. This is termed updatability, and includes such aspects as growth and
retrofit for hardware, emergency fixes, function update, and system update for software. Maintainability is partitioned
into diagnostics (hardware) and the various field utilities (software). However, the craft interface to the various
maintenance facilities in the system is central to the craft's ability to maintain and control the 3B21D computer
hardware and software. This is an important capability of the craft interface system. The craft interface provides the
craft and others with the means to request diagnostics, receive error analysis reports, initiate emergency recovery
procedures, gather plant measurements data, and exercise routine maintenance programs. In addition, the craft
interface system allows configuration control by providing access to growth and retrofit procedures, system and
function update capabilities, emergency fix facilities, and the various field utilities.
2.5.3.2 System Updatability
One component of the maintainability required of UNIX®RTR-based systems is the ability of these systems to
accept hardware and software changes in a way that does not interfere with their primary tasks. In other words, a
UNIX®RTR-based system must be able to accept changes without disturbing call processing, networking, or other
critical functions. UNIX®RTR system supports this through the following aspects of updatability: growth, retrofit,
software update, and program update.
2.5.3.2.1 Growth
The first aspect of updatability is growth. Growth is the ability to add or remove hardware and related software
components to the running system. Growth extends from physically connecting new equipment (such as memory
boards, disks drives, tape drives, and other units) through informing the system of its existence, exercising it,
logically connecting it into the system's configuration, and committing to its use in the system. Other subsystems,
such as hardware and software fault recovery and diagnostics, then take over to ensure that the new system
component continues to be sane and usable.
2.5.3.2.2 Retrofit
The second aspect of updatability is retrofit. Retrofit is the ability to replace hardware components in the system with
similar components of a different vintage or with different capabilities or interface characteristics. Retrofit procedures
may remove (de-grow) old units and then grow or add new ones. They also may add the new units first and then
transition work from the old units to the new. Thus, retrofit of units may involve extensive periods of time where old
and new units coexist in the system. Retrofit may also involve substantial software changes to interact with new
units and to recognize the existence of both old and new units.
2.5.3.2.3 Software Update
The third component of updatability, software update, deals exclusively with software and data file changes in the
UNIX®RTR system. Such changes are done logically, on a file-by-file or functional level. Just as with growth and
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retrofit, software update can install new or replace system programs or files, inform the system about them, logically
connect them into the system, exercise them in that state, and then commit to or back out of them. Software update
is intended primarily for installing fixes or small features that do not disturb the system's architecture.
2.5.3.2.4 Program Update
The fourth updatability component, program update, allows program and data changes of much greater magnitude,
up to complete software program replacement. A bootstrap is required to install the changes for any program
update. By using disk redundancy or backup copies of sections of UNIX®RTR program disks, program update can
prepare a new, partial, or total version of the program on disk and then switch to it (and back, if necessary). Where
software update performs a logical change of files, program update does a physical change of a set of partitions (file
systems and/or file partitions).
2.5.4 Improved Diagnostics
The 3B21D computer diagnostic system follows a systematic approach for isolating hardware failures and provides
a suspect pack list to the user. For each circuit pack or unit, the diagnostic software does the following:
(1) Runs the self-test of the Boundary Scan Master (BSM) chip if the chip is used on the circuit pack.
(2) Runs the boundary-scan integrity test followed by the boundary-scan interconnect test.
(3) Instructs all the ASICs on the unit under test to run their internal device level Built-In Self Test (BIST) and
analyze their results.
(4) Runs functional tests on non-BIST units.
System diagnostics are organized on a unit basis. Unit diagnostics are structured in subunit test phases. Test
phases are executed to first test the most elementary operations, and then proceed to the more detailed subunit
operations.
All diagnostic programs avoid interference with the normal system functions. Special driver functions handle error
conditions generated by the diagnostic tests, thus avoiding the normal error handling routines.
The diagnostic system also provides maintenance personnel with interactive diagnostic commands. These can be
used to do the following:
Run a single or range of diagnostic phases.
Repeat a single or range of diagnostic phases.
Run a diagnostic up to a specified point in the data table and then stop.
Repeatedly perform a specified group of tests within a phase.
Provide optional parameters to main store diagnostics.
Step through diagnostic data table commands.
See 235-600-700, Input Message Manual, and 235-105-220, Corrective Maintenance Procedures.
2.5.4.1 Boundary Scan Architecture
The 3B21D computer hardware uses Built-In Self Test (BIST) and Boundary Scan (BS) features at the circuit pack
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and ASIC device levels to reduce the testing difficulties and increase fault coverage. Additional circuits have been
incorporated in the 3B21D computer hardware design to provide BS cells adjacent to each chip's input/output pins to
control and observe the signals. BS cells are like test points that are interconnected as shift register chains. A
separate BS bus is used to assess and control the BS cells.
Boundary scan cells can be operated in either a normal or test mode. In the test mode, the BS cells can accept test
instructions and data, and scan out the test responses. They are used to perform interconnection tests or internal
tests (BIST).
Software diagnosis is performed on the off-line processor complex through the maintenance channel. The
maintenance channel connects the active and the standby processors. The diagnosis is initiated from the active
processor. Diagnostic commands issued by the active processor are passed via the maintenance channel link.
These commands are then received, interpreted, and reissued to the Boundary Scan Master (BSM) device through
the Generic Processor Interface (GPI) by the Maintenance Channel (MCH).
2.5.4.2 Built-In Diagnostics
The inclusion of on-chip circuitry to provide test vectors or to analyze output responses is called Built-In Self Test
(BIST). The BIST reduces the complexity and cost of an external tester by including some or all tester functions in
the chip itself.
The use of BIST and Boundary Scan (BS) provides a higher percentage of fault coverage. The BIST and BS
hardware is accessed via diagnostic software that executes the ASIC BIST test and the circuit pack BS test.
2.5.5 Auto Restart
The 3B21D computer system hardware is designed to automatically restart following a power interruption. To
support this feature, the 3B21D computer unit power switches must be in the ON position. The unit power switch ON
position allows auto-restart when power is applied to the unit. This feature provides for unattended system
operation. The Auto Restart feature is available in RTR Release 21.5 and later.
2.5.6 Fault Isolation and Repair
The 3B21D computer design enables fault isolation to a circuit pack level. This is accomplished by the following:
ASIC technology, which places complete functions on one circuit pack, making it easier to isolate a fault though
functional testing.
Built-In Self Test (BIST), which allows a more thorough test at the ASIC and circuit pack level.
2.5.7 Hot Card Replacement
CAUTION: All circuit packs must be removed and installed with the power OFF. The "hot card" replacement of
circuit packs is not supported.
Before a 3B21D circuit pack is removed or installed in an apparatus housing, the power to the circuit pack must be
removed. However, the SCSI peripherals can be installed without powering down the associated SCSI bus. The
DFC, PSSDB, and SCSI peripheral circuit packs have their own board-mounted power converters and power
switches. This is equivalent to a "hot card" replacement, because the other units on the SCSI bus are not affected.
NOTE: The SCSI bus must be removed when installing a disk.
See 235-105-110, System Maintenance Requirements and Tools, for more information about spare pack handling,
circuit pack removal, and installation.
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