Microchip Technology PIC18LF67K40 User manual

2016 Microchip Technology Inc. Preliminary DS40001841B-page 1
PIC18(L)F67K40
Description
PIC18(L)F67K40 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals,
combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications.
These 64-pin devices are equipped with a 10-bit ADC with Computation (ADCC) automating Capacitive Voltage Divider
(CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and performing automatic threshold
comparisons. They also offer a set of Core Independent Peripherals such as Complementary Waveform Generator
(CWG), Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/Memory Scan, Zero-Cross Detect
(ZCD) and Peripheral Pin Select (PPS), providing for increased design flexibility and lower system cost.
Core Features
• C Compiler Optimized RISC Architecture
• Only 83 Instructions
• Operating Speed:
- DC – 64 MHz clock input
- 62.5 ns minimum instruction cycle
• Programmable 2-Level Interrupt Priority
• 31-Level Deep Hardware Stack
• Four 8-Bit Timers (TMR2/4/6/8) with Hardware
Limit Timer (HLT)
• Five 16-Bit Timers (TMR0/1/3/5/7)
• Low-Current Power-on Reset (POR)
• Power-up Timer (PWRT)
• Brown-out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Programmable Code Protection
• Windowed Watchdog Timer (WWDT):
- Timer monitoring of overflow and underflow
events
- Variable prescaler selection
- Variable window size selection
- All sources configurable in hardware or
software
Memory
• 128K bytes Program Flash Memory
• 3568 Bytes Data SRAM Memory
• 1024 Bytes Data EEPROM
• Direct, Indirect and Relative Addressing modes
Operating Characteristics
• Operating Voltage Ranges:
- 1.8V to 3.6V (PIC18LF6xK40)
- 2.3V to 5.5V (PIC18F6xK40)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
Power-Saving Operation Modes
• Doze: CPU and Peripherals Running at Different
Cycle Rates (typically CPU is lower)
• Idle: CPU Halted While Peripherals Operate
• Sleep: Lowest Power Consumption
• Peripheral Module Disable (PMD):
- Ability to selectively disable hardware module
to minimize active power consumption of
unused peripherals
eXtreme Low-Power (XLP) Features
• Sleep mode: 50 nA @ 1.8V, typical
• Windowed Watchdog Timer: 500 nA @ 1.8V,
typical
• Secondary Oscillator: 500 nA @ 32 kHz
• Operating Current:
- 8 uA @ 32 kHz, 1.8V, typical
- 32 uA/MHz @ 1.8V, typical
Digital Peripherals
• Complementary Waveform Generator (CWG):
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
• Capture/Compare/PWM (CCP) modules:
- Five CCPs
- 16-bit resolution for Capture/Compare modes
- 10-bit resolution for PWM mode
• 10-Bit Pulse-Width Modulators (PWM):
-Two10-bitPWMs
• Serial Communications:
- Five Enhanced USART (EUSART) with
Auto-Baud Detect, Auto-wake-up on Start.
RS-232, RS-485, LIN compatible
- SPI
-I
2C, SMBus and PMBus™ compatible
• 59 I/O Pins and One Input Pin:
- Individually programmable pull-ups
- Slew rate control
- Interrupt-on-change
- Input level selection control
64-Pin, Low-Power, High-Performance Microcontrollers
with XLP Technology
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2016 Microchip Technology Inc. Preliminary DS40001841B-page 2
PIC18(L)F67K40
Digital Peripherals (Continued)
• Programmable CRC with Memory Scan:
- Reliable data/program memory monitoring for
Fail-Safe operation (e.g., Class B)
- Calculate CRC over any portion of Flash or
EEPROM
- High-speed or background operation
• Hardware Limit Timer (TMR2/4/6/8+HLT):
- Hardware monitoring and Fault detection
• Peripheral Pin Select (PPS):
- Enables pin mapping of digital I/O
• Data Signal Modulator (DSM)
• Two Signal Measurement Timer (SMT1/2):
- 24-bit timer/counter with prescaler
- Multiple gate and clock inputs
Analog Peripherals
• 10-Bit Analog-to-Digital Converter with Computa-
tion (ADC2):
- 47 external channels
- Conversion available during Sleep
- Four internal analog channels
- Internal and external trigger options
- Automated math functions on input signals:
- averaging, filter calculations, oversam-
pling and threshold comparison
• Hardware Capacitive Voltage Divider (CVD)
Support:
- 8-bit precharge timer
- Adjustable sample and hold capacitor array
- Guard ring digital output drive
• Zero-Cross Detect (ZCD):
- Detect when AC signal on pin crosses
ground
• 5-Bit Digital-to-Analog Converter (DAC):
- Output available externally
- Programmable 5-bit voltage (% of VDD)
- Internal connections to comparators, Fixed
Voltage Reference and ADC
• Three Comparators (CMP):
- Five external inputs
- External output via PPS
• Fixed Voltage Reference (FVR) module:
- 1.024V, 2.048V and 4.096V output levels
Clocking Structure
• High-Precision Internal Oscillator Block (HFINTOSC):
- Selectable frequency range up to 64 MHz
- ±1% at calibration
• 32 kHz Low-Power Internal Oscillator
(LFINTOSC)
• External 32 kHz Crystal Oscillator (SOSC)
• External Oscillator Block:
- Three crystal/resonator modes
- 4x PLL with external sources
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock
stops
• Oscillator Start-up Timer (OST)
Programming/Debug Features
• In-Circuit Debug Integrated On-Chip
• In-Circuit Serial Programming™ (ICSP™) via Two
Pins
• In-Circuit Debug (ICD) with Three Breakpoints via
Two Pins
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2016 Microchip Technology Inc. Preliminary DS40001841B-page 3
PIC18(L)F67K40
PIC18(L)F6xK40 Family Types
Device
Data Sheet Index
Program Memory Flash
(words)
Data SRAM
(bytes)
Data EEPROM
(bytes)
I/O Pins
16-bit Timers
Comparators
10-bit ADC2with
Computation (ch)
5-bit DAC
Zero-Cross Detect
CCP/10-bit PWM
CWG
Signal Measurement
Timer (SMT)
8-bit TMR with HLT
Windowed Watchdog
Timer
CRC with Memory Scan
EUSART
I2C/SPI
PPS
Peripheral Module Disable
Temperature Indicator
Debug(1)
PIC18(L)F65K40 (1) 32k 2048 1024 60 5 3 47 1 1 5/2 1 2 4 Y Y 5 2 Y Y Y I
PIC18(L)F66K40 (1) 64k 3568 1024 60 5 3 47 1 1 5/2 1 2 4 Y Y 5 2 Y Y Y I
PIC18(L)F67K40 (2) 128k 3568 1024 60 5 3 47 1 1 5/2 1 2 4 Y Y 5 2 Y Y Y I
Note 1: Debugging Methods: (I) – Integrated on Chip.
Data Sheet Index: (Unshaded devices are described in this document.)
1. DS40001842 PIC18(L)F65/66K40 Data Sheet, 64-Pin, 8-bit Flash Microcontrollers
2. DS40001841 PIC18(L)F67K40 Data Sheet, 64-Pin, 8-bit Flash Microcontrollers
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
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2016 Microchip Technology Inc. Preliminary DS40001841B-page 4
PIC18(L)F67K40
Pin Diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
38
37
36
35
34
33
50 49
17 18 19 20 21 22 23 24 25 26
RE2 RE3 RE4 RE5 RE6 RE7 RD0 RH2 RH3 RD1 RD2 RD3 RD4 RD5 RD6 RD7
RE1
RE0
RG0
RG1
RG2
RG3
VPP/MCLR/RG5
RG4
VSS
VDD
RF7
RF6
RF5
RF4
RF3
RF2
RB0
RB1
RB2
RB3
RB4
RB5
RB6
VSS
RA6
RA7
VDD
RB7
RC4
RC3
RC2
RF0 RF1
RG7 RG6
RA3 RA2
RA1 RA0
RH1 RH0
RA4
RA5
RC1 RC0 RC7 RC6
RC5
15
16
31
40
39
27 28 29 30 32
48
47
46
45
44
43
42
41
54 53 52 5158 57 56 5560 59
64 63 62 61
64-Pin TQFP (10x10x1)
PIC18(L)F67K40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
38
37
36
35
34
33
50 49
17 18 19 20 21 22 23 24 25 26
RE2 RE3 RE4 RE5 RE6 RE7 RD0 RH2 RH3 RD1 RD2 RD3 RD4 RD5 RD6 RD7
RE1
RE0
RG0
RG1
RG2
RG3
VPP/MCLR/RG5
RG4
VSS
VDD
RF7
RF6
RF5
RF4
RF3
RF2
RB0
RB1
RB2
RB3
RB4
RB5
RB6
VSS
RA6
RA7
VDD
RB7
RC4
RC3
RC2
RF0 RF1
RG7 RG6
RA3 RA2
RA1 RA0
RH1 RH0
RA4
RA5
RC1 RC0 RC7 RC6
RC5
15
16
31
40
39
27 28 29 30 32
48
47
46
45
44
43
42
41
54 53 52 5158 57 56 5560 59
64 63 62 61
PIC18(L)F67K40
64-Pin QFN (9x9x1)
Note: It is recommended that the exposed bottom pad be connected to VSS. However, it must
not be the only VSS connection to the device.
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2016 Microchip Technology Inc. Preliminary DS40001841B-page 5
PIC18(L)F67K40
Pin Allocation Tables
TABLE 1: 64-PIN ALLOCATION TABLE (PIC18(L)F6XK40)
I/O(2)
64-Pin TQFP, QFN
A/D
DAC
Comparator
Timers
CCP and PWM
CWG
ZCD
SMT
Clock Reference
(CLKR)
Interrupt
EUSART
DSM
MSSP
Basic
RA0 24 ANA0 —C1IN4-
C2IN4-
C3IN4-
T8IN(1) — — — — — — — — —
RA1 23 ANA1 ——T2IN(1) — — — — — — — — — —
RA2 22 ANA2
VREF-
VREF-C1IN1+
C2IN1+
C3IN1+
— — — — — — — — — — —
RA3 21 ANA3
VREF+
VREF+— — — — — — — — — — — —
RA4 28 ANA4 — — T0CKI(1) — — — — — — — — — —
RA5 27 ANA5 — — T3G(1) — — — — — — — — — —
RA6 40 ANA6 — — — — — — — — — — — — CLKOUT
OSC2
RA7 39 ANA7 — — — — — — — — — — — OSC1
CLKIN
RB0 48 ANB0 — — — — — ZCDIN — — IOCB0
INT0(1) — — —
RB1 47 ANB1 — — — — — — — — IOCB1
INT1(1) — — —(4) —
RB2 46 ANB2 — — — — — — — — IOCB2
INT2(1) — — —(4) —
RB3 45 ANB3 — — — — — — — — IOCB3
INT3(1) — — — —
RB4 44 ANB4 — — — — — — — — IOCB4 — — — —
RB5 43 ANB5 — — T1G(1)
T3CKI(1) — — — — — IOCB5 — — — —
RB6 42 ANB6 — — — — — — — — IOCB6 — — — ICSPCLK
RB7 37 ANB7 DAC1OUT2 — — — — — — — IOCB7 — — — ICSPDAT
RC0 30 — — — T1CKI(1) — — — — — IOCC0 CK4(3) — — SOSCO
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 17-1 for details on which PORT pins may be used for
this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in Register 17-2
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I2C™ logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard
TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
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2016 Microchip Technology Inc. Preliminary DS40001841B-page 6
PIC18(L)F67K40
RC1 29 — — — T6IN(1) — — — IOCC1 RX4(1)
DT4(1) — — SOSCI
RC2 33 — — — — — CWG1IN(1) — — — IOCC2 — — — —
RC3 34 — — — — — — — — — IOCC3 — — SCL1(3,4)
SCK1(1) —
RC4 35 — — — — — — — — — IOCC4 ——SDA1(3,4)
SDI1(1) —
RC5 36 — — — — — — — — — IOCC5 — — — —
RC6 31 — — — — — — — — — IOCC6 CK1(3) — — —
RC7 32 — — — — — — — — — IOCC7 RX1(1)
DT1(3) — — —
RD0 58 AND0 — — — — — — — — — — — — —
RD1 55 AND1 — — T5CKI(1)
T7G(1) — — — — — — — — — —
RD2 54 AND2 — — — — — — — — — — — — —
RD3 53 AND3 — — — — — — — — — — MDCARL(1) — —
RD4 52 AND4 — — — — — — — — — — MDCARH(1) —
RD5 51 AND5 — — — — — — — — — — MDSRC(1) SDA2(3,4)
SDI2(1) —
RD6 50 AND6 — — — — — — — — — — — SCL2(3,4)
SCK2(1)
RD7 49 AND7 — — — — — — — — — — — SS2(1) —
RE0 2ANE0 — — — — — — — — IOCE0 CK3(3) — — —
RE1 1ANE1 — — — — — — — — IOCE1 RX3(1)
DT3(3) — — —
RE2 64 ANE2 — — — — — — — — IOCE2 CK5(3) — — —
RE3 63 ANE3 — — — — — — — — IOCE3 RX5(1)
DT5(3) — — —
RE4 62 ANE4 ——T4IN(1) CCP2(1) — — ——IOCE4 — — — —
TABLE 1: 64-PIN ALLOCATION TABLE (PIC18(L)F6XK40) (CONTINUED)
I/O(2)
64-Pin TQFP, QFN
A/D
DAC
Comparator
Timers
CCP and PWM
CWG
ZCD
SMT
Clock Reference
(CLKR)
Interrupt
EUSART
DSM
MSSP
Basic
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 17-1 for details on which PORT pins may be used for
this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in Register 17-2
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I2C™ logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard
TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
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2016 Microchip Technology Inc. Preliminary DS40001841B-page 7
PIC18(L)F67K40
RE5 61 ANE5 — — — CCP1(1) — — — — IOCE5 — — — —
RE6 60 ANE6 — — — CCP3(1) — — SMT1WIN1(1) —IOCE6 — — — —
RE7 59 ANE7 — — — — — — SMT1SIG1(1) —IOCE7 — — — —
RF0 18 ANF0— —C1IN0-
C2IN0-
— — — — — — — — — — —
RF1 17 ANF1 — — — — — — — — — — — — —
RF2 16 ANF2 — — — — — — — — — — — — —
RF3 15 ANF3— —C1IN2-
C2IN2-
C3IN2-
— — — — — — — — — — —
RF4 14 ANF4 —C2IN0+ — — — — — — — — — — —
RF5 13 ANF5 DAC1OUT1 C1IN1-
C2IN1-
— — — — — — — — — — —
RF6 12 ANF6 —C1IN0+ — — — — — — — — — — —
RF7 11 ANF7— —C1IN3-
C2IN3-
C3IN3-
— — — — — — — — — SS1(1) —
RG0 3ANG0 — — — — — — — — — — — — —
RG1 4ANG1 — — — — — — — — — CK2(1) — — —
RG2 5ANG2 —C3IN0+ — — — — — — — RX2(1)
DT2(3) — — —
RG3 6ANG3 —C3IN0- —CCP4(1) — — — — — — — — —
RG4 8ANG4 —C3IN1- T5G(1)
T7CKI(1) CCP5(1) — — — — — — — — —
RG5 7— — — — — — — — — — IOCG5 — — MCLR, VPP
RG6 20 ANG6 — — — — — — SMT2WIN1(1) — — — — — —
RG7 19 ANG7 — — — — — — SMT2SIG1(1) — — — — — —
RH0 26 — — — — — — — — — — — — — —
RH1 25 ADCACT(1) — — — — — — — — — — — — —
TABLE 1: 64-PIN ALLOCATION TABLE (PIC18(L)F6XK40) (CONTINUED)
I/O(2)
64-Pin TQFP, QFN
A/D
DAC
Comparator
Timers
CCP and PWM
CWG
ZCD
SMT
Clock Reference
(CLKR)
Interrupt
EUSART
DSM
MSSP
Basic
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 17-1 for details on which PORT pins may be used for
this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in Register 17-2
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I2C™ logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard
TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
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2016 Microchip Technology Inc. Preliminary DS40001841B-page 8
PIC18(L)F67K40
RH2 57 — — — — — — — — — — — — — —
RH3 56 — — — — — — — — — — — — — —
VDD 10, 38 — — — — — — — — — — — — — VDD
VSS 9, 41 — — — — — — — — — — — — — VSS
OUT(2) —ADGRDA
ADGRDB
—C1OUT
C2OUT
C3OUT
TMR0 CCP1
CCP2
CCP3
CCP4
CCP5
PWM6OUT
PWM7OUT
CWG1A
CWG1B
CWG1C
CWG1D
— — CLKR —TX1/CK1(3)
DT1(3)
TX2/CK2(3)
DT2(3)
TX3/CK3(3)
DT3(3)
TX4/CK4(3)
DT4(3)
TX5/CK5(3)
DT5(3)
DSM SDO1
SCK1
SDO2
SCK2
—
TABLE 1: 64-PIN ALLOCATION TABLE (PIC18(L)F6XK40) (CONTINUED)
I/O(2)
64-Pin TQFP, QFN
A/D
DAC
Comparator
Timers
CCP and PWM
CWG
ZCD
SMT
Clock Reference
(CLKR)
Interrupt
EUSART
DSM
MSSP
Basic
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 17-1 for details on which PORT pins may be used for
this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in Register 17-2
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I2C™ logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard
TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
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2016 Microchip Technology Inc. Preliminary DS40001841B-page 9
PIC18(L)F67K40
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with PIC18(L)F6xK40 Microcontrollers ...................................................................................... 16
3.0 Device Configuration .................................................................................................................................................................. 19
4.0 Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 32
5.0 Reference Clock Output Module ................................................................................................................................................ 51
6.0 Power-Saving Operation Modes ................................................................................................................................................ 56
7.0 Peripheral Module Disable (PMD).............................................................................................................................................. 64
8.0 Resets ........................................................................................................................................................................................ 71
9.0 Windowed Watchdog Timer (WWDT) ........................................................................................................................................ 80
10.0 Memory Organization ................................................................................................................................................................. 89
11.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 126
12.0 8x8 Hardware Multiplier............................................................................................................................................................ 150
13.0 Cyclic Redundancy Check (CRC) Module with Memory Scanner............................................................................................ 152
14.0 Interrupts .................................................................................................................................................................................. 169
15.0 I/O Ports ................................................................................................................................................................................... 206
16.0 Interrupt-on-Change ................................................................................................................................................................. 217
17.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 221
18.0 Timer0 Module ......................................................................................................................................................................... 231
19.0 Timer1/3/5/7 Module with Gate Control.................................................................................................................................... 237
20.0 Timer2/4/6/8 Module ................................................................................................................................................................ 253
21.0 Capture/Compare/PWM Module .............................................................................................................................................. 274
22.0 Pulse-Width Modulation (PWM 6/7) ......................................................................................................................................... 289
23.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 297
24.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 303
25.0 Signal Measurement Timer (SMT) ........................................................................................................................................... 330
26.0 Data Signal Modulator (DSM) Module...................................................................................................................................... 374
27.0 Master Synchronous Serial Port (MSSP1) Module ................................................................................................................. 385
28.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 442
29.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 473
30.0 Temperature Indicator Module ................................................................................................................................................. 475
31.0 5-Bit Digital-to-Analog Converter (DAC) Module...................................................................................................................... 477
32.0 Analog-to-Digital Converter with Computation (ADC2) Module ............................................................................................... 481
33.0 Comparator Module (C1/2/3) ................................................................................................................................................... 517
34.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 527
35.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 534
36.0 Instruction Set Summary .......................................................................................................................................................... 536
37.0 Development Support............................................................................................................................................................... 586
38.0 Electrical Specifications............................................................................................................................................................ 590
39.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 620
40.0 Packaging Information.............................................................................................................................................................. 621
Appendix A: Revision History............................................................................................................................................................. 628
Appendix B: Device Differences ........................................................................................................................................................ 629
The Microchip Website ...................................................................................................................................................................... 630
Customer Change Notification Service .............................................................................................................................................. 630
Customer Support.............................................................................................................................................................................. 630
Product Identification System ............................................................................................................................................................ 631
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2016 Microchip Technology Inc. Preliminary DS40001841B-page 10
PIC18(L)F67K40
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