Microchip Technology Microsemi Hello FPGA Libero Design User manual

UG0891
User Guide
Hello FPGA Libero Design

50200891. 1.0 12/19
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Microsemi Proprietary UG0891 Revision 1.0 iii
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Hello FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Video Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Line_write_read Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1.1 WRITE_LSRAM_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.2 Image Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.3 LCD_FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 FlashFreeze_SB Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.1 CCC IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.2 FLASH_FREEZE IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.3 MSS IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 UART_interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.1 COREUART_C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 APB3_if (APB slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 Mux_2_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6 FF_EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 FF_GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.8 OSC_C0 IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.9 Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Digit Recognition (AI) Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 FlashFreeze SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 Apb3_if (APB slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Line_write_read SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 TOP CNN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5 Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 DSP (FIR) Filter Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 FlashFreeze_SB_0 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2 FIR_FILTER_0 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 LCD_DISPLAY_0 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4 Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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Figures
Figure 1 Hello FPGA Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2 LCD and Camera Sensor Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3 Top-Level Hardware Implementation (Video Demo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4 Line_write_read SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5 FlashFreeze_SB_0 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6 CCC IP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7 Flash_Freeze IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8 MSS Component Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 9 UART_interface SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10 CoreUART C0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 11 Apb3_if . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12 MUX_2_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 13 FF_EXT Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 14 FF_Generator Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 15 OSC_C0 IP Core Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 16 Top-Level Hardware Implementation (AI Digit Recognition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17 FlashFreeze_SB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 18 APB Slave Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 19 Line_write_read SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 20 Implemented SmartDesign block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 21 DSP FIR Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 22 Top-Level DSP Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23 FlashFreeze_SB_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24 FIR_FILTER Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25 LCD_DISPLAY_0 module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Microsemi Proprietary UG0891 Revision 1.0 v
Tables
Table 1 Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 2 Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3 Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Revision History
Microsemi Proprietary UG0891 Revision 1.0 1
1 Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
1.1 Revision 1.0
This is the first publication of the document.

Hello FPGA
Microsemi Proprietary UG0891 Revision 1.0 2
2 Hello FPGA
Hello FPGA is a low cost, compact-sized, and a feature-rich FPGA kit based on the non-volatile, Flash-
based, and low-power SmartFusion2 SoC FPGA (M2S010) from Microchip. SmartFusion2 SoC FPGAs
offer more resources in low density with a complete Microcontroller Subsystem that includes a 166 MHz
ARM Cortex M3 processor with an Embedded Trace Macrocell (ETM) and Instruction Cache, embedded
flash, and extensive peripherals including CAN, TSE, and USB.
An ultra-low power Flash*Freeze feature of SmartFusion2 SoC FPGAs allows the retention of design
while maintaining the I/O state for low-power applications. A single pin interrupt puts the device in the
Flash*Freeze mode and brings up these FPGAs to operational modes (within ~13 microseconds).
These FPGAs are ideal for general purpose functions such as Gigabit Ethernet or dual PCI Express
control planes, bridging functions, input/output (I/O) expansion and conversion, video/image processing,
system management and secure connectivity. These FPGAs are used by customers in Communications,
Industrial, Medical, Defense, and Aviation markets.
The Hello FPGA kit is designed for FPGA beginners and enthusiasts. The Hello FPGA kit is ideal for
developing control logic and data acquisition, image processing, signal processing, and artificial
intelligence applications.
The kit supports the measurement of the live FPGA core power consumption while running these
designs. The kit also allows users to freeze the design. The Hello FPGA kit includes a Microchip PIC32
MCU that it is used to program the SmartFusion2 SoC FPGA, monitor power, and general-purpose
functions.
The Hello FPGA Kit demonstrates the following features of the SmartFusion2 SoC FPGA:
• DSP functions: FIR Filter.
• Parallel Processing and Complex functions: Artificial Intelligence (real time hand-written digit
recognition).
• Low-Power: Shows power consumption in operational and Flash*Freeze modes.
• Instant ON: Highlighting fast wake-up from the Flash*Freeze mode to fully functional mode.
This user guide describes the following designs, which can be run on the kit:
•Video Demo Design, page 4
•Digit Recognition (AI) Demo Design, page 13
•DSP (FIR) Filter Demo Design, page 18
These designs are created using Microchip’s Libero SoC Design Software. The software includes all of
the necessary IPs required to build such application prototypes.
Note: These designs also include a user-friendly GUI application to test specific features functions. These
demo designs include the Flash*Freeze feature for demonstration. Users can monitor the power
consumption when the FPGA is in operational and Flash*Freeze modes to evaluate the low-power
advantage.
The kit includes Arduino and Mikrobus connectors for flexibility for prototyping, and expansion kits. This
can be very useful as the user’s FPGA knowledge and the associated tools experience increases. The kit
can work as a standalone unit or as an extension to existing MCHP kits.
Figure 1, page 3 shows the Hello FPGA kit, which consists of the SmartFusion2 FPGA and
MCU (PIC32MX795F512L).

Hello FPGA
Microsemi Proprietary UG0891 Revision 1.0 3
Figure 1 • Hello FPGA Kit
The Hello FPGA kit includes the LCD board and the camera sensor. These boards can be connected to
the Hello FPGA kit as shown in Figure 2, page 3.
Figure 2 • LCD and Camera Sensor Boards

Video Demo Design
Microsemi Proprietary UG0891 Revision 1.0 4
3 Video Demo Design
The following figure shows the top-level video demo design in Libero.
Figure 3 • Top-Level Hardware Implementation (Video Demo)
The video demo design interfaces the Camera Sensor OV7725 and LCD with the SmartFusion2 SoC
FPGA. The design also includes the Flash*Freeze feature.
The Top module contains the following modules:
•Line_write_read Module, page 4
•FlashFreeze_SB Module, page 6
•UART_interface, page 9
•APB3_if (APB slave), page 10
•FF_EXT, page 10
•FF_GENERATOR, page 11
•Mux_2_1, page 10
•OSC_C0 IP, page 11
3.1 Line_write_read Module
Figure 4, page 5 shows the components of the Line_read_write module. Line_write_read module
acquires the data from the OV7725 Camera sensor, performs image scaling as well as image
enhancement and sends data to LCD Screen. OV7725 camera has an array size of 640 x 480 and is
configured to operate in RGB 565 format. LCD ILI9488 has a display resolution of 480 x 320.
WRITE_LSRAM module down samples the 640x480 camera data to 480x320 LCD resolution. After
down sampling the image data goes through image enhancement that can be configured through UART.
Image Enhancement block writes the data in the Dual Port RAM. LCD_FSM reads the data from dual
port RAM and sends it to the LCD display as per the LCD interface protocol.

Video Demo Design
Microsemi Proprietary UG0891 Revision 1.0 5
Figure 4 • Line_write_read SD
The Line_write_read module contains the following components:
•WRITE_LSRAM_0, page 5
•Image Enhancement, page 5
•LCD_FSM, page 5
3.1.1 WRITE_LSRAM_0
Signals from the Camera PLK_I, H_REF, and DATA_I(8) are transferred through the Double Flip-Flop
synchronizer circuit to ensure the integrity of these signals. Input data signal from the camera DATA_I is
considered valid when the H_REF signal is high. Data from the camera is in the form of RGB 5:6:5 format
and is split across 2 clock cycles. Down sampling from 640 pixels per horizontal line to 480 pixels per
horizontal line is achieved by skipping a pixel for every 4 pixels. Down sampling from 480 lines to 320
lines is achieved by skipping one horizontal line for every 3 lines.
3.1.2 Image Enhancement
This module performs modification on the pixel output data from the WRITE_LSRAM based on the user-
controlled data provided by the UART block. User-controlled data include contrast, brightness, and RGB
color adjustment values.
3.1.3 LCD_FSM
The LCD_FSM module reads data from the dual port RAM and sends it to the LCD display. The module
starts reading the dual port RAM when the write address in WRITE_LSRAM reaches 160. The
LCD_FSM also resets the registers of the LCD based on the V_Sync signal of the camera which
indicates the start of new frame data. LCD_FSM provides data to the LCD based on the interface
protocol.

Video Demo Design
Microsemi Proprietary UG0891 Revision 1.0 6
3.2 FlashFreeze_SB Module
Figure 5, page 6 shows the components of the FlashFreeze_SB_MSS module. The
FlashFreeze_SB_MSS module configures the Microcontroller Sub System (MSS). The I2C peripheral in
MSS is used to configure camera registers. MSS is the APB master which is connected to the APB slave
(apb3_if) module to initialize LCD registers during startup. The Flash_FREEZE module provides the
feature of low power FF mode to the FPGA. The FF_Entry_SW signal provides the hardware interrupt for
FF to MSS. When interrupt comes MSS executes the instruction related to FF firmware through which
FPGA goes into the flash freeze mode. MSS is in an infinite loop when the FPGA fabric is in the
Flash*Freeze mode.
Figure 5 • FlashFreeze_SB_0 Module

Video Demo Design
Microsemi Proprietary UG0891 Revision 1.0 7
3.2.1 CCC IP
CCC IP is available in Libero SoC -> Clock and Management IP catalog. CCC IP acquires the 25/50
MHZ clock from the on-chip oscillator IP and generates the GL0 clock of 100 MHz and GL1 of 24 MHz
clock. All the modules inside FPGA works on GL0 clock. The following figure shows the configuration of
the CCC IP.
Figure 6 • CCC IP Configuration
3.2.2 FLASH_FREEZE IP
FLASH FREEZE IP is available in Libero SoC -> Catalog. SmartFusion2 SoC FPGA devices provide an
ultra-low static power solution through Flash*Freeze technology. Flash*Freeze mode entry retains all the
Static Random Access Memory (SRAM) and registers information. Flash*Freeze mode exit achieves
rapid recovery to active mode (approximately 13 µs). The following figure shows the FLASH FREEZE IP.
Figure 7 • Flash_Freeze IP

Video Demo Design
Microsemi Proprietary UG0891 Revision 1.0 8
3.2.3 MSS IP
SmartFusion2 Microcontroller Subsystem (MSS) IP is available in Libero SoC -> Catalog -> Processors.
The MSS Component Configurator represents a graphical block diagram of the SmartFusion2
Microcontroller Subsystem. Each of MSS sub-blocks can be enabled or disabled as per the application
requirements. This design uses FIC_0 for APB interface and I2C_0 to enable camera configuration
interface and GPIO to acquire external signal.
Figure 8 • MSS Component Configuration

Video Demo Design
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3.3 UART_interface
Figure 9 • UART_interface SD
UART_interface SmartDesign performs the task of communication between the SmartFusion2 FPGA
and the PC with PIC microcontroller as a bridge. Based on the data from Hello_FPGA GUI, receive_data
module generates the address and the data. Addr_decoder module generates the values of brightness,
contrast, and color and provides it to the Image_enchancement module.
3.3.1 COREUART_C0
COREUART IP is available in the Libero SoC peripheral IP catalog. BAUD rate of UART is 230400,
based on the operating clock frequency, BAUD_VAL, and BAUD_VAL_FRACTION values. The following
figure shows the CoreUART configuration.
Figure 10 • CoreUART C0 Configuration

Video Demo Design
Microsemi Proprietary UG0891 Revision 1.0 10
3.4 APB3_if (APB slave)
Figure 11 • Apb3_if
Apb3_if module implements the APB slave Interface to communicate with APB3 Master (MSS). LCD
initialization is done through this module based on the control and data words provided by the MSS. After
LCD initialization, MSS gives the command to the APB slave to generate init_done signal.
3.5 Mux_2_1
Figure 12 • MUX_2_1
MSS provides the select signal (Init_done) to the MUX, MSS first initializes the LCD and after
initialization, MSS gives LCD control to the FPGA fabric.
3.6 FF_EXT
Figure 13 • FF_EXT Module
FF_EXT module generates the pulse based on the PPL lock signal. The output pulse is given to the PIC
controller, which signifies the FPGA fabric is out of flash freeze mode.

Video Demo Design
Microsemi Proprietary UG0891 Revision 1.0 11
3.7 FF_GENERATOR
Figure 14 • FF_Generator Module
FF_Generator module implements a power down signal for the camera module based on the flash freeze
signal FF_to_start_i, which indicates the fabric is in flash freeze or active.
3.8 OSC_C0 IP
OSC_C0 IP is available in the Libero SoC clock and management IP catalog. There are three oscillator
blocks in the SmartFusion2 device that can be used in different use models:
• On-chip 25/50 MHz RC Oscillator - This oscillator generates a 50 MHz waveform when the core
supply voltage is 1.2V and 25 MHz when the supply voltage is 1.0V. The device core voltage
can be selected from the Libero SoC Device Settings dialog box.
• On-chip 1 MHz RC Oscillator
• Main Crystal Oscillator
For this design we used on chip 25/50 MHz RC Oscillator. The following figure shows the configuration of
the OSC_C0 IP core.
Figure 15 • OSC_C0 IP Core Configuration

Video Demo Design
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3.9 Resource Utilization
The following table lists the resource utilization of the Video demo design.
Table 1 • Resource Utilization
Type Used Total Percentage
4LUT 558 12084 4.62
DFF 584 12084 4.83
User I/O
(single-ended)
37 138 26.81
RAM1K18 1 21 4.76
MACC 3 22 13.64

Digit Recognition (AI) Demo Design
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4 Digit Recognition (AI) Demo Design
The following figure shows the top-level AI digit recognition demo design in Libero.
Figure 16 • Top-Level Hardware Implementation (AI Digit Recognition)
AI Digit Recognition libero project aims to show Artificial Intelligence (AI) application. The Libero design
for AI digit recognition is similar to the Video Demo Libero project with below additional modules.
•FlashFreeze SmartDesign, page 14
•Apb3_if (APB slave), page 15
•Line_write_read SmartDesign, page 16
•TOP CNN, page 16

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4.1 FlashFreeze SmartDesign
Figure 17 • FlashFreeze_SB
FlashFreeze_SB_MSS configures the MSS. The I2C peripheral in MSS is used to configure camera
registers. MSS is the APB master which is connected to the APB slave (apb3_if) module to initialize LCD
registers during startup. Flash_FREEZE module provides the feature of low power FF mode to the
FPGA. The FF_Entry_SW signal provides the hardware interrupt for FF to MSS. When there is an
interrupt, MSS executes the instruction related to FF firmware through which FPGA goes into the flash
freeze mode. While FPGA is in FF mode, MSS will wait for the FPGA to come out of FF. MSS identifies
that the FPGA is out of FF mode based on the FF_done signal interrupt. After receiving the FF_done
signal interrupt the MSS can communicate with the FPGA through APB.

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4.2 Apb3_if (APB slave)
Apb3_if is an APB slave module that communicates with the MSS. MSS first loads the weights into the
Convolution Neural Network (CNN) SD through APB slave. After loading weights, MSS initializes the
LCD display and transfers the LCD control to the FPGA fabric through init_done signal. APB slave
acquires the digit recognized result from the CNN SD. The MSS loads the graphics related to the
recognized digit in to the LSRAM for On Screen Display (OSD) of the recognized digit. The following
figure shows the APB slave module configuration.
Figure 18 • APB Slave Module Configuration