Microchip Technology ATSAMR30M18A User manual

ATSAMR30M18A
SAMR30 IEEE® 802.15.4™ Sub-1GHz Module Datasheet
Introduction
The ATSAMR30M18A is an IEEE® 802.15.4™-2003/2006/2011-compliant RF module for the sub-1 GHz ISM bands,
such as 780 MHz (China), 868 MHz (Europe) and 915 MHz (North America), optimized for low-power applications.
This module combines the ATSAMR30E18A SiP (System in Package), 16 MHz crystal oscillator, discrete balun,
lumped element harmonic reject filter and required RF shielding in a compact 12.7 mm x 11.0 mm design. The
module as implemented on the Xplained Pro development board has passed regulatory approvals with chip antenna
or SMA connectorized monopole antenna.
This data sheet provides only a brief overview of the necessary sections of the module. For a detailed description of
each peripheral, refer to the ATSAMR30E18A data sheet.
Features
• Processor
– ARM® Cortex®-M0+ CPU running at up to 48 MHz
• Single-cycle hardware multiplier
• Micro Trace Buffer (MTB)
• Memories
– 256 KB in-system self-programmable Flash
– 32 KB SRAM
– 8 KB low-power RAM
• System
– Power-on Reset (POR) and Brown-out Detection (BOD)
– Internal clock option with 48 MHz Digital Frequency Locked Loop (DFLL48M) and 48 MHz to 96 MHz
Fractional Digital Phase Locked Loop (FDPLL96M)
– External Interrupt Controller (EIC)
– Up to 14 external interrupts
– One non-maskable interrupt
– Two-pin Serial Wire Debug (SWD) programming, test and debugging interface
• Low Power
– Idle and Standby Sleep modes
– Sleep walking peripherals
• Integrated Ultra-Low Power Transceiver for 700/800/900 MHz ISM Band:
– Chinese WPAN band from 779 to 787 MHz
– European SRD band from 863 to 870 MHz
– North American ISM band from 902 to 928 MHz
– Japanese band from 915 to 930 MHz
• Direct Sequence Spread Spectrum with Different Modulation and Data Rates:
– BPSK with 20 and 40 kb/s, compliant to IEEE 802.15.4-2003/2006/2011
– O-QPSK with 100 and 250 kb/s, compliant to IEEE 802.15.4-2006/2011
– O-QPSK with 200, 400, 500 and 1000 kb/s PSDU data rate
© 2018-2021 Microchip Technology Inc.
and its subsidiaries
Datasheet DS70005384B-page 1

– Industry-leading link budget:
• RX sensitivity up to -105 dBm
• TX output power up to +8.7 dBm
– Hardware-assisted MAC:
• Auto-Acknowledge
• Auto-Retry
• CSMA-CA and Listen Before Talk (LBT)
• Automatic address filtering and automated FCS check
– Special 802.15.4-2011 hardware support:
• FCS computation and Clear Channel Assessment
• RSSI measurement, Energy Detection and Link Quality Indication
– 128 Byte TX/RX Frame Buffer
– Integrated 16 MHz Crystal Oscillator (external crystal is not needed)
– Fully integrated, fast settling transceiver PLL to support frequency hopping
– Hardware Security (AES, True Random Generator)
• Peripherals
– 16-channel Direct Memory Access Controller (DMAC)
– 12-channel event system
– Up to three 16-bit Timer/Counters (TC), including one low-power TC(TC4), each configurable as:
• 16-bit TC with two compare/capture channels
• 8-bit TC with two compare/capture channels
• 32-bit TC with two compare/capture channels, by using two TCs
– Two 24-bit and one 16-bit Timer/Counters for Control (TCC), with extended functions:
• Up to four compare channels with optional complementary output
• Generation of synchronized pulse width modulation (PWM) pattern across port pins
• Deterministic fault protection, fast decay and configurable dead-time between complementary output
• Dithering that increase resolution with up to 5-bit and reduce quantization error
– 32-bit Real Time Counter (RTC) with clock/calendar function
– Watchdog Timer (WDT)
– CRC-32 generator
– One full-speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface
• Embedded host and device function
• Eight endpoints
– Up to two Serial Communication Interfaces (SERCOM), each configurable to operate as either:
• USART with full-duplex or single-wire half-duplex configuration
• I2C up to 3.4 MHz
• SPI
• LIN Client
– Up to three Serial Communication Interfaces (SERCOM) including one low-power SERCOM (SERCOM5),
each configurable to operate as UART with internal clock
– One Configurable Custom Logic (CCL)
– One 12-bit, 350 ksps Analog-to-Digital Converter (ADC) with up to four external channels
• Differential and single-ended input
• Automatic offset and gain error compensation
• Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
– Two Analog Comparators (AC) with window compare function
– Peripheral Touch Controller (PTC)
• 12-Channel capacitive touch and proximity sensing
• Clock
ATSAMR30M18A
© 2018-2021 Microchip Technology Inc.
and its subsidiaries
Datasheet DS70005384B-page 2

– High precision 16 MHz integrated internal crystal
– 32.768 kHz internal oscillator (OSC32K)
– 32.768 kHz ultra-low power internal oscillator (OSCULP32K)
– 16/12/8/4 MHz high-accuracy internal oscillator (OSC16M)
– 48 MHz Digital Frequency Locked Loop (DFLL48M)
– 96 MHz Fractional Digital Phased Locked Loop (FDPLL96M)
• I/O and Package
– 16 programmable I/O pins
– 25-pin module package (12.7 mm x 11.0 mm) with castellated PCB pads
• Operating Voltage
– 1.8V – 3.6V
• Temperature Range
– -40°C to 85°C Industrial
• Power Consumption(1)
– RX_ON = 10.79 mA
– BUSY_TX = 26.97 mA
– Standby = 2.03 µA
– Backup mode = 0.77 µA
Note:
1. For more details, see 9.3.4 Current Consumption Specifications.
ATSAMR30M18A
© 2018-2021 Microchip Technology Inc.
and its subsidiaries
Datasheet DS70005384B-page 3

Table of Contents
Introduction.....................................................................................................................................................1
Features......................................................................................................................................................... 1
1. Ordering Information and Module Marking..............................................................................................6
2. Package Information............................................................................................................................... 7
3. Module Block Diagram............................................................................................................................ 8
3.1. Interconnection between SAM L21 and AT86RF212B within ATSAMR30E18A SiP................... 8
3.2. AT86RF212B Transceiver Circuit Description............................................................................10
4. Pinout Information................................................................................................................................. 12
5. Nonvolatile Memory Information........................................................................................................... 15
6. Boot Loader...........................................................................................................................................16
7. Module Description............................................................................................................................... 17
7.1. Physical Layer Modes................................................................................................................ 17
7.2. Receiver (RX).............................................................................................................................20
7.3. Transmitter (TX)......................................................................................................................... 21
7.4. Frame Buffer.............................................................................................................................. 23
7.5. Crystal Oscillator (XOSC) and Clock Output (CLKM)................................................................ 25
7.6. Frequency Synthesizer (PLL).....................................................................................................26
7.7. Automatic Filter Tuning (FTN).................................................................................................... 29
8. Radio Transceiver Usage......................................................................................................................31
8.1. Frame Receive Procedure......................................................................................................... 31
8.2. Frame Transmit Procedure.........................................................................................................31
9. Electrical Characteristics.......................................................................................................................33
9.1. Absolute Maximum Ratings........................................................................................................33
9.2. Recommended Operating Conditions........................................................................................ 33
9.3. Module Performance..................................................................................................................33
10. Mechanical Description......................................................................................................................... 41
10.1. Module Outline Drawings........................................................................................................... 41
10.2. Footprint..................................................................................................................................... 42
11. Design Considerations.......................................................................................................................... 43
11.1. Approved Antennas....................................................................................................................43
11.2. Module Assembly Considerations.............................................................................................. 43
12. Application Reference Design...............................................................................................................44
12.1. RF Trace Layout Design Instructions......................................................................................... 44
12.2. Routing Guidelines..................................................................................................................... 52
13. Regulatory Approval..............................................................................................................................54
13.1. United States (FCC)................................................................................................................... 54
ATSAMR30M18A
© 2018-2021 Microchip Technology Inc.
and its subsidiaries
Datasheet DS70005384B-page 4

13.2. Canada (ISED)...........................................................................................................................56
13.3. Europe........................................................................................................................................57
14. Continuous Transmission Test Mode Errata......................................................................................... 59
14.1. Overview.................................................................................................................................... 59
14.2. Configuration..............................................................................................................................59
15. Reference Documentation.................................................................................................................... 62
16. Document Revision History...................................................................................................................63
The Microchip Website.................................................................................................................................64
Product Change Notification Service............................................................................................................64
Customer Support........................................................................................................................................ 64
Microchip Devices Code Protection Feature................................................................................................ 64
Legal Notice................................................................................................................................................. 65
Trademarks.................................................................................................................................................. 65
Quality Management System....................................................................................................................... 66
Worldwide Sales and Service.......................................................................................................................67
ATSAMR30M18A
© 2018-2021 Microchip Technology Inc.
and its subsidiaries
Datasheet DS70005384B-page 5

1. Ordering Information and Module Marking
The following table provides the ordering details for the ATSAMR30M18A module.
Table 1-1. Ordering Information for ATSAMR30M18A
Model Number Ordering Code Package
Dimension
Number of
Pins Description Regulatory Approval
ATSAMR30M18A
ATSAMR30M18A-I/
RMxxx 12.7mm x
11mm x
2.71mm
25
SAM R30 Module
in Tray package
FCC, ISED,
CE
ATSAMR30M18AT-I/
RMxxx
SAM R30 Module
in Tape and Reel
package
Figure 1-1. Module Ordering Code Information
ATSAMR 30 M 18 A T – I / RM xxx
Product Family
SAMR = Microcontroller with RF
Product Series
30 = Cortex M0 + CPU + Sub GHz
802.15.4 Transceiver
Pin Count
M = Module
Flash Memory Density
18 = 256 KB
Device Variant
A = Hardware Revision
xxx = Bootloader
FW Version
Package Type
RM = Radio Module
Temperature Rating
I = -40 to +85C
Package Carrier
Blank = Tray
T = Tape and Reel
ATSAMR30M18A
Ordering Information and Module Marking
© 2018-2021 Microchip Technology Inc.
and its subsidiaries
Datasheet DS70005384B-page 6

2. Package Information
The following table provides the ATSAMR30M18A module package dimensions.
Table 2-1. ATSAMR30M18A Package Information
Parameter Value Units
Package size 12.7 x 11.0 mm
Pad count 25 —
Total thickness 2.71 mm
Pad pitch 1.2 mm
Pad width 0.8 mm
ATSAMR30M18A
Package Information
© 2018-2021 Microchip Technology Inc.
and its subsidiaries
Datasheet DS70005384B-page 7

3. Module Block Diagram
The ATSAMR30M18A module contains ATSAMR30E18A SiP, 16 MHz crystal, discrete Balun and lumped element
Harmonic Filter.
The following figure shows the block diagram of the ATSAMR30M18A module.
Figure 3-1. Module Block Diagram
ATSAMR30E18A Balun + Harmonic
Filter (Discrete)
16 MHz
RF_P
RF_N RF_OUT
SERCOM SPI/
ADC/AC/CCL
SWD Interface/TC/
TCC
GPIOs
UART/I2C
USB/EXTINT
ATSAMR30M18A
The ATSAMR30E18A SIP consists of two vertically integrated silicon dies:
• SAM L21 ARM Cortex M0+ based microcontroller
• AT86RF212B low-power, low-voltage 700/800/900 MHz transceiver
The local communication and control interface is wired within the package. Key I/O external signals are exposed
as I/O pins.
3.1 Interconnection between SAM L21 and AT86RF212B within ATSAMR30E18A SiP
This section describes the interconnection between SAM L21 and AT86RF212B. The interface comprises a client SPI
and additional control signals. This interface is a host SPI interface in SAM L21 as shown in the following figure.
ATSAMR30M18A
Module Block Diagram
© 2018-2021 Microchip Technology Inc.
and its subsidiaries
Datasheet DS70005384B-page 8

Figure 3-2. Interconnection between SAM L21 and AT86RF212B
SAM L21 AT86RF212B
SAM R30
SERCOM 4
SPI-Client
GCLK
GENERATOR 1
/SEL
MOSI
MISO
SCLK
CLKM
IRQ
CONTROL
LOGIC
PORTx
SLP_TR
/RST
External PA
and POWER
CONTROL
ANTENNA
DIVERSITY
CONTROL
RFCTRL
DIG1
DIG2
DIG3
DIG4
PA20
PB15
PB16
(2)
PB17
(2)
PA10
(2)
PA11
(2)
PC16(F)
(1)
PB00(A)
(1)
PB31(F)
(1)
PAD1
PB30(F)
(1)
PAD2
PC19(F)
(1)
PAD0
PAD3 PC18(F)
(1)
1. Alternate pin function and direction has to be configured by software.
2. Pin function is configured by hardware automatically after reset.
EXTINT1
The SPI is used for register, Frame Buffer, SRAM and AES access. The additional control signals are connected to
the GPIO/IRQ interface of the microcontroller. The following table introduces the radio transceiver I/O signals and
their functionality.
Table 3-1. Microcontroller Interface Signal Description
Signal Description
/SEL SPI select signal, active-low
MOSI SPI data (host output client input) signal
MISO SPI data (host input client output) signal
SCLK SPI clock signal
ATSAMR30M18A
Module Block Diagram
© 2018-2021 Microchip Technology Inc.
and its subsidiaries
Datasheet DS70005384B-page 9

...........continued
Signal Description
CLKM
Optional, clock output, usable as:
• Microcontroller clock source and/or MAC timer reference
• High precision timing reference
IRQ
Interrupt request signal, further used as:
• Frame Buffer Empty indicator
SLP_TR
Multi-purpose control signal (functionality is state dependent):
• Sleep/Wake up: enable/disable SLEEP state
• TX start: BUSY_TX_(ARET) state
• Disable/enable CLKM
/RST AT86RF212B Reset signal; active-low
DIG2
Optional:
• IRQ_2 (RX_START) for RX Frame Time Stamping
3.2 AT86RF212B Transceiver Circuit Description
The AT86RF212B single-chip radio transceiver provides a complete radio transceiver interface between radio
frequency signals and the baseband microcontroller. It comprises a bidirectional analog RF front end, direct-
conversion mixers, low-noise fractional-n PLL, quadrature digitizer, DSP modem and baseband packet-handler
optimized for IEEE 802.15.4 MAC/PHY automation and low power. An SPI accessible 128-byte TRX buffer stores
receive or transmit data. Radio communication between transmitter and receiver is based on DSSS Spread Spectrum
with OQPSK or BPSK modulation schemes as defined by the IEEE 802.15.4 standard. Additional proprietary
modulation modes include high-data rate payload encoding and wideband BPSK-40-ALT.
ATSAMR30M18A
Module Block Diagram
© 2018-2021 Microchip Technology Inc.
and its subsidiaries
Datasheet DS70005384B-page 10