Motorola MC68020 User manual

© MOTOROLA INC., 1992
MC68020
MC68EC020
MICROPROCESSORS
USER’S MANUAL
First Edition
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MOTOROLA M68020 USER’S MANUAL iii
PREFACE
The M68020 User’s Manual describes the capabilities, operation, and programming of the
MC68020 32-bit, second-generation, enhanced microprocessor and the MC68EC020 32-
bit, second-generation, enhanced embedded microprocessor.
Throughout this manual, “MC68020/EC020” is used when information applies to both the
MC68020 and the MC68EC020. “MC68020” and “MC68EC020” are used when
information applies only to the MC68020 or MC68EC020, respectively.
For detailed information on the MC68020 and MC68EC020 instruction set, refer to
M68000PM/AD,
M68000 Family Programmer’s Reference Manual .
This manual consists of the following sections:
Section 1 Introduction
Section 2 Processing States
Section 3 Signal Description
Section 4 On-Chip Cache Memory
Section 5 Bus Operation
Section 6 Exception Processing
Section 7 Coprocessor Interface Description
Section 8 Instruction Execution Timing
Section 9 Applications Information
Section 10 Electrical Characteristics
Section 11 Ordering Information and Mechanical Data
Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire
Bus Arbitration Protocol
NOTE
In this manual,
assert and negate are used to specify forcing a
signal to a particular state. In particular,
assertion and assert
refer to a signal that is active or true; negation and negate
indicate a signal that is inactive or false. These terms are used
independently of the voltage level (high or low) that they
represent.

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TABLE OF CONTENTS
Paragraph Page
Number Title Number
Section 1
Introduction
1.1 Features ..................................................................................................1-2
1.2 Programming Model ................................................................................1-4
1.3 Data Types and Addressing Modes Overview ........................................1-8
1.4 Instruction Set Overview .........................................................................1-10
1.5 Virtual Memory and Virtual Machine Concepts.......................................1-10
1.5.1 Virtual Memory ....................................................................................1-10
1.5.2 Virtual Machine....................................................................................1-12
1.6 Pipelined Architecture .............................................................................1-12
1.7 Cache Memory........................................................................................1-13
Section 2
Processing States
2.1 Privilege Levels.......................................................................................2-2
2.1.1 Supervisor Privilege Level ...................................................................2-2
2.1.2 User Privilege Level.............................................................................2-3
2.1.3 Changing Privilege Level.....................................................................2-3
2.2 Address Space Types .............................................................................2-4
2.3 Exception Processing..............................................................................2-5
2.3.1 Exception Vectors................................................................................2-5
2.3.2 Exception Stack Frame .......................................................................2-6
Section 3
Signal Description
3.1 Signal Index ............................................................................................3-2
3.2 Function Code Signals (FC2–FC0).........................................................3-2
3.3 Address Bus (A31–A0, MC68020)(A23–A0, MC68EC020) ....................3-2
3.4 Data Bus (D31–D0).................................................................................3-2
3.5 Transfer Size Signals (SIZ1, SIZ0) .........................................................3-2
3.6 Asynchronous Bus Control Signals.........................................................3-4
3.7 Interrupt Control Signals..........................................................................3-5
3.8 Bus Arbitration Control Signals ...............................................................3-6
3.9 Bus Exception Control Signals................................................................3-6
3.10 Emulator Support Signal .........................................................................3-7
3.11 Clock (CLK).............................................................................................3-7

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3.12 Power Supply Connections.....................................................................3-7
3.13 Signal Summary......................................................................................3-8
Section 4
On-Chip Cache Memory
4.1 On-Chip Cache Organization and Operation ..........................................4-1
4.2 Cache Reset ...........................................................................................4-3
4.3 Cache Control .........................................................................................4-3
4.3.1 Cache Control Register (CACR) .........................................................4-3
4.3.2 Cache Address Register (CAAR) ........................................................4-4
Section 5
Bus Operation
5.1 Bus Transfer Signals...............................................................................5-1
5.1.1 Bus Control Signals.............................................................................5-2
5.1.2 Address Bus........................................................................................5-3
5.1.3 Address Strobe....................................................................................5-3
5.1.4 Data Bus..............................................................................................5-3
5.1.5 Data Strobe .........................................................................................5-4
5.1.6 Data Buffer Enable ..............................................................................5-4
5.1.7 Bus Cycle Termination Signals............................................................5-4
5.2 Data Transfer Mechanism.......................................................................5-5
5.2.1 Dynamic Bus Sizing ............................................................................5-5
5.2.2 Misaligned Operands...........................................................................5-14
5.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment ................5-20
5.2.4 Address, Size, and Data Bus Relationships........................................5-21
5.2.5 Cache Interactions ..............................................................................5-22
5.2.6 Bus Operation .....................................................................................5-24
5.2.7 Synchronous Operation with DSACK1/DSACK0............................... 5-24
5.3 Data Transfer Cycles ..............................................................................5-25
5.3.1 Read Cycle..........................................................................................5-26
5.3.2 Write Cycle ..........................................................................................5-33
5.3.3 Read-Modify-Write Cycle.....................................................................5-39
5.4 CPU Space Cycles .................................................................................5-44
5.4.1 Interrupt Acknowledge Bus Cycles......................................................5-45
5.4.1.1 Interrupt Acknowledge Cycle—Terminated Normally...................... 5-45
5.4.1.2 Autovector Interrupt Acknowledge Cycle.........................................5-48
5.4.1.3 Spurious Interrupt Cycle ..................................................................5-48
5.4.2 Breakpoint Acknowledge Cycle...........................................................5-50
5.4.3 Coprocessor Communication Cycles ..................................................5-53
5.5 Bus Exception Control Cycles.................................................................5-53
5.5.1 Bus Errors ...........................................................................................5-55

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5.5.2 Retry Operation ...................................................................................5-56
5.5.3 Halt Operation......................................................................................5-60
5.5.4 Double Bus Fault.................................................................................5-60
5.6 Bus Synchronization................................................................................5-62
5.7 Bus Arbitration.........................................................................................5-62
5.7.1 MC68020 Bus Arbitration ....................................................................5-63
5.7.1.1 Bus Request (MC68020) .................................................................5-66
5.7.1.2 Bus Grant (MC68020)......................................................................5-66
5.7.1.3 Bus Grant Acknowledge (MC68020) ...............................................5-66
5.7.1.4 Bus Arbitration Control (MC68020)..................................................5-67
5.7.2 MC68EC020 Bus Arbitration ...............................................................5-70
5.7.2.1 Bus Request (MC68EC020) ............................................................5-71
5.7.2.2 Bus Grant (MC68EC020).................................................................5-71
5.7.2.3 Bus Arbitration Control (MC68EC020).............................................5-73
5.8 Reset Operation ......................................................................................5-76
Section 6
Exception Processing
6.1 Exception Processing Sequence ............................................................6-1
6.1.1 Reset Exception...................................................................................6-4
6.1.2 Bus Error Exception.............................................................................6-4
6.1.3 Address Error Exception......................................................................6-6
6.1.4 Instruction Trap Exception...................................................................6-6
6.1.5 Illegal Instruction and Unimplemented Instruction Exceptions ............6-7
6.1.6 Privilege Violation Exception ...............................................................6-8
6.1.7 Trace Exception...................................................................................6-9
6.1.8 Format Error Exception .......................................................................6-10
6.1.9 Interrupt Exceptions.............................................................................6-11
6.1.10 Breakpoint Instruction Exception.........................................................6-17
6.1.11 Multiple Exceptions..............................................................................6-17
6.1.12 Return from Exception.........................................................................6-19
6.2 Bus Fault Recovery.................................................................................6-21
6.2.1 Special Status Word (SSW).................................................................6-21
6.2.2 Using Software to Complete the Bus Cycles.......................................6-23
6.2.3 Completing the Bus Cycles with RTE..................................................6-24
6.3 Coprocessor Considerations...................................................................6-25
6.4 Exception Stack Frame Formats.............................................................6-25

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Section 7
Coprocessor Interface Description
7.1 Introduction .............................................................................................7-1
7.1.1 Interface Features ...............................................................................7-2
7.1.2 Concurrent Operation Support ............................................................7-2
7.1.3 Coprocessor Instruction Format..........................................................7-3
7.1.4 Coprocessor System Interface ............................................................7-4
7.1.4.1 Coprocessor Classification ..............................................................7-4
7.1.4.2 Processor-Coprocessor Interface....................................................7-5
7.1.4.3 Coprocessor Interface Register Selection .......................................7-6
7.2 Coprocessor Instruction Types ...............................................................7-7
7.2.1 Coprocessor General Instructions.......................................................7-8
7.2.1.1 Format .............................................................................................7-8
7.2.1.2 Protocol............................................................................................7-9
7.2.2 Coprocessor Conditional Instructions..................................................7-10
7.2.2.1 Branch on Coprocessor Condition Instruction .................................7-12
7.2.2.1.1 Format ..........................................................................................7-12
7.2.2.1.2 Protocol........................................................................................7-12
7.2.2.2 Set on Coprocessor Condition Instruction .......................................7-13
7.2.2.2.1 Format ..........................................................................................7-13
7.2.2.2.2 Protocol........................................................................................7-14
7.2.2.3 Test Coprocessor Condition, Decrement, and Branch Instruction...7-14
7.2.2.3.1 Format ..........................................................................................7-14
7.2.2.3.2 Protocol........................................................................................7-15
7.2.2.4 Trap on Coprocessor Condition Instruction ..................................... 7-15
7.2.2.4.1 Format ..........................................................................................7-15
7.2.2.4.2 Protocol........................................................................................7-16
7.2.3 Coprocessor Context Save and Restore Instructions .........................7-16
7.2.3.1 Coprocessor Internal State Frames.................................................7-17
7.2.3.2 Coprocessor Format Words.............................................................7-18
7.2.3.2.1 Empty/Reset Format Word...........................................................7-18
7.2.3.2.2 Not-Ready Format Word ..............................................................7-19
7.2.3.2.3 Invalid Format Word .....................................................................7-19
7.2.3.2.4 Valid Format Word .......................................................................7-20
7.2.3.3 Coprocessor Context Save Instruction ............................................7-20
7.2.3.3.1 Format ..........................................................................................7-20
7.2.3.3.2 Protocol........................................................................................7-21
7.2.3.4 Coprocessor Context Restore Instruction........................................7-22
7.2.3.4.1 Format ..........................................................................................7-22
7.2.3.4.2 Protocol........................................................................................7-23
7.3 Coprocessor Interface Register Set........................................................7-24

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7.3.1 Response CIR .....................................................................................7-24
7.3.2 Control CIR..........................................................................................7-24
7.3.3 Save CIR .............................................................................................7-25
7.3.4 Restore CIR .........................................................................................7-25
7.3.5 Operation Word CIR ............................................................................7-25
7.3.6 Command CIR.....................................................................................7-25
7.3.7 Condition CIR ......................................................................................7-26
7.3.8 Operand CIR .......................................................................................7-26
7.3.9 Register Select CIR .............................................................................7-27
7.3.10 Instruction Address CIR.......................................................................7-27
7.3.11 Operand Address CIR .........................................................................7-27
7.4 Coprocessor Response Primitives ..........................................................7-27
7.4.1 ScanPC ...............................................................................................7-28
7.4.2 Coprocessor Response Primitive General Format..............................7-28
7.4.3 Busy Primitive ......................................................................................7-30
7.4.4 Null Primitive........................................................................................7-31
7.4.5 Supervisor Check Primitive .................................................................7-33
7.4.6 Transfer Operation Word Primitive ......................................................7-33
7.4.7 Transfer from Instruction Stream Primitive ..........................................7-34
7.4.8 Evaluate and Transfer Effective Address Primitive .............................7-35
7.4.9 Evaluate Effective Address and Transfer Data Primitive.....................7-35
7.4.10 Write to Previously Evaluated Effective Address Primitive..................7-37
7.4.11 Take Address and Transfer Data Primitive..........................................7-39
7.4.12 Transfer to/from Top of Stack Primitive ...............................................7-40
7.4.13 Transfer Single Main Processor Register Primitive .............................7-40
7.4.14 Transfer Main Processor Control Register Primitive ...........................7-41
7.4.15 Transfer Multiple Main Processor Registers Primitive.........................7-42
7.4.16 Transfer Multiple Coprocessor Registers Primitive .............................7-42
7.4.17 Transfer Status Register and ScanPC Primitive..................................7-44
7.4.18 Take Preinstruction Exception Primitive ..............................................7-45
7.4.19 Take Midinstruction Exception Primitive..............................................7-47
7.4.20 Take Postinstruction Exception Primitive ............................................7-48
7.5 Exceptions...............................................................................................7-49
7.5.1 Coprocessor-Detected Exceptions......................................................7-49
7.5.1.1 Coprocessor-Detected Protocol Violations ......................................7-50
7.5.1.2 Coprocessor-Detected Illegal Command or Condition Words .........7-51
7.5.1.3 Coprocessor Data-Processing-Related Exceptions.........................7-51
7.5.1.4 Coprocessor System-Related Exceptions .......................................7-51
7.5.1.5 Format Errors ...................................................................................7-52
7.5.2 Main-Processor-Detected Exceptions .................................................7-52
7.5.2.1 Protocol Violations ...........................................................................7-52
7.5.2.2 F-Line Emulator Exceptions.............................................................7-54

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7.5.2.3 Privilege Violations...........................................................................7-55
7.5.2.4 cpTRAPcc Instruction Traps ............................................................7-55
7.5.2.5 Trace Exceptions .............................................................................7-55
7.5.2.6 Interrupts..........................................................................................7-56
7.5.2.7 Format Errors...................................................................................7-57
7.5.2.8 Address and Bus Errors...................................................................7-57
7.5.3 Coprocessor Reset..............................................................................7-58
7.6 Coprocessor Summary ...........................................................................7-58
Section 8
Instruction Execution Timing
8.1 Timing Estimation Factors ......................................................................8-1
8.1.1 Instruction Cache and Prefetch ...........................................................8-1
8.1.2 Operand Misalignment ........................................................................8-2
8.1.3 Bus/Sequencer Concurrency...............................................................8-2
8.1.4 Instruction Execution Overlap .............................................................8-3
8.1.5 Instruction Stream Timing Examples...................................................8-4
8.2 Instruction Timing Tables........................................................................8-9
8.2.1 Fetch Effective Address ......................................................................8-13
8.2.2 Fetch Immediate Effective Address.....................................................8-14
8.2.3 Calculate Effective Address ................................................................8-16
8.2.4 Calculate Immediate Effective Address...............................................8-17
8.2.5 Jump Effective Address.......................................................................8-19
8.2.6 MOVE Instruction ................................................................................8-20
8.2.7 Special-Purpose MOVE Instruction.....................................................8-29
8.2.8 Arithmetic/Logical Instructions.............................................................8-30
8.2.9 Immediate Arithmetic/Logical Instructions...........................................8-31
8.2.10 Binary-Coded Decimal Operations......................................................8-32
8.2.11 Single-Operand Instructions................................................................8-33
8.2.12 Shift/Rotate Instructions ......................................................................8-34
8.2.13 Bit Manipulation Instructions ...............................................................8-35
8.2.14 Bit Field Manipulation Instructions.......................................................8-36
8.2.15 Conditional Branch Instructions...........................................................8-37
8.2.16 Control Instructions..............................................................................8-38
8.2.17 Exception-Related Instructions............................................................8-39
8.2.18 Save and Restore Operations.............................................................8-40
Section 9
Applications Information
9.1 Floating-Point Units.................................................................................9-1
9.2 Byte Select Logic for the MC68020/EC020.............................................9-5
9.3 Power and Ground Considerations.........................................................9-9

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9.4 Clock Driver.............................................................................................9-10
9.5 Memory Interface ....................................................................................9-11
9.6 Access Time Calculations .......................................................................9-12
9.7 Module Support.......................................................................................9-14
9.7.1 Module Descriptor................................................................................9-14
9.7.2 Module Stack Frame ...........................................................................9-16
9.8 Access Levels .........................................................................................9-17
9.8.1 Module Call..........................................................................................9-18
9.8.2 Module Return .....................................................................................9-19
Section 10
Electrical Characteristics
10.1 Maximum Ratings .................................................................................10-1
10.2 Thermal Considerations ........................................................................10-1
10.2.1 MC68020 Thermal Characteristics and
DC Electrical Characteristics ...........................................................10-2
10.2.2 MC68EC020 Thermal Characteristics and
DC Electrical Characteristics ...........................................................10-4
10.3 AC Electrical Characteristics.................................................................10-5
Section 11
Ordering Information and Mechanical Data
11.1 Standard Ordering Information..............................................................11-1
11.1.1 Standard MC68020 Ordering Information..........................................11-1
11.1.2 Standard MC68EC020 Ordering Information ....................................11-1
11.2 Pin Assignments and Package Dimensions..........................................11-2
11.2.1 MC68020 RC and RP Suffix—Pin Assignment .................................11-2
11.2.2 MC68020 RC Suffix—Package Dimensions ..................................... 11-3
11.2.3 MC68020 RP Suffix—Package Dimensions......................................11-4
11.2.4 MC68020 FC and FE Suffix—Pin Assignment..................................11-5
11.2.5 MC68020 FC Suffix—Package Dimensions......................................11-6
11.2.6 MC68020 FE Suffix—Package Dimensions ......................................11-7
11.2.7 MC68EC020 RP Suffix—Pin Assignment..........................................11-8
11.2.8 MC68EC020 RP Suffix—Package Dimensions.................................11-9
11.2.9 MC68EC020 FG Suffix—Pin Assignment..........................................11-10
11.2.10 MC68EC020 FG Suffix—Package Dimensions.................................11-11
Appendix A
Interfacing an MC68EC020 to a DMA Device That
Supports a Three-Wire Bus Arbitration Protocol

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LIST OF ILLUSTRATIONS
Figure Page
Number Title Number
1-1 MC68020/EC020 Block Diagram .....................................................................1-3
1-2 User Programming Model ................................................................................1-5
1-3 Supervisor Programming Model Supplement ..................................................1-6
1-4 Status Register (SR)........................................................................................1-7
1-5 Instruction Pipe ................................................................................................1-13
2-1 General Exception Stack Frame......................................................................2-6
3-1 Functional Signal Groups.................................................................................3-1
4-1 MC68020/EC020 On-Chip Cache Organization ..............................................4-2
4-2 Cache Control Register....................................................................................4-3
4-3 Cache Address Register..................................................................................4-4
5-1 Relationship between External and Internal Signals........................................5-2
5-2 Input Sample Window ......................................................................................5-2
5-3 Internal Operand Representation.....................................................................5-6
5-4 MC68020/EC020 Interface to Various Port Sizes............................................5-6
5-5 Long-Word Operand Write to Word Port Example...........................................5-10
5-6 Long-Word Operand Write to Word Port Timing..............................................5-11
5-7 Word Operand Write to Byte Port Example .....................................................5-12
5-8 Word Operand Write to Byte Port Timing.........................................................5-13
5-9 Misaligned Long-Word Operand Write to Word Port Example ........................5-14
5-10 Misaligned Long-Word Operand Write to Word Port Timing............................5-15
5-11 Misaligned Long-Word Operand Read from Word Port Example ....................5-16
5-12 Misaligned Word Operand Write to Word Port Example..................................5-16
5-13 Misaligned Word Operand Write to Word Port Timing..................................... 5-17
5-14 Misaligned Word Operand Read from Word Bus Example..............................5-18
5-15 Misaligned Long-Word Operand Write to Long-Word Port Example ...............5-18
5-16 Misaligned Long-Word Operand Write to Long-Word Port Timing ..................5-19
5-17 Misaligned Long-Word Operand Read from Long-Word Port Example...........5-20
5-18 Byte Enable Signal Generation for 16- and 32-Bit Ports..................................5-23
5-19 Long-Word Read Cycle Flowchart...................................................................5-26
5-20 Byte Read Cycle Flowchart..............................................................................5-27
5-21 Byte and Word Read Cycles—32-Bit Port .......................................................5-28
5-22 Long-Word Read—8-Bit Port ...........................................................................5-29
5-23 Long-Word Read—16- and 32-Bit Ports..........................................................5-30