Motorola PowerPC MPC750 User manual

MPC750
Rise Microprocessor User's Manual
MPC750UM/AD
8/97
@ MOTOROLA

~~Pc1g~"t\~!~Ib?~e{:l~\ig~~ Il'J~~:s~ Machines Corp. 1991-1997. All rights reserved.
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Overview
MPC750 Processor Programming Model
L1 Instruction and Data Cache Operation
Exceptions
Memory Management
Instruction Timing
Signal Descriptions
System Interface Operation
L2 Cache Interface Operation
Power and Thermal Management
Performance Monitor
PowerPC Instruction Set Listings _
Instructions Not Implemented _
Glossary of Terms and Abbreviations
..
Index.

Overview
MPC750 Processor Programming Model
L1 Instruction and Data Cache Operation
Exceptions
Memory Management
Instruction Timing
Signal Descriptions
System Interface Operation
L2 Cache Interface Operation
Power and Thermal Management
Performance Monitor
... PowerPC Instruction Set Listings
~ Instructions Not Implemented
III Glossary of Terms and Abbreviations
• Index

Paragraph
Number
1.1
1.2
1.2.1
1.2.2
1.2.2.1
1.2.2.2
1.2.2.3
1.2.2.4
1.2.2.4.1
1.2.2.4.2
1.2.2.4.3
1.2.2.4.4
1.2.3
1.2.4
1.2.5
1.2.6
1.2.7
1.2.8
1.2.9
1.3
1.4
1.5
1.5.1
1.5.2
Contents
CONTENTS
Title Page
Number
Audience ............................................................................................................ xxix
Organization....................................................................................................... xxix
Suggested Reading...............................................................................................xxx
Conventions ..................................................................................................... xxxiii
Acronyms and Abbreviations .......................................................................... xxxiv
Terminology Conventions .............................................................................. xxxvii
Chapter 1
Overview
MPC750 Microprocessor Overview .................................................................... 1-1
MPC750 Microprocessor Features ...................................................................... 1-4
Overview
of the MPC750 Microprocessor Features ....................................... 1-4
Instruction Flow...............................................................................................
1-7
Instruction Queue and Dispatch Unit .......................................................... 1-8
Branch Processing Unit (BPU).................................................................... 1-8
Completion Unit .......................................................................................... 1-9
Independent Execution Units..................................................................... 1-10
Integer Units (IUs)................................................................................. 1-10
Floating-Point Unit (FPU) ..................................................................... 1-10
Load/Store Unit (LSU) .......................................................................... 1-11
System Register Unit (SRU).................................................................. 1-11
Memory Management Units (MMUs) ........................................................... 1-12
On-Chip Instruction and Data Caches ........................................................... 1-13
L2 Cache Implementation (Not Supported in the MPC740) ......................... 1-14
System InterfacelBus Interface Unit (BIU) ................................................... 1-15
Signals............................................................................................................ 1-16
Signal Configuration...................................................................................... 1-17
Clocking......................................................................................................... 1-19
MPC750 Microprocessor: Implementation........................................................ 1-19
PowerPC Registers and Programming Model ...................................................
1-21
Instruction Set.................................................................................................... 1-26
PowerPC Instruction Set................................................................................ 1-27
MPC750 Microprocessor Instruction Set ...................................................... 1-28
iii

Paragraph
Number
CONTENTS
Title Page
Number
1.6 On-Chip Cache Implementation.........................................................................1-29
1.6.1 PowerPC Cache Model...................................................................................1-29
1.6.2 MPC7
SO Microprocessor Cache Implementation ..........................................1-29
1.7 Exception Model.................................................................................................1-29
1.7.1 PowerPC Exception Model ............................................................................
l-29
1.7.2 MPC7S0 Microprocessor Exception Implementation....................................1-31
1.8 Memory Management.........................................................................................1-32
1.8.1 PowerPC Memory Management Model.........................................................1-33
1.8.2 MPC7S0 Microprocessor Memory Management Implementation.................1-33
1.9 Instruction Timing ..............................................................................................1-34
1.10 Power Management............................................................................................1-36
1.11 Thermal Management.........................................................................................1-37
1.12 Performance Monitor..........................................................................................1-38
2.1
2.1.1
2.1.2
2.1.2.1
2.1.2.2
2.1.2.3
2.1.2.4
2.1.2.4.1
2.1.2.4.2
2.1.2.4.3
2.1.2.4.4
2.1.2.4.S
2.1.2.4.6
2.1.2.4.7
2.1.2.4.8
2.1.2.4.9
2.1.3
2.1.4
2.1.5
2.1.6
2.2
2.2.1
2.2.2
2.2.3
iv
Chapter 2
MPC750 Processor Programming Model
The MPC7S0 Processor Register Set....................................................................2-1
Register Set.......................................................................................................2-1
MPC7S0-Specific Registers .............................................................................2-8
Instruction Address Breakpoint Register (IABR) ........................................2-8
Hardware Implementation-Dependent Register 0........................................2-9
Hardware Implementation-Dependent Register 1......................................2-13
Performance Monitor Registers..................................................................2-14
Monitor Mode Control Register 0 (MMCRO)........................................2-14
User Monitor Mode Control Register 0 (UMMCRO) ............................2-1S
Monitor Mode Control Register 1 (MMCRl) ........................................2-16
User Monitor Mode Control Register 1 (UMMCRl) ............................2-16
Performance Monitor Counter Registers (PMC
I-PMC4) .....................2-16
User Performance Monitor Counter Registers (UPMCI-UPMC4).......2-20
Sampled Instruction Address Register (SIA) .........................................2-20
User Sampled Instruction Address Register (USIA)..............................2-20
Sampled Data Address Register (SDA) and User Sampled Data Address
Register (USDA) ....................................................................................2-20
Instruction Cache Throttling Control Register (ICTC) ..................................2-21
Thermal Management Registers
(THRMI-THRM3) ....................................2-21
L2 Cache Control Register (L2CR)................................................................2-24
Reset Settings .................................................................................................2-27
Operand Conventions .........................................................................................2-28
Floating-Point Execution
Models-UISA .....................................................2-28
Data Organization in Memory and Data Transfers ........................................2-28
Alignment and Misaligned Accesses..............................................................2-29
MPC750 RISC Microprocessor User's Manual

Paragraph
Number
2.2.4
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.1.3
2.3.1.4
2.3.2
2.3.2.1
2.3.2.2
2.3.2.3
2.3.2.4
2.3.2.4.1
2.3.2.4.2
2.3.2.4.3
2.3.3
2.3.4
2.3.4.1
2.3.4.1.1
2.3.4.1.2
2.3.4.1.3
2.3.4.1.4
2.3.4.2
2.3.4.2.1
2.3.4.2.2
2.3.4.2.3
2.3.4.2.4
2.3.4.2.5
2.3.4.2.6
2.3.4.3
2.3.4.3.1
2.3.4.3.2
2.3.4.3.3
2.3.4.3.4
2.3.4.3.5
2.3.4.3.6
2.3.4.3.7
2.3.4.3.8
2.3.4.3.9
2.3.4.3.lO
Contents
CONTENTS
Title Page
Number
Floating-Point Operand..................................................................................2-29
Instruction Set Summary....................................................................................
2-31
Classes ofInstmctions....................................................................................2-32
Definition
of Boundedly Undefined ..........................................................2-33
Defined Instmction Class........................................................................... 2-33
Illegal Instmction Class .............................................................................2-33
Reserved Instmction Class......................................................................... 2-34
Addressing Modes..........................................................................................2-35
Memory Addressing...................................................................................2-35
Memory Operands......................................................................................2-35
Effective Address Calculation ...................................................................2-35
Synchronization .........................................................................................2-36
Context Synchronization........................................................................2-36
Execution Synchronization ....................................................................2-36
Instmction-Re1ated Exceptions..............................................................2-37
Instruction Set Overview................................................................................2-37
PowerPC UISA Instmctions ..........................................................................2-38
Integer Instmctions ....................................................................................2-38
Integer Arithmetic Instmctions ..............................................................2-38
Integer Compare Instmctions.................................................................2-39
Integer Logical Instmctions ...................................................................2-40
Integer Rotate and Shift Instmctions .....................................................2-40
Floating-Point Instmctions.........................................................................2-41
Floating-Point Arithmetic Instmctions ..................................................2-42
Floating-Point Multiply-Add Instmctions .............................................2-42
Floating-Point Rounding and Conversion Instmctions..........................2-43
Floating-Point Compare Instmctions .....................................................2-43
Floating-Point Status and Control Register Instmctions .......................2-44
Floating-Point Move Instmctions ..........................................................2-44
Load and Store Instmctions .......................................................................2-45
Self-Modifying Code .............................................................................2-45
Integer Load and Store Address Generation..........................................2-46
Register Indirect Integer Load Instmctions ...........................................2-46
Integer Store Instmctions.......................................................................2-47
Integer Store Gathering..........................................................................2-48
Integer Load and Store with Byte-Reverse Instmctions ........................2-49
Integer Load and Store Multiple Instmctions ........................................2-49
Integer Load and Store String Instmctions ............................................2-50
Floating-Point Load and Store Address Generation ..............................2-51
Floating-Point Store Instmctions ...........................................................
2-51
v

Paragraph
Number
2.3.4.4
2.3.4.4.1
2.3.4.4.2
2.3.4.4.3
2.3.4.4.4
2.3.4.5
2.3.4.6
2.3.4.6.1
2.3.4.6.2
2.3.4.7
2.3.5
2.3.5.1
2.3.5.2
2.3.5.3
2.3.5.3.1
2.3.5.4
2.3.6
2.3.6.1
2.3.6.2
2.3.6.3
2.3.6.3.1
2.3.6.3.2
2.3.6.3.3
2.3.7
3.1
3.2
3.3
3.3.1
3.3.2
3.3.2.1
3.3.3
3.3.4
3.3.5
3.3.5.1
3.3.5.2
3.3.5.3
vi
CONTENTS
Title Page
Number
Branch and Flow Control Instructions .......................................................2-53
Branch Instruction Address Calculation.................................................2-53
Branch Instructions ................................................................................2-54
Condition Register Logical Instructions ................................................2-54
Trap Instructions ....................................................................................2-55
System Linkage
Instruction-UISA ..........................................................2-55
Processor Control
Instructions-UISA ......................................................2-56
Move to/from Condition Register Instructions ......................................2-56
Move to/from Special-Purpose Register Instructions (UISA) ...............2-56
Memory Synchronization
Instructions-UISA ..........................................2-59
PowerPC VEA Instructions............................................................................2-60
Processor Control Instructions- VEA .......................................................2-60
Memory Synchronization Instructions- VEA..............,............................2-61
Memory Control
Instructions- VEA.........................................................2-62
User-Level Cache
Instructions-VEA ...................................................2-62
Optional External Control Instructions ......................................................2-64
PowerPC OEA Instructions............................................................................2-65
System Linkage
Instructions-OEA ..........................................................2-65
Processor Control
Instructions-OEA .......................................................2-65
Memory Control
Instructions-OEA .........................................................2-66
Supervisor-Level Cache Management
Instruction-(OEA) ..................2-66
Segment Register Manipulation Instructions (OEA) .............................2-67
Translation Lookaside Buffer Management Instructions-(OEA) ........2-67
Recommended Simplified Mnemonics ..........................................................2-68
Chapter 3
L1 Instruction and Data Cache Operation
Data Cache Organization......................................................................................3-3
Instruction Cache Organization ............................................................................3-4
Memory and Cache Coherency ............................................................................3-5
Memory/Cache Access Attributes (WIMG Bits) .............................................3-6
MEl Protocol ....................................................................................................3-7
MEl Hardware Considerations.....................................................................3-9
Coherency Precautions in Single Processor Systems.....................................3-10
Coherency Precautions in Multiprocessor Systems .......................................3-10
MPC750-lnitiated Load/Store Operations......................................................
3-10
Performed Loads and Stores....................................................................... 3-11
Sequential Consistency of Memory Accesses............................................3-11
Atomic Memory References ......................................................................
3-11
MPC750 RISC Microprocessor User's Manual

Paragraph
Number
3.4
3.4.1
3.4.1.1
3.4.1.2
3.4.1.3
3.4.1.4
3.4.1.5
3.4.1.6
3.4.2
3.4.2.1
3.4.2.2
3.4.2.3
3.4.2.4
3.4.2.5
3.4.2.6
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.5.1
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.7
3.8
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
Contents
CONTENTS
Title Page
Number
Cache ControL...................................................................................................3-13
Cache Control Parameters in
HIDO ................................................................3-13
Data Cache Flash Invalidation ...................................................................3-13
Data Cache Enabling/Disabling .................................................................3-13
Data Cache Locking...................................................................................3-14
Instruction Cache Flash Invalidation .........................................................3-14
Instruction Cache Enabling/Disabling .......................................................3-14
Instruction Cache Locking .........................................................................3-15
Cache Control Instructions............................................................................. 3-15
Data Cache Block Touch (debt) and
Data Cache Block Touch for Store (debtst)..........................................3-15
Data Cache Block Zero (debz) ..................................................................3-16
Data Cache Block Store (debst) ................................................................3-16
Data Cache Block Flush
(debt') .................................................................3-17
Data Cache Block Invalidate (debi)........................................................... 3-17
Instruction Cache Block Invalidate (icbi)..................................................3-17
Cache Operations ...............................................................................................3-18
Cache Block Replacement/Castout Operations .............................................3-18
Cache Flush Operations .................................................................................
3-21
Data Cache-Block-Fill Operations.................................................................3-21
Instruction Cache-Block-Fill Operations .......................................................3-21
Data Cache-Block-Push Operation ................................................................3-22
Enveloped High-Priority Cache-Block-Push Operation............................3-22
Ll Caches and 60x Bus Transactions ................................................................3-22
Read Operations and the MEl Protocol .........................................................3-23
Bus Operations Caused by Cache Control Instructions .................................3-24
Snooping ........................................................................................................3-25
Snoop Response to 60x Bus Transactions ..................................................... 3-26
Transfer Attributes .........................................................................................3-28
Bus Interface ......................................................................................................
3- 30
MEl State Transactions ......................................................................................3-32
Chapter 4
Exceptions
MPC750 Microprocessor Exceptions...................................................................4-2
Exception Recognition and Priorities...................................................................4-4
Exception Processing ...........................................................................................4-7
Enabling and Disabling Exceptions ...............................................................4-10
Steps for Exception Processing......................................................................4-10
Setting MSR[RI] ............................................................................................4-11
Returning from an Exception Handler ...........................................................4-11
vii

Paragraph
Number
4.4
4.5
4.5.1
4.5.2
4.5.2.1
4.5.2.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
4.5.9
4.5.10
4.5.11
4.5.12
4.5.13
4.5.14
4.5.15
4.5.16
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.6.1
5.1.6.2
5.1.7
5.1.8
5.2
5.3
5.4
5.4.1
5.4.1.1
5.4.1.2
5.4.1.3
viii
CONTENTS
Title Page
Number
Process Switching...............................................................................................4-12
Exception Definitions.........................................................................................4-12
System Reset Exception (OxOOl00)................................................................4-13
Machine
Check Exception (Ox00200) ............................................................4-14
Machine Check Exception Enabled (MSR[ME] =1) ................................4-16
Checkstop State (MSR[ME] = 0) ...............................................................4-16
DSI Exception (Ox00300)...............................................................................4-17
lSI Exception (Ox00400) ................................................................................4-17
External Interrupt Exception (Ox00500).........................................................4-17
Alignment Exception (Ox00600) .............,......................................................4-18
Program Exception (Ox00700) .......................................................................4-18
Floating-Point Unavailable Exception (Ox00800) ..........................................4-19
Decrementer Exception (Ox00900).................................................................4-19
System Call Exception (OxOOCOO) .................................................................4-19
Trace Exception
(OxOODOO) ...........................................................................4-19
Floating-Point Assist Exception
(OxOOEOO) ...................................................4-20
Performance
Monitor Interrupt (OxOOFOO) .....................................................4-20
Instruction Address Breakpoint Exception (Ox01300) ...................................4-21
System Management Interrupt (Ox01400)......................................................4-22
Thermal Management Interrupt Exception (Ox01700) ...................................4-24
Chapter 5
Memory Management
MMU Overview ...................................................................................................5-2
Memory Addressing .........................................................................................5-4
MMU Organization ..........................................................................................5-4
Address Translation Mechanisms.......................
,..................... '" .....................5-9
Memory Protection Facilities .........................................................................5-11
Page History Information ...............................................................................5-12
General
Flow ofMMU Address Translation..................................................5-12
Real Addressing
Mode and Block Address Translation Selection.............5-12
Page Address Translation Selection...........................................................5-14
MMU Exceptions Summary...........................................................................5-16
MMU Instructions and Register Summary.....................................................5-18
Real Addressing
Mode .......................................................................................5-20
Block Address Translation .................................................................................5-21
Memory Segment Model ....................................................................................5-21
Page History Recording..................................................................................5-21
Referenced
Bit ............................................................................................5-22
Changed Bit ................................................................................................5-23
Scenarios for Referenced and Changed Bit Recording..............................5-23
MPC750 RISC Microprocessor User's Manual

Paragraph
Number
5.4.2
5.4.3
5.4.3.1
5.4.3.2
5.4.4
5.4.5
5.4.6
5.4.7
6.1
6.2
6.3
6.3.1
6.3.2
6.3.2.1
6.3.2.2
6.3.2.3
6.3.2.4
6.3.3
6.3.3.1
6.3.3.2
6.4
6.4.1
6.4.1.1
6.4.1.2
6.4.l.3
6.4.l.3.1
6.4.l.3.2
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.5
6.5.1
6.5.2
Contents
CONTENTS
Title Page
Number
Page Memory Protection................................................................................5-25
TLB Description.............................................................................................5-25
TLB Organization ......................................................................................5-25
TLB Invalidation........................................................................................5-27
Page Address Translation Summary ..............................................................5-28
Page Table Search Operation.........................................................................5-30
Page Table Updates........................................................................................5-34
Segment Register Updates .............................................................................5-34
Chapter 6
Instruction Timing
Terminology and Conventions.............................................................................6-1
Instruction Timing Overview ...............................................................................6-3
Timing Considerations .........................................................................................6-7
General Instruction Flow..................................................................................6-8
Instruction Fetch Timing................................................................................6-11
Cache Arbitration.......................................................................................6-11
Cache Hit....................................................................................................6-11
Cache Miss.................................................................................................6-14
L2 Cache Access Timing Considerations (MPC750 Only) .......................6-15
Instruction Dispatch and Completion Considerations....................................6-16
Rename Register Operation .......................................................................6-17
Instruction Serialization.............................................................................6-17
Execution Unit Timings .....................................................................................6-18
Branch Processing Unit Execution Timing....................................................6-18
Branch Folding and Removal
of Fall-Through Branch Instructions .........6-18
Branch Instructions and Completion..........................................................6-20
Branch Prediction and Resolution..............................................................6-21
Static Branch Prediction ........................................................................6-22
Predicted Branch Timing Examples ......................................................6-22
Integer Unit Execution Timing ......................................................................6-24
Floating-Point Unit Execution Timing...........................................................6-24
Effect
of Floating-Point Exceptions on Performance ....................................6-25
Load/Store Unit Execution Timing................................................................6-25
Effect
of Operand Placement on Performance...............................................6- 25
Integer Store Gathering..................................................................................6-26
System Register Unit Execution Timing........................................................6-27
Memory Performance Considerations................................................................6-27
Caching and Memory Coherency...................................................................6-27
Effect
ofTLB Miss ........................................................................................6-28
ix

Paragraph
Number
6.6
6.6.1
6.6.1.1
6.6.1.2
6.6.1.3
6.7
7.1
7.2
7.2.1
7.2.1.1
7.2.1.2
7.2.1.3
7.2.1.3.1
7.2.1.3.2
7.2.2
7.2.2.1
7.2.2.1.1
7.2.2.1.2
7.2.3
7.2.3.1
7.2.3.1.1
7.2.3.1.2
7.2.3.2
7.2.3.2.1
7.2.3.2.2
7.2.4
7.2.4.1
7.2.4.1.1
7.2.4.1.2
7.2.4.2
7.2.4.3
7.2.4.3.1
7.2.4.3.2
7.2.4.4
7.2.4.5
7.2.4.6
7.2.4.6.1
7.2.4.6.2
x
CONTENTS
Title Page
Number
Instruction Scheduling Guidelines......................................................................6-29
Branch, Dispatch, and Completion Unit Resource Requirements .................6-29
Branch Resolution Resource Requirements ...............................................6-30
Dispatch Unit Resource Requirements.......................................................6-30
Completion Unit Resource Requirements..................................................6-30
Instruction Latency Summary ............................................................................6-31
Chapter 7
Signal Descriptions
Signal Configuration.........................,...................................................................7-3
Signal Descriptions...............................................................................................7-4
Address Bus Arbitration Signals ......................................................................7-4
Bus Request (BR)-Output ..........................................................................7-4
Bus Grant
(BG)-Input ................................................................................7-4
Address Bus Busy (ABB) .............................................................................7-5
Address Bus Busy (ABB)-Output..........................................................7-5
Address Bus Busy (ABB)-Input ............................................................7-5
Address Transfer Start Signals .........................................................................7-6
Transfer Start (TS)........................................................................................7-6
Transfer Start (TS)-Output. ....................................................................7-6
Transfer Start
(TS)-Input .......................................................................7-6
Address Transfer Signals..................................................................................7-6
Address Bus (A[0-31]) ................................................................................7-7
Address Bus
(A[0-31])-Output .............................................................7-7
Address Bus
(A[0-31])-Input ................................................................7-7
Address Bus Parity (AP[0-3])......................................................................7-7
Address Bus Parity
(AP[0-3])-Output ..................................................7-7
Address Bus Parity (AP[0-3])-Input .....................................................7-8
Address Transfer Attribute Signals ..................................................................7-8
Transfer Type (TT[O-4]) ..............................................................................7-8
Transfer Type (TT[O-4])-Output...........................................................7-8
Transfer Type (TT[O-4])-Input..............................................................7-8
Transfer Size (TSIZ[0-2])-Output...........................................................7-11
Transfer Burst (TBST)................................................................................7-12
Transfer Burst
(TBST)-Output ............................................................7-12
Transfer Burst
(TBST)-Input ...............................................................7-12
Cache Inhibit (CI)-Output .......................................................................7-12
Write-Through (WT)-Output... ................................................................7-13
Global (GBL)..............................................................................................7-13
Global
(GBL)-Output ..........................................................................7-13
Global (GBL)-Input .............................................................................7-13
MPC750 RISC Microprocessor User's Manual

Paragraph
Number
7.2.5
7.2.5.1
7.2.5.2
7.2.5.2.1
7.2.5.2.2
7.2.6
7.2.6.1
7.2.6.2
7.2.6.3
7.2.6.3.1
7.2.6.3.2
7.2.7
7.2.7.1
7.2.7.1.1
7.2.7.1.2
7.2.7.2
7.2.7.2.1
7.2.7.2.2
7.2.7.3
7.2.8
7.2.8.1
7.2.8.2
7.2.8.3
7.2.9
7.2.9.1
7.2.9.2
7.2.9.3
7.2.9.4
7.2.9.5
7.2.9.6
7.2.9.6.1
7.2.9.6.2
7.2.9.7
7.2.9.7.1
7.2.9.7.2
7.2.9.7.3
7.2.9.7.4
7.2.9.7.5
7.2.9.7.6
7.2.9.8
7.2.9.9
7.2.9.9.1
7.2.9.9.2
Contents
CONTENTS
Title Page
Number
Address Transfer Tennination Signals...........................................................7-13
Address Acknowledge
(AACK)-Input ...................................................7-14
Address Retry (ARTRY) ...........................................................................7-14
Address Retry (ARTRY)-Output........................................................7-14
Address Retry (ARTRY)-Input ...........................................................7-15
Data Bus Arbitration Signals .........................................................................7-15
Data Bus Grant (DBG)-Input ..................................................................7-15
Data Bus Write Only (DBWO)-Input... ..................................................7-16
Data Bus Busy (DBB) ................................................................................7-16
Data Bus Busy (DBB)-Output.............................................................7-16
Data Bus Busy (DBB)-Input................................................................7-16
Data Transfer Signals.....................................................................................7-17
Data Bus (DH[0-31], DL[0-31])...............................................................7-17
Data Bus (DH[0-31], DL[0-31])-Output............................................7-17
Data Bus (DH[0-31], DL[0-31])-Input ..............................................7-18
Data Bus Parity (DP[0-7]).........................................................................7-18
Data Bus Parity (DP[0-7])-Output......................................................7-18
Data Bus Parity
(DP[0-7])-Input ........................................................7-18
Data Bus Disable
(DBDIS)-Input ...........................................................7-19
Data Transfer Termination Signals ................................................................7-19
Transfer Acknowledge (TA)-Input .........................................................7-19
Data Retry (DRTRY)-Input.....................................................................7-20
Transfer Error Acknowledge (TEA)-Input .............................................7-20
System Status Signals ....................................................................................7-21
Interrupt (INT)-Input ..............................................................................7-21
System Management Interrupt (SMI)-Input............................................7 -21
Machine Check Interrupt (MCP)-Input ..................................................7-21
Checkstop Input (CKSTP
IN)-Input.. ....................................................7-22
Checkstop Output (CKSTP _OUT)-Output ............................................7-22
Reset Signals ..............................................................................................7-23
Hard Reset (HRESET)-Input ..............................................................7-23
Soft Reset (SRESET)-Input.................................................................7-23
Processor Status Signals.............................................................................7-23
Quiescent Request
(QREQ)-Output. ...................................................7-24
Quiescent Acknowledge (QACK)-Input ............................................7-24
Reservation (RSRV)-Output ...............................................................7-24
Time Base Enable (TBEN)-Input........................................................7-24
TLBI Sync (TLBISYNC)-Input...............................,..........................7-25
L2 Cache Interface.................................................................................7- 25
L2 Address (L2ADDR[16--0])-Output....................................................7-25
L2 Data (L2DATA[0-63]).........................................................................7-25
L2 Data (L2DATA[0-63])-Output......................................................7-25
L2 Data (L2DATA[0-63])-Input ........................................................7-26
xi

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Number
7.2.9.10
7.2.9.10.1
7.2.9.10.2
7.2.9.11
7.2.9.12
7.2.9.13
7.2.9.14
7.2.9.15
7.2.9.16
7.2.9.17
7.2.10
7.2.11
7.2.11.1
7.2.11.2
7.2.11.3
7.2.12
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.3.2.1
8.3.2.2
8.3.2.2.1
8.3.2.2.2
8.3.2.2.3
8.3.2.2.4
8.3.2.3
8.3.2.4
8.3.2.4.1
8.3.3
xii
CONTENTS
Title Page
Number
L2 Data Parity (L2DP[0-7]).......................................................................7-26
L2 Data Parity (L2DP[0-7])-Output ...................................................7-26
L2 Data Parity
(L2DP[0-7])-Input ......................................................7-26
L2 Chip Enable
(L2CE)-Output ..............................................................7-26
L2 Write Enable
(L2WE)-Output ............................................................7-27
L2 Clock Out A (L2CLK_OUTA)-Output..............................................7-27
L2 Clock Out B (L2CLK_OUTB)-Output..............................................7-27
L2 Sync Out (L2SYNC_OUT)-Output ...................................................7-27
L2 Sync In (L2SYNC_IN)-Input.............................................................7-28
L2 Low-Power Mode Enable (L2ZZ)-Output .........................................7-28
IEEE 1149.1a-1993 Interface Description .....................................................7-28
Clock Signals..................................................................................................7-29
System Clock
(SYSCLK)-Input ..............................................................7-29
Clock Out
(CLK_OUT)-Output ..............................................................7-29
PLL Configuration (PLL_CFG[0-3])-Input............................................7-30
Power and Ground Signals .............................................................................7-30
Chapter 8
System Interface Operation
MPC750 System Interface Overview................................................................... 8-1
Operation of the Instruction and Data Ll Caches ............................................8-2
Operation of the L2 Cache ...............................................................................8-4
Operation
of the System Interface....................................................................8-4
Direct-Store Accesses.......................................................................................8-5
Memory Access Protocol......................................................................................8-6
Arbitration Signals............................................................................................8-8
Address Pipelining and Split-Bus Transactions ...............................................8-9
Address Bus Tenure............................................................................................
8-10
Address Bus Arbitration.................................................................................8-10
Address Transfer ............................................................................................8-12
Address Bus Parity .....................................................................................8-13
Address Transfer Attribute Signals ............................................................8-13
Transfer Type (TT[0-4]) Signals ...........................................................8-13
Transfer Size (TSIZ[0-2]) Signals.........................................................8-13
Write-Through (WT) Signal...................................................................8-14
Cache Inhibit (CI) Signal .......................................................................8-14
Burst Ordering During Data Transfers.......................................................8-15
Effect
of Alignment in Data Transfers .......................................................8-15
Alignment of External Control Instructions...........................................8-17
Address Transfer Termination........................................................................8-17
MPC750 RISC Microprocessor User's Manual

Paragraph
Number
8.4
8.4.1
8.4.1.1
8.4.2
8.4.3
8.4.4
8.4.4.1
8.4.4.2
8.4.5
8.5
8.6
8.6.1
8.7
8.7.1
8.7.2
8.7.3
8.7.4
8.8
8.8.1
8.8.2
8.9
8.9.1
8.10
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.5.1
9.1.5.2
9.1.6
9.1.7
9.1.7.1
9.1.7.2
9.1.7.3
Contents
CONTENTS
Title Page
Number
Data Bus Tenure.................................................................................................8-19
Data Bus Arbitration ......................................................................................8-19
Using the DBB Signal................................................................................8-20
Data Bus Write Only...................................................................................... 8-21
Data Transfer..................................................................................................8-
21
Data Transfer Termination............................................................................. 8-22
Normal Single-Beat Termination...............................................................8-22
Data Transfer Termination Due to a Bus Error..........................................8-26
Memory
Coherency-MEl Protocol..............................................................8-26
Timing Examples ...............................................................................................8-28
Optional Bus Configuration...............................................................................8-34
No-DRTRY Mode..........................................................................................8-34
Interrupt, Checkstop, and Reset Signals.............................................................8-35
External Interrupts..........................................................................................8-35
Checkstops .....................................................................................................8-35
Reset Inputs....................................................................................................8-35
System Quiesce Control Signals ....................................................................8-35
Processor State Signals.......................................................................................8-36
Support for the lwarxlstwcx. Instruction Pair ...............................................8-36
TLBISYNC Input...........................................................................................8-36
IEEE 1149.1a-1993 Compliant Interface...........................................................8-37
JTAG/COP Interface......................................................................................8-37
Using Data Bus Write Only ...............................................................................8-37
Chapter 9
L2 Cache Interface Operation
L2 Cache Interface Overview ..............................................................................9-1
L2 Cache Operation .........................................................................................9-2
L2 Cache Control Register (L2CR) .................................................................9-4
L2 Cache Initialization.....................................................................................9-6
L2 Cache Global Invalidation..........................................................................9-7
L2 Cache Test Features and Methods ..............................................................9-7
L2CR Support for L2 Cache Testing ...........................................................9-7
L2 Cache Testing .........................................................................................9-8
L2 Clock Configuration ...................................................................................9-9
L2 Cache SRAM Timing Examples ................................................................9-9
Flow-Through Burst SRAM ........................................................................9-9
Pipelined Burst SRAM...............................................................................9-11
Late-Write SRAM......................................................................................9-12
xiii

Paragraph
Number
10.1
10.2
10.2.1
10.2.1.1
10.2.1.2
10.2.1.3
10.2.1.4
10.2.1.5
10.2.2
10.3
10.3.1
10.3.2
10.3.2.1
10.3.2.2
10.3.2.3
10.3.2.4
10.4
11.1
11.2
11.2.1
11.2.1.1
11.2.1.2
11.2.1.3
11.2.1.4
11.2.1.5
11.2.1.6
11.2.1.7
11.2.1.8
11.3
11.4
11.5
xiv
CONTENTS
Title
Chapter 10
Power and Thermal Management
Page
Number
Dynamic Power Management ............................................................................10-1
Programmable Power Modes..............................................................................10-1
Power Management Modes ............................................................................10-2
Full-Power Mode with DPM Disabled.......................................................10-2
Full-Power Mode with DPM Enabled........................................................10-2
Doze Mode .................................................................................................10-3
Nap Mode...................................................................................................10-3
Sleep Mode.................................................................................................10-4
Power Management Software Considerations................................................10-5
Thermal Assist Unit............................................................................................10-6
Thermal Assist Unit Overview.......................................................................10-6
Thermal Assist Unit Operation.......................................................................10-8
TAU Single Threshold Mode.....................................................................10-8
TAU Dual-Threshold Mode .......................................................................10-9
MPC750 Junction Temperature Determination .......................................10-10
Power Saving Modes and TAU Operation...............................................10-10
Instruction Cache Throttling.............................................................................l0-10
Chapter 11
Performance Monitor
Performance Monitor Interrupt...........................................................................11-2
Special-Purpose Registers Used by Performance Monitor.................................11-3
Performance Monitor Registers......................................................................11-3
Monitor Mode Control Register 0 (MMCRO) ............................................11-3
User Monitor Mode Control Register 0 (UMMCRO) ................................11-5
Monitor Mode Control Register 1 (MMCRl)............................................11-5
User Monitor Mode Control Register 1 (UMMCRl) ................................11-6
Performance Monitor Counter Registers (PMCI-PMC4) .........................11-6
User Performance Monitor Counter Registers (UPMC1-UPMC4).........11-10
Sampled Instruction Address Register (SIA) ...........................................11-10
User Sampled Instruction Address Register (USIA)................................11-10
Event Counting.................................................................................................11-11
Event Selection.................................................................................................11-12
Warnings...........................................................................................................11-12
MPC750 RISC Microprocessor User's Manual

Paragraph
Number
CONTENTS
Title
Appendix A
PowerPC Instruction Set Listings
Page
Number
A.I Instructions Sorted by Mnemonic .......................................................................A-I
A.2 Instructions Sorted by Opcode .....................:...................................................... A-9
A.3 Instructions Grouped
by Functional Categories................................................ A-I7
AA Instructions Sorted by Form.............................................................................. A-29
A.5 Instruction Set Legend ......................................................................................A-4I
Contents
Appendix B
Instructions Not Implemented
Glossary of Terms and Abbreviations
xv

xvi MPC750 RISC Microprocessor User's Manual

Figure
Number
1-1
1-2
1-3
1-4
1-5
1-6
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
3-1
3-2
3-3
3-4
3-5
3-6
3-7
4-1
4-2
4-3
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
Illustrations
ILLUSTRATIONS
Title Page
Number
MPC750 Microprocessor Block Diagram ........................................................... 1-3
Cache Organization............................................................................................ 1-13
System Interface................................................................................................. 1-16
MPC750 Microprocessor Signal Groups ........................................................... 1-18
MPC750 Microprocessor Programming
Model-Registers .............................. 1-23
Pipeline Diagram ............................................................................................... 1-34
Programming
Model-MPC750 Microprocessor Registers................................ 2-2
Instruction Address Breakpoint Register............................................................. 2-9
Hardware Implementation-Dependent Register 0 (HIDO)................................... 2-9
Hardware Implementation-Dependent Register 1 (HID
1) ................................. 2-13
Monitor Mode Control Register 0 (MMCRO) ................................................... 2-14
Monitor Mode Control Register 1
(MMCRl) ................................................... 2-16
Performance Monitor Counter Registers
(PMCl-PMC4) ................................. 2-16
Sampled instruction Address Registers (SIA) ................................................... 2-20
Instruction Cache Throttling Control Register (ICTC)...................................... 2-21
Thermal Management Registers
1-2 (THRMl-THRM2) ................................ 2-22
Thermal Management Register 3 (THRM3)...................................................... 2-23
L2 Cache Control Register (L2CR) ................................................................... 2-24
Cache Integration................................................................................................. 3-2
Data Cache Organization..................................................................................... 3-4
Instruction Cache Organization ........................................................................... 3-5
MEl Cache Coherency Protocol-State Diagram (WIM == 00l) ......................... 3-8
PLRU Replacement Algorithm.......................................................................... 3-19
Double-Word Address
Ordering-Critical Double Word First......................... 3-23
Bus Interface Address Buffers........................................................................... 3-31
Machine Status SaveIRestore Register 0
(SRRO) ................................................ 4-7
Machine Status SaveIRestore Register 1 (SRRl) ................................................ 4-7
Machine State Register (MSR) ............................................................................ 4-8
MMU Conceptual Block Diagram-32-Bit Implementations............................. 5-6
MPC750 Microprocessor IMMU Block Diagram............................................... 5-7
MPC750 Microprocessor DMMU Block Diagram.............................................. 5-8
Address Translation Types ................................................................................ 5-10
General Flow
of Address Translation (Real Addressing Mode and Block) ...... 5-13
General Flow of Page and Direct-Store Interface Address Translation ............ 5-15
Segment Register and DTLB Organization ....................................................... 5-26
Page Address Translation
Flow- TLB Hit........................................................ 5-29
xvii