Motorola PowerPC MPC750 User manual

MPC750
Rise Microprocessor User's Manual
MPC750UM/AD
8/97
@ MOTOROLA

~~Pc1g~"t\~!~Ib?~e{:l~\ig~~ Il'J~~:s~ Machines Corp. 1991-1997. All rights reserved.
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Overview
MPC750 Processor Programming Model
L1 Instruction and Data Cache Operation
Exceptions
Memory Management
Instruction Timing
Signal Descriptions
System Interface Operation
L2 Cache Interface Operation
Power and Thermal Management
Performance Monitor
PowerPC Instruction Set Listings _
Instructions Not Implemented _
Glossary of Terms and Abbreviations
..
Index.

Overview
MPC750 Processor Programming Model
L1 Instruction and Data Cache Operation
Exceptions
Memory Management
Instruction Timing
Signal Descriptions
System Interface Operation
L2 Cache Interface Operation
Power and Thermal Management
Performance Monitor
... PowerPC Instruction Set Listings
~ Instructions Not Implemented
III Glossary of Terms and Abbreviations
• Index

Paragraph
Number
1.1
1.2
1.2.1
1.2.2
1.2.2.1
1.2.2.2
1.2.2.3
1.2.2.4
1.2.2.4.1
1.2.2.4.2
1.2.2.4.3
1.2.2.4.4
1.2.3
1.2.4
1.2.5
1.2.6
1.2.7
1.2.8
1.2.9
1.3
1.4
1.5
1.5.1
1.5.2
Contents
CONTENTS
Title Page
Number
Audience ............................................................................................................ xxix
Organization....................................................................................................... xxix
Suggested Reading...............................................................................................xxx
Conventions ..................................................................................................... xxxiii
Acronyms and Abbreviations .......................................................................... xxxiv
Terminology Conventions .............................................................................. xxxvii
Chapter 1
Overview
MPC750 Microprocessor Overview .................................................................... 1-1
MPC750 Microprocessor Features ...................................................................... 1-4
Overview
of the MPC750 Microprocessor Features ....................................... 1-4
Instruction Flow...............................................................................................
1-7
Instruction Queue and Dispatch Unit .......................................................... 1-8
Branch Processing Unit (BPU).................................................................... 1-8
Completion Unit .......................................................................................... 1-9
Independent Execution Units..................................................................... 1-10
Integer Units (IUs)................................................................................. 1-10
Floating-Point Unit (FPU) ..................................................................... 1-10
Load/Store Unit (LSU) .......................................................................... 1-11
System Register Unit (SRU).................................................................. 1-11
Memory Management Units (MMUs) ........................................................... 1-12
On-Chip Instruction and Data Caches ........................................................... 1-13
L2 Cache Implementation (Not Supported in the MPC740) ......................... 1-14
System InterfacelBus Interface Unit (BIU) ................................................... 1-15
Signals............................................................................................................ 1-16
Signal Configuration...................................................................................... 1-17
Clocking......................................................................................................... 1-19
MPC750 Microprocessor: Implementation........................................................ 1-19
PowerPC Registers and Programming Model ...................................................
1-21
Instruction Set.................................................................................................... 1-26
PowerPC Instruction Set................................................................................ 1-27
MPC750 Microprocessor Instruction Set ...................................................... 1-28
iii

Paragraph
Number
CONTENTS
Title Page
Number
1.6 On-Chip Cache Implementation.........................................................................1-29
1.6.1 PowerPC Cache Model...................................................................................1-29
1.6.2 MPC7
SO Microprocessor Cache Implementation ..........................................1-29
1.7 Exception Model.................................................................................................1-29
1.7.1 PowerPC Exception Model ............................................................................
l-29
1.7.2 MPC7S0 Microprocessor Exception Implementation....................................1-31
1.8 Memory Management.........................................................................................1-32
1.8.1 PowerPC Memory Management Model.........................................................1-33
1.8.2 MPC7S0 Microprocessor Memory Management Implementation.................1-33
1.9 Instruction Timing ..............................................................................................1-34
1.10 Power Management............................................................................................1-36
1.11 Thermal Management.........................................................................................1-37
1.12 Performance Monitor..........................................................................................1-38
2.1
2.1.1
2.1.2
2.1.2.1
2.1.2.2
2.1.2.3
2.1.2.4
2.1.2.4.1
2.1.2.4.2
2.1.2.4.3
2.1.2.4.4
2.1.2.4.S
2.1.2.4.6
2.1.2.4.7
2.1.2.4.8
2.1.2.4.9
2.1.3
2.1.4
2.1.5
2.1.6
2.2
2.2.1
2.2.2
2.2.3
iv
Chapter 2
MPC750 Processor Programming Model
The MPC7S0 Processor Register Set....................................................................2-1
Register Set.......................................................................................................2-1
MPC7S0-Specific Registers .............................................................................2-8
Instruction Address Breakpoint Register (IABR) ........................................2-8
Hardware Implementation-Dependent Register 0........................................2-9
Hardware Implementation-Dependent Register 1......................................2-13
Performance Monitor Registers..................................................................2-14
Monitor Mode Control Register 0 (MMCRO)........................................2-14
User Monitor Mode Control Register 0 (UMMCRO) ............................2-1S
Monitor Mode Control Register 1 (MMCRl) ........................................2-16
User Monitor Mode Control Register 1 (UMMCRl) ............................2-16
Performance Monitor Counter Registers (PMC
I-PMC4) .....................2-16
User Performance Monitor Counter Registers (UPMCI-UPMC4).......2-20
Sampled Instruction Address Register (SIA) .........................................2-20
User Sampled Instruction Address Register (USIA)..............................2-20
Sampled Data Address Register (SDA) and User Sampled Data Address
Register (USDA) ....................................................................................2-20
Instruction Cache Throttling Control Register (ICTC) ..................................2-21
Thermal Management Registers
(THRMI-THRM3) ....................................2-21
L2 Cache Control Register (L2CR)................................................................2-24
Reset Settings .................................................................................................2-27
Operand Conventions .........................................................................................2-28
Floating-Point Execution
Models-UISA .....................................................2-28
Data Organization in Memory and Data Transfers ........................................2-28
Alignment and Misaligned Accesses..............................................................2-29
MPC750 RISC Microprocessor User's Manual

Paragraph
Number
2.2.4
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.1.3
2.3.1.4
2.3.2
2.3.2.1
2.3.2.2
2.3.2.3
2.3.2.4
2.3.2.4.1
2.3.2.4.2
2.3.2.4.3
2.3.3
2.3.4
2.3.4.1
2.3.4.1.1
2.3.4.1.2
2.3.4.1.3
2.3.4.1.4
2.3.4.2
2.3.4.2.1
2.3.4.2.2
2.3.4.2.3
2.3.4.2.4
2.3.4.2.5
2.3.4.2.6
2.3.4.3
2.3.4.3.1
2.3.4.3.2
2.3.4.3.3
2.3.4.3.4
2.3.4.3.5
2.3.4.3.6
2.3.4.3.7
2.3.4.3.8
2.3.4.3.9
2.3.4.3.lO
Contents
CONTENTS
Title Page
Number
Floating-Point Operand..................................................................................2-29
Instruction Set Summary....................................................................................
2-31
Classes ofInstmctions....................................................................................2-32
Definition
of Boundedly Undefined ..........................................................2-33
Defined Instmction Class........................................................................... 2-33
Illegal Instmction Class .............................................................................2-33
Reserved Instmction Class......................................................................... 2-34
Addressing Modes..........................................................................................2-35
Memory Addressing...................................................................................2-35
Memory Operands......................................................................................2-35
Effective Address Calculation ...................................................................2-35
Synchronization .........................................................................................2-36
Context Synchronization........................................................................2-36
Execution Synchronization ....................................................................2-36
Instmction-Re1ated Exceptions..............................................................2-37
Instruction Set Overview................................................................................2-37
PowerPC UISA Instmctions ..........................................................................2-38
Integer Instmctions ....................................................................................2-38
Integer Arithmetic Instmctions ..............................................................2-38
Integer Compare Instmctions.................................................................2-39
Integer Logical Instmctions ...................................................................2-40
Integer Rotate and Shift Instmctions .....................................................2-40
Floating-Point Instmctions.........................................................................2-41
Floating-Point Arithmetic Instmctions ..................................................2-42
Floating-Point Multiply-Add Instmctions .............................................2-42
Floating-Point Rounding and Conversion Instmctions..........................2-43
Floating-Point Compare Instmctions .....................................................2-43
Floating-Point Status and Control Register Instmctions .......................2-44
Floating-Point Move Instmctions ..........................................................2-44
Load and Store Instmctions .......................................................................2-45
Self-Modifying Code .............................................................................2-45
Integer Load and Store Address Generation..........................................2-46
Register Indirect Integer Load Instmctions ...........................................2-46
Integer Store Instmctions.......................................................................2-47
Integer Store Gathering..........................................................................2-48
Integer Load and Store with Byte-Reverse Instmctions ........................2-49
Integer Load and Store Multiple Instmctions ........................................2-49
Integer Load and Store String Instmctions ............................................2-50
Floating-Point Load and Store Address Generation ..............................2-51
Floating-Point Store Instmctions ...........................................................
2-51
v

Paragraph
Number
2.3.4.4
2.3.4.4.1
2.3.4.4.2
2.3.4.4.3
2.3.4.4.4
2.3.4.5
2.3.4.6
2.3.4.6.1
2.3.4.6.2
2.3.4.7
2.3.5
2.3.5.1
2.3.5.2
2.3.5.3
2.3.5.3.1
2.3.5.4
2.3.6
2.3.6.1
2.3.6.2
2.3.6.3
2.3.6.3.1
2.3.6.3.2
2.3.6.3.3
2.3.7
3.1
3.2
3.3
3.3.1
3.3.2
3.3.2.1
3.3.3
3.3.4
3.3.5
3.3.5.1
3.3.5.2
3.3.5.3
vi
CONTENTS
Title Page
Number
Branch and Flow Control Instructions .......................................................2-53
Branch Instruction Address Calculation.................................................2-53
Branch Instructions ................................................................................2-54
Condition Register Logical Instructions ................................................2-54
Trap Instructions ....................................................................................2-55
System Linkage
Instruction-UISA ..........................................................2-55
Processor Control
Instructions-UISA ......................................................2-56
Move to/from Condition Register Instructions ......................................2-56
Move to/from Special-Purpose Register Instructions (UISA) ...............2-56
Memory Synchronization
Instructions-UISA ..........................................2-59
PowerPC VEA Instructions............................................................................2-60
Processor Control Instructions- VEA .......................................................2-60
Memory Synchronization Instructions- VEA..............,............................2-61
Memory Control
Instructions- VEA.........................................................2-62
User-Level Cache
Instructions-VEA ...................................................2-62
Optional External Control Instructions ......................................................2-64
PowerPC OEA Instructions............................................................................2-65
System Linkage
Instructions-OEA ..........................................................2-65
Processor Control
Instructions-OEA .......................................................2-65
Memory Control
Instructions-OEA .........................................................2-66
Supervisor-Level Cache Management
Instruction-(OEA) ..................2-66
Segment Register Manipulation Instructions (OEA) .............................2-67
Translation Lookaside Buffer Management Instructions-(OEA) ........2-67
Recommended Simplified Mnemonics ..........................................................2-68
Chapter 3
L1 Instruction and Data Cache Operation
Data Cache Organization......................................................................................3-3
Instruction Cache Organization ............................................................................3-4
Memory and Cache Coherency ............................................................................3-5
Memory/Cache Access Attributes (WIMG Bits) .............................................3-6
MEl Protocol ....................................................................................................3-7
MEl Hardware Considerations.....................................................................3-9
Coherency Precautions in Single Processor Systems.....................................3-10
Coherency Precautions in Multiprocessor Systems .......................................3-10
MPC750-lnitiated Load/Store Operations......................................................
3-10
Performed Loads and Stores....................................................................... 3-11
Sequential Consistency of Memory Accesses............................................3-11
Atomic Memory References ......................................................................
3-11
MPC750 RISC Microprocessor User's Manual

Paragraph
Number
3.4
3.4.1
3.4.1.1
3.4.1.2
3.4.1.3
3.4.1.4
3.4.1.5
3.4.1.6
3.4.2
3.4.2.1
3.4.2.2
3.4.2.3
3.4.2.4
3.4.2.5
3.4.2.6
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.5.1
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.7
3.8
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
Contents
CONTENTS
Title Page
Number
Cache ControL...................................................................................................3-13
Cache Control Parameters in
HIDO ................................................................3-13
Data Cache Flash Invalidation ...................................................................3-13
Data Cache Enabling/Disabling .................................................................3-13
Data Cache Locking...................................................................................3-14
Instruction Cache Flash Invalidation .........................................................3-14
Instruction Cache Enabling/Disabling .......................................................3-14
Instruction Cache Locking .........................................................................3-15
Cache Control Instructions............................................................................. 3-15
Data Cache Block Touch (debt) and
Data Cache Block Touch for Store (debtst)..........................................3-15
Data Cache Block Zero (debz) ..................................................................3-16
Data Cache Block Store (debst) ................................................................3-16
Data Cache Block Flush
(debt') .................................................................3-17
Data Cache Block Invalidate (debi)........................................................... 3-17
Instruction Cache Block Invalidate (icbi)..................................................3-17
Cache Operations ...............................................................................................3-18
Cache Block Replacement/Castout Operations .............................................3-18
Cache Flush Operations .................................................................................
3-21
Data Cache-Block-Fill Operations.................................................................3-21
Instruction Cache-Block-Fill Operations .......................................................3-21
Data Cache-Block-Push Operation ................................................................3-22
Enveloped High-Priority Cache-Block-Push Operation............................3-22
Ll Caches and 60x Bus Transactions ................................................................3-22
Read Operations and the MEl Protocol .........................................................3-23
Bus Operations Caused by Cache Control Instructions .................................3-24
Snooping ........................................................................................................3-25
Snoop Response to 60x Bus Transactions ..................................................... 3-26
Transfer Attributes .........................................................................................3-28
Bus Interface ......................................................................................................
3- 30
MEl State Transactions ......................................................................................3-32
Chapter 4
Exceptions
MPC750 Microprocessor Exceptions...................................................................4-2
Exception Recognition and Priorities...................................................................4-4
Exception Processing ...........................................................................................4-7
Enabling and Disabling Exceptions ...............................................................4-10
Steps for Exception Processing......................................................................4-10
Setting MSR[RI] ............................................................................................4-11
Returning from an Exception Handler ...........................................................4-11
vii