Motorola MPC8260 PowerQUICC II User manual

MPC8260UM/D
4/1999
Rev. 0
MPC8260 PowerQUICC II
UserÕs Manual
ª
ª

PowerQUICC II, Mfax, and DigitalDNA are trademarks of Motorola, Inc.
The PowerPC name, the PowerPC logotype, PowerPC 601, PowerPC 603, PowerPC 603e, PowerPC 604, PowerPC 604e, and RS/6000 are trademarks of
International Business Machines Corporation used by Motorola under license from International Business Machines Corporation.
I
2
C is a registered trademark of Philips Semiconductors
Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied
copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document.
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© Motorola, Inc., 1999. All rights reserved.

Overview
PowerPC Processor Core
Memory Map
System Interface Unit (SIU)
Reset
External Signals
60x Signals
The 60x Bus
Clocks and Power Control
Memory Controller
Secondary (L2) Cache Support
IEEE 1149.1 Test Access Port
Communications Processor Module Overview
Serial Interface with Time-Slot Assigner
CPM Multiplexing
Baud-Rate Generators (BRGs)
Timers
SDMA Channels and IDMA Emulation
Serial Communications Controllers (SCCs)
SCC UART Mode
SCC HDLC Mode
SCC BISYNC Mode
SCC Transparent Mode
SCC Ethernet Mode
SCC AppleTalk Mode
Serial Management Controllers (SMCs)
Multi-Channel Controllers (MCCs)
Fast Communications Controllers
ATM Controller
Fast Ethernet Controller
FCC HDLC Controller
FCC Transparent Controller
Serial Peripheral Interface (SPI)
I
2
C Controller
Parallel I/O Ports
Register Quick Reference Guide
Glossary
Index
3
4
5
6
7
8
9
10
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IND
12
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14
15
16
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Overview
PowerPC Processor Core
Memory Map
System Interface Unit (SIU)
Reset
External Signals
60x Signals
The 60x Bus
Clocks and Power Control
Memory Controller
Secondary (L2) Cache Support
IEEE 1149.1 Test Access Port
Communications Processor Module Overview
Serial Interface with Time-Slot Assigner
CPM Multiplexing
Baud-Rate Generators (BRGs)
Timers
SDMA Channels and IDMA Emulation
Serial Communications Controllers (SCCs)
SCC UART Mode
SCC HDLC Mode
SCC BISYNC Mode
SCC Transparent Mode
SCC Ethernet Mode
SCC AppleTalk Mode
Serial Management Controllers (SMCs)
Multi-Channel Controllers (MCCs)
Fast Communications Controllers
ATM Controller
Fast Ethernet Controller
FCC HDLC Controller
FCC Transparent Controller
Serial Peripheral Interface (SPI)
I
2
C Controller
Parallel I/O Ports
Register Quick Reference Guide
Glossary
Index
3
4
5
6
7
8
9
10
1
GLO
IND
12
13
14
15
16
17
18
19
11
20
22
23
24
25
26
27
28
29
21
30
32
33
34
31
35
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MOTOROLA Contents v
CONTENTS
Paragraph
Number Title Page
Number
About This Book
Before Using this ManualÑImportant Note.......................................................... lv
Audience ................................................................................................................ lv
Organization.......................................................................................................... lvi
Suggested Reading................................................................................................ lix
MPC8xx Documentation .............................................................................. lix
PowerPC Documentation ............................................................................. lix
Conventions ........................................................................................................... lx
Acronyms and Abbreviations ............................................................................... lxi
PowerPC Architecture Terminology Conventions ............................................. lxiv
Chapter 1
Overview
1.1 Features................................................................................................................ 1-1
1.2 MPC8260Õs Architecture Overview .................................................................... 1-4
1.2.1 MPC603e Core ................................................................................................ 1-5
1.2.2 System Interface Unit (SIU) ............................................................................ 1-6
1.2.3 Communications Processor Module (CPM) .................................................... 1-6
1.3 Software Compatibility Issues ............................................................................. 1-7
1.3.1 Signals.............................................................................................................. 1-7
1.4 Differences between MPC860 and MPC8260..................................................... 1-9
1.5 Serial Protocol Table............................................................................................ 1-9
1.6 MPC8260 Configurations .................................................................................. 1-10
1.6.1 Pin Configurations ......................................................................................... 1-10
1.6.2 Serial Performance......................................................................................... 1-10
1.7 MPC8260 Application Examples ...................................................................... 1-11
1.7.1 Examples of Communication Systems .......................................................... 1-11
1.7.1.1 Remote Access Server ............................................................................... 1-11
1.7.1.2 Regional Office Router.............................................................................. 1-12
1.7.1.3 LAN-to-WAN Bridge Router .................................................................... 1-13
1.7.1.4 Cellular Base Station ................................................................................. 1-14
1.7.1.5 Telecommunications Switch Controller .................................................... 1-14
1.7.1.6 SONET Transmission Controller .............................................................. 1-15

vi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
CONTENTS
Paragraph
Number Title Page
Number
1.7.2 Bus Configurations.........................................................................................1-15
1.7.2.1 Basic System ..............................................................................................1-15
1.7.2.2 High-Performance Communication ...........................................................1-16
1.7.2.3 High-Performance System Microprocessor ...............................................1-17
Chapter 2
PowerPC Processor Core
2.1 Overview ..............................................................................................................2-1
2.2 PowerPC Processor Core Features ......................................................................2-3
2.2.1 Instruction Unit.................................................................................................2-5
2.2.2 Instruction Queue and Dispatch Unit ...............................................................2-5
2.2.3 Branch Processing Unit (BPU).........................................................................2-6
2.2.4 Independent Execution Units ...........................................................................2-6
2.2.4.1 Integer Unit (IU)...........................................................................................2-6
2.2.4.2 Load/Store Unit (LSU).................................................................................2-7
2.2.4.3 System Register Unit (SRU) ........................................................................2-7
2.2.5 Completion Unit ...............................................................................................2-7
2.2.6 Memory Subsystem Support ............................................................................2-8
2.2.6.1 Memory Management Units (MMUs) .........................................................2-8
2.2.6.2 Cache Units ..................................................................................................2-8
2.3 Programming Model.............................................................................................2-8
2.3.1 Register Set.......................................................................................................2-8
2.3.1.1 PowerPC Register Set ..................................................................................2-9
2.3.1.2 MPC8260-Specific Registers .....................................................................2-11
2.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0) .....................2-11
2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1) .....................2-14
2.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2) .....................2-15
2.3.1.2.4 Processor Version Register (PVR).........................................................2-16
2.3.2 PowerPC Instruction Set and Addressing Modes...........................................2-16
2.3.2.1 Calculating Effective Addresses ................................................................2-16
2.3.2.2 PowerPC Instruction Set ............................................................................2-16
2.3.2.3 MPC8260 Implementation-Specific Instruction Set ..................................2-18
2.4 Cache Implementation........................................................................................2-18
2.4.1 PowerPC Cache Model...................................................................................2-18
2.4.2 MPC8260 Implementation-Specific Cache Implementation..........................2-19
2.4.2.1 Data Cache .................................................................................................2-19
2.4.2.2 Instruction Cache........................................................................................2-21
2.4.2.3 Cache Locking............................................................................................2-21
2.4.2.3.1 Entire Cache Locking.............................................................................2-21
2.4.2.3.2 Way Locking ..........................................................................................2-21
2.5 Exception Model.................................................................................................2-22

MOTOROLA Contents vii
CONTENTS
Paragraph
Number Title Page
Number
2.5.1 PowerPC Exception Model ............................................................................2-22
2.5.2 MPC8260 Implementation-Specific Exception Model..................................2-23
2.5.3 Exception Priorities........................................................................................2-26
2.6 Memory Management ........................................................................................2-26
2.6.1 PowerPC MMU Model ..................................................................................2-27
2.6.2 MPC8260 Implementation-Specific MMU Features .....................................2-28
2.7 Instruction Timing..............................................................................................2-29
2.8 Differences between the MPC8260Õs Core and the PowerPC 603e
Microprocessor...............................................................................................2-30
Chapter 3
Memory Map
Chapter 4
System Interface Unit (SIU)
4.1 System Configuration and Protection ..................................................................4-2
4.1.1 Bus Monitor .....................................................................................................4-3
4.1.2 Timers Clock....................................................................................................4-4
4.1.3 Time Counter (TMCNT)..................................................................................4-4
4.1.4 Periodic Interrupt Timer (PIT) .........................................................................4-5
4.1.5 Software Watchdog Timer ...............................................................................4-6
4.2 Interrupt Controller ..............................................................................................4-7
4.2.1 Interrupt Configuration ....................................................................................4-8
4.2.2 Interrupt Source Priorities ................................................................................4-9
4.2.2.1 SCC, FCC, and MCC Relative Priority .....................................................4-12
4.2.2.2 PIT, TMCNT, and IRQ Relative Priority ..................................................4-12
4.2.2.3 Highest Priority Interrupt ...........................................................................4-13
4.2.3 Masking Interrupt Sources .............................................................................4-13
4.2.4 Interrupt Vector Generation and Calculation.................................................4-14
4.2.4.1 Port C External Interrupts ..........................................................................4-16
4.3 Programming Model ..........................................................................................4-17
4.3.1 Interrupt Controller Registers ........................................................................4-17
4.3.1.1 SIU Interrupt Configuration Register (SICR)............................................4-17
4.3.1.2 SIU Interrupt Priority Register (SIPRR)....................................................4-18
4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L) .................4-19
4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L).....................4-21
4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L) ............................4-22
4.3.1.6 SIU Interrupt Vector Register (SIVEC).....................................................4-23
4.3.1.7 SIU External Interrupt Control Register (SIEXR).....................................4-24
4.3.2 System Configuration and Protection Registers ............................................4-25
4.3.2.1 Bus Configuration Register (BCR) ...........................................................4-25

viii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
CONTENTS
Paragraph
Number Title Page
Number
4.3.2.2 60x Bus Arbiter Configuration Register (PPC_ACR) ...............................4-28
4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL) .............4-28
4.3.2.4 Local Bus Arbiter Configuration Register (LCL_ACR)............................4-29
4.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL)...4-30
4.3.2.6 SIU Module Configuration Register (SIUMCR) .......................................4-31
4.3.2.7 Internal Memory Map Register (IMMR) ...................................................4-34
4.3.2.8 System Protection Control Register (SYPCR)...........................................4-35
4.3.2.9 Software Service Register (SWSR)............................................................4-36
4.3.2.10 60x Bus Transfer Error Status and Control Register 1 (TESCR1).............4-36
4.3.2.11 60x Bus Transfer Error Status and Control Register 2 (TESCR2).............4-37
4.3.2.12 Local Bus Transfer Error Status and Control Register 1 (L_TESCR1) .....4-38
4.3.2.13 Local Bus Transfer Error Status and Control Register 2 (L_TESCR2) .....4-39
4.3.2.14 Time Counter Status and Control Register (TMCNTSC) ..........................4-40
4.3.2.15 Time Counter Register (TMCNT)..............................................................4-41
4.3.2.16 Time Counter Alarm Register (TMCNTAL) .............................................4-41
4.3.3 Periodic Interrupt Registers............................................................................4-42
4.3.3.1 Periodic Interrupt Status and Control Register (PISCR)............................4-42
4.3.3.2 Periodic Interrupt Timer Count Register (PITC) .......................................4-43
4.3.3.3 Periodic Interrupt Timer Register (PITR) ..................................................4-44
4.4 SIU Pin Multiplexing..........................................................................................4-44
Chapter 5
Reset
5.1 Reset Causes.........................................................................................................5-1
5.1.1 Reset Actions....................................................................................................5-2
5.1.2 Power-On Reset Flow.......................................................................................5-2
5.1.3
HRESET Flow .................................................................................................5-3
5.1.4
SRESET Flow...................................................................................................5-3
5.2 Reset Status Register (RSR).................................................................................5-4
5.3 Reset Mode Register (RMR) ................................................................................5-5
5.4 Reset Configuration..............................................................................................5-6
5.4.1 Hard Reset Configuration Word.......................................................................5-8
5.4.2 Hard Reset Configuration Examples ................................................................5-9
5.4.2.1 Single MPC8260 with Default Configuration..............................................5-9
5.4.2.2 Single MPC8260 Configured from Boot EPROM.....................................5-10
5.4.2.3 Multiple MPC8260s Configured from Boot EPROM................................5-10
5.4.2.4 Multiple MPC8260s in a System with No EPROM...................................5-12
Chapter 6

MOTOROLA Contents ix
CONTENTS
Paragraph
Number Title Page
Number
External Signals
6.1 Functional Pinout .................................................................................................6-1
6.2 Signal Descriptions ..............................................................................................6-2
Chapter 7
60x Signals
7.1 Signal Configuration ............................................................................................7-2
7.2 Signal Descriptions ..............................................................................................7-3
7.2.1 Address Bus Arbitration Signals......................................................................7-3
7.2.1.1 Bus Request (BR)ÑOutput .........................................................................7-3
7.2.1.1.1 Address Bus Request (BR)ÑOutput .......................................................7-3
7.2.1.1.2 Address Bus Request (BR)ÑInput..........................................................7-4
7.2.1.2 Bus Grant (BG) ............................................................................................7-4
7.2.1.2.1 Bus Grant (BG)ÑInput............................................................................7-4
7.2.1.2.2 Bus Grant (BG)ÑOutput.........................................................................7-5
7.2.1.3 Address Bus Busy (ABB) ............................................................................7-5
7.2.1.3.1 Address Bus Busy (ABB)ÑOutput .........................................................7-5
7.2.1.3.2 Address Bus Busy (ABB)ÑInput............................................................7-6
7.2.2 Address Transfer Start Signal ..........................................................................7-6
7.2.2.1 Transfer Start (TS) .......................................................................................7-6
7.2.2.1.1 Transfer Start (TS)ÑOutput ....................................................................7-6
7.2.2.2 Transfer Start (TS)ÑInput...........................................................................7-6
7.2.3 Address Transfer Signals .................................................................................7-7
7.2.3.1 Address Bus (A[0Ð31]) ................................................................................7-7
7.2.3.1.1 Address Bus (A[0Ð31])ÑOutput.............................................................7-7
7.2.3.1.2 Address Bus (A[0Ð31])ÑInput................................................................7-7
7.2.4 Address Transfer Attribute Signals..................................................................7-7
7.2.4.1 Transfer Type (TT[0Ð4])..............................................................................7-8
7.2.4.1.1 Transfer Type (TT[0Ð4])ÑOutput...........................................................7-8
7.2.4.1.2 Transfer Type (TT[0Ð4])ÑInput .............................................................7-8
7.2.4.2 Transfer Size (TSIZ[0Ð3]) ...........................................................................7-8
7.2.4.3 Transfer Burst (TBST) .................................................................................7-8
7.2.4.4 Global (GBL) ...............................................................................................7-9
7.2.4.4.1 Global (GBL)ÑOutput............................................................................7-9
7.2.4.4.2 Global (GBL)ÑInput...............................................................................7-9
7.2.4.5 Caching-Inhibited (CI)ÑOutput..................................................................7-9
7.2.4.6 Write-Through (WT)ÑOutput ....................................................................7-9
7.2.5 Address Transfer Termination Signals...........................................................7-10
7.2.5.1 Address Acknowledge (AACK) ................................................................7-10
7.2.5.1.1 Address Acknowledge (AACK)ÑOutput .............................................7-10
7.2.5.1.2 Address Acknowledge (AACK)ÑInput................................................7-10

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CONTENTS
Paragraph
Number Title Page
Number
7.2.5.2 Address Retry (ARTRY)............................................................................7-11
7.2.5.2.1 Address Retry (ARTRY)ÑOutput.........................................................7-11
7.2.5.2.2 Address Retry (ARTRY)ÑInput ...........................................................7-11
7.2.6 Data Bus Arbitration Signals..........................................................................7-12
7.2.6.1 Data Bus Grant (DBG) ...............................................................................7-12
7.2.6.1.1 Data Bus Grant (DBG)ÑInput ..............................................................7-12
7.2.6.1.2 Data Bus Grant (DBG)ÑOutput............................................................7-12
7.2.6.2 Data Bus Busy (DBB) ................................................................................7-13
7.2.6.2.1 Data Bus Busy (DBB)ÑOutput.............................................................7-13
7.2.6.2.2 Data Bus Busy (DBB)ÑInput................................................................7-13
7.2.7 Data Transfer Signals .....................................................................................7-13
7.2.7.1 Data Bus (D[0Ð63]) ....................................................................................7-13
7.2.7.1.1 Data Bus (D[0Ð63])ÑOutput.................................................................7-14
7.2.7.1.2 Data Bus (D[0Ð63])ÑInput ...................................................................7-14
7.2.7.2 Data Bus Parity (DP[0Ð7]) .........................................................................7-14
7.2.7.2.1 Data Bus Parity (DP[0Ð7])ÑOutput ......................................................7-14
7.2.7.2.2 Data Bus Parity (DP[0Ð7])ÑInput.........................................................7-15
7.2.8 Data Transfer Termination Signals ................................................................7-15
7.2.8.1 Transfer Acknowledge (TA) ......................................................................7-15
7.2.8.1.1 Transfer Acknowledge (TA)ÑInput......................................................7-15
7.2.8.1.2 Transfer Acknowledge (TA)ÑOutput ...................................................7-16
7.2.8.2 Transfer Error Acknowledge (TEA) ..........................................................7-16
7.2.8.2.1 Transfer Error Acknowledge (TEA)ÑInput..........................................7-16
7.2.8.2.2 Transfer Error Acknowledge (TEA)ÑOutput .......................................7-17
7.2.8.3 Partial Data Valid Indication (PSDVAL)...................................................7-17
7.2.8.3.1 Partial Data Valid (PSDVAL)ÑInput ...................................................7-17
7.2.8.3.2 Partial Data Valid (PSDVAL)ÑOutput.................................................7-18
Chapter 8
The 60x Bus
8.1 Terminology .........................................................................................................8-1
8.2 Bus Configuration.................................................................................................8-2
8.2.1 Single MPC8260 Bus Mode.............................................................................8-2
8.2.2 60x-Compatible Bus Mode...............................................................................8-3
8.3 60x Bus Protocol Overview..................................................................................8-4
8.3.1 Arbitration Phase ..............................................................................................8-5
8.3.2 Address Pipelining and Split-Bus Transactions ...............................................8-7
8.4 Address Tenure Operations ..................................................................................8-7
8.4.1 Address Arbitration ..........................................................................................8-7
8.4.2 Address Pipelining............................................................................................8-9
8.4.3 Address Transfer Attribute Signals ................................................................8-10