Motorola 68000 Setup guide

Motorola 68000's
Instruction Set

We have included this appendix to save you the task of having to turn to secondary
material when writing 68000 assembly language programs. Since most
programmers are not interested in the encoding of instructions, details of
instruction encoding have been omitted (i.e., the actual op-code bit patterns).
Applications of some of the instructions have been provided to demonstrate how
they can be used in practice.
Instructions are listed by mnemonic in alphabetical order. The information
provided about each instruction is: its assembler syntax, its attributes (i.e., whether
it takes a byte, word, or longword operand), its description in words, the effect its
execution has on the condition codes, and the addressing modes it may take. The
effect of an instruction on the CCR is specified by the following codes:
UThe state of the bit is undefined (i.e., its value cannot be predicted)
-The bit remains unchanged by the execution of the instruction
*The bit is set or cleared according to the outcome of the instruction.
Unless an addressing mode is implicit (e.g., NOP, RESET, RTS, etc.), the legal
source and destination addressing modes are specified by their assembly language
syntax. The following notation is used to describe the 68000's instruction set.
Dn, An Data and address register direct.
(An) Address register indirect.
(An)+, -(An) Address register indirect with post-incrementing or pre-
decrementing.
(d,An), (d,An,Xi) Address register indirect with displacement, and address
register indirect with indexing and a displacement.
ABS.W, ABS.L Absolute addressing with a 16-bit or a 32-bit address.
(d,PC), (d,PC,Xi) Program counter relative addressing with a 16-bit offset,
or with an 8-bit offset plus the contents of an index
register.
imm An immediate value (i.e., literal) which may be 16 or 32
bits, depending on the instruction.
1
The 68000's Instruction Set

2The 68000's Instruction Set
Two notations are employed for address register indirect addressing. The
notation originally used to indicate address register indirect addressing has been
superseded. However, the Teesside 68000 simulator supports only the older form.
Old notation Current notation
d(An), d(An,Xi) (d,An), (d,An,Xi)
d(PC), d(PC,Xi) (d,PC), (d,PC,Xi)
ABCD Add decimal with extend
Operation: [destination]10 ←[source]10 + [destination]10 + [X]
Syntax: ABCD Dy,Dx
ABCD -(Ay),-(Ax)
Attributes: Size = byte
Description: Add the source operand to the destination operand along with
the extend bit, and store the result in the destination location.
The addition is performed using BCD arithmetic. The only legal
addressing modes are data register direct and memory to memory
with address register indirect using pre-decrementing.
Application: The ABCD instruction is used in chain arithmetic to add together
strings of BCD digits. Consider the addition of two nine-digit
numbers. Note that the strings are stored so that the least-
significant digit is at the high address.
LEA Number1,A0 A0 points at first string
LEA Number2,A1 A1 points at second string
MOVE #8,D0 Nine digits to add
MOVE #$04,CCR Clear X-bit and Z-bit of the CCR
LOOP ABCD -(A0),-(A1) Add a pair of digits
DBRA D0,LOOP Repeat until 9 digits added
Condition codes: X N Z V C
* U * U *
The Z-bit is cleared if the result is non-zero, and left unchanged
otherwise. The Z-bit is normally set by the programmer before
the BCD operation, and can be used to test for zero after a chain
of multiple-precision operations. The C-bit is set if a decimal
carry is generated.

3
The 68000's Instruction Set
ADD Add binary
Operation: [destination] ←[source] + [destination]
Syntax: ADD <ea>,Dn
ADD Dn,<ea>
Attributes: Size = byte, word, longword
Description: Add the source operand to the destination operand and store the
result in the destination location.
Condition codes: X N Z V C
* * * * *
Source operand addressing modes
Destination operand addressing modes
ADDA Add address
Operation: [destination] ←[source] + [destination]
Syntax: ADDA <ea>,An
Attributes: Size = word, longword
Description: Add the source operand to the destination address register and
store the result in the destination address register. The source is
sign-extended before it is added to the destination. For example,
if we execute ADDA.W D3,A4 where A4 = 0000010016 and D3.W =
800216, the contents of D3 are sign-extended to FFFF800216 and
added to 0000010016 to give FFFF810216, which is stored in A4.

4The 68000's Instruction Set
Application: To add to the contents of an address register and not update the
CCR. Note that ADDA.W D0,A0 is the same as LEA (A0,D0.W),A0.
Condition codes: X N Z V C
- - - - -
An ADDA operation does not affect the state of the CCR.
Source operand addressing modes
ADDI Add immediate
Operation: [destination] ←<literal> + [destination]
Syntax: ADDI #<data>,<ea>
Attributes: Size = byte, word, longword
Description: Add immediate data to the destination operand. Store the result
in the destination operand. ADDI can be used to add a literal
directly to a memory location. For example, ADDI.W #$1234,$2000
has the effect [M(200016)]← [M(200016)] +123416.
Condition codes: X N Z V C
* * * * *
Destination operand addressing modes
ADDQ Add quick
Operation: [destination] ←<literal> + [destination]
Syntax: ADDQ #<data>,<ea>

5
The 68000's Instruction Set
Sample syntax: ADDQ #6,D3
Attributes: Size = byte, word, longword
Description: Add the immediate data to the contents of the destination operand.
The immediate data must be in the range 1 to 8. Word and
longword operations on address registers do not affect condition
codes. Note that a word operation on an address register affects
all bits of the register.
Application: ADDQ is used to add a small constant to the operand at the effective
address. Some assemblers permit you to write ADD and then choose
ADDQ automatically if the constant is in the range 1 to 8.
Condition codes: Z N Z V C
* * * * *
Note that the CCR is not updated if the destination operand is an
address register.
Destination operand addressing modes
ADDX Add extended
Operation: [destination] ←[source] + [destination] + [X]
Syntax: ADDX Dy,Dx
ADDX -(Ay),-(Ax)
Attributes: Size = byte, word, longword
Description: Add the source operand to the destination operand along with
the extend bit, and store the result in the destination location.
The only legal addressing modes are data register direct and
memory to memory with address register indirect using pre-
decrementing.
Application: The ADDX instruction is used in chain arithmetic to add together
strings of bytes (words or longwords). Consider the addition of

6The 68000's Instruction Set
two 128-bit numbers, each of which is stored as four consecutive
longwords.
LEA Number1,A0 A0 points at first number
LEA Number2,A1 A1 points at second number
MOVE #3,D0 Four longwords to add
MOVE #$00,CCR Clear X-bit and Z-bit of the CCR
LOOP ADDX -(A0),-(A1) Add pair of numbers
DBRA D0,LOOP Repeat until all added
Condition codes: X N Z V C
* * * * *
The Z-bit is cleared if the result is non-zero, and left unchanged
otherwise. The Z-bit can be used to test for zero after a chain of
multiple precision operations.
AND AND logical
Operation: [destination] ←[source].[destination]
Syntax: AND <ea>,Dn
AND Dn,<ea>
Attributes: Size = byte, word, longword
Description: AND the source operand to the destination operand and store
the result in the destination location.
Application: AND is used to mask bits. If we wish to clear bits 3 to 6 of data
register D7, we can execute AND #%10000111,D7. Unfortunately,
the AND operation cannot be used with an address register as
either a source or a destination operand. If you wish to perform a
logical operation on an address register, you have to copy the
address to a data register and then perform the operation there.
Condition codes: X N Z V C
- * * 0 0
Source operand addressing modes

7
The 68000's Instruction Set
Destination operand addressing modes
ANDI AND immediate
Operation: [destination] ←<literal>.[destination]
Syntax: ANDI #<data>,<ea>
Attributes: Size = byte, word, longword
Description: AND the immediate data to the destination operand. The ANDI
permits a literal operand to be ANDed with a destination other
than a data register. For example, ANDI #$FE00,$1234 or
ANDI.B #$F0,(A2)+.
Condition codes: X N Z V C
- * * 0 0
Destination operand addressing modes
ANDI to CCR AND immediate to condition
code register
Operation: [CCR] ←<data>.[CCR]
Syntax: ANDI #<data>,CCR
Attributes: Size = byte
Description: AND the immediate data to the condition code register (i.e., the
least-significant byte of the status register).

8The 68000's Instruction Set
Application: ANDI is used to clear selected bits of the CCR. For example,
ANDI #$FA,CCR clears the Z- and C-bits, i.e., XNZVC = X N 0 V 0.
Condition codes: X N Z V C
* * * * *
X: cleared if bit 4 of data is zero
N: cleared if bit 3 of data is zero
Z: cleared if bit 2 of data is zero
V: cleared if bit 1 of data is zero
C: cleared if bit 0 of data is zero
ANDI to SR AND immediate to status register
Operation: IF [S] =1
THEN
[SR] ←<literal>.[SR]
ELSE TRAP
Syntax: ANDI #<data>,SR
Attributes: Size = word
Description: AND the immediate data to the status register and store the
result in the status register. All bits of the SR are affected.
Application: This instruction is used to clear the interrupt mask, the S-bit, and
the T-bit of the SR. ANDI #<data>,SR affects both the status byte
of the SR and the CCR. For example, ANDI #$7FFF,SR clears the
trace bit of the status register, while ANDI #$7FFE,SR clears the
trace bit and also clears the carry bit of the CCR.
Condition codes: X N Z V C
* * * * *
ASL,ASR Arithmetic shift left/right
Operation: [destination] ←[destination] shifted by <count>
Syntax: ASL Dx,Dy
ASR Dx,Dy
ASL #<data>,Dy
ASR #<data>,Dy
ASL <ea>
ASR <ea>

9
The 68000's Instruction Set
Attributes: Size = byte, word, longword
Description: Arithmetically shift the bits of the operand in the specified direc-
tion (i.e., left or right). The shift count may be specified in one of
three ways. The count may be a literal, the contents of a data
register, or the value 1. An immediate (i.e., literal) count permits
a shift of 1 to 8 places. If the count is in a register, the value is
modulo 64 (i.e., 0 to 63). If no count is specified, one shift is made
(i.e., ASL <ea> shifts the contents of the word at the effective
address one place left).
The effect of an arithmetic shift left is to shift a zero into the
least-significant bit position and to shift the most-significant bit
out into both the X- and the C-bits of the CCR. The overflow bit
of the CCR is set if a sign change occurs during shifting (i.e., if
the most-significant bit changes value during shifting).
The effect of an arithmetic shift right is to shift the least-
significant bit into both the X- and C-bits of the CCR. The most-
significant bit (i.e., the sign bit) is replicated to preserve the sign of
the number.
Application: ASL multiplies a twos complement number by 2. ASL is almost
identical to the corresponding logical shift, LSR. The only differ-
ence between ASL and LSL is that ASL sets the V-bit of the CCR if
overflow occurs, while LSL clears the V-bit to zero. An ASR divides
a twos complement number by 2. When applied to the contents
of a memory location, all 68000 shift operations operate on a word.
Condition codes: X N Z V C
* * * * *
The X-bit and the C-bit are set according to the last bit shifted out
of the operand. If the shift count is zero, the C-bit is cleared. The
V-bit is set if the most-significant bit is changed at any time
during the shift operation and cleared otherwise.

10 The 68000's Instruction Set
Destination operand addressing modes
Bcc Branch on condition cc
Operation: If cc = 1 THEN [PC] ←[PC] + d
Syntax: Bcc <label>
Sample syntax: BEQ Loop_4
BVC *+8
Attributes: BEQ takes an 8-bit or a 16-bit offset (i.e., displacement).
Description: If the specified logical condition is met, program execution
continues at location [PC] + displacement, d. The displacement is
a twos complement value. The value in the PC corresponds to
the current location plus two. The range of the branch is -126 to
+128 bytes with an 8-bit offset, and -32K to +32K bytes with a 16-
bit offset. A short branch to the next instruction is impossible,
since the branch code 0 indicates a long branch with a 16-bit
offset. The assembly language form BCC *+8 means branch to the
point eight bytes from the current PC if the carry bit is clear.
BCC branch on carry clear C
BCS branch on carry set C
BEQ branch on equal Z
BGE branch on greater than or equal N.V + N.V
BGT branch on greater than N.V.Z + N.V.Z
BHI branch on higher than C.Z
BLE branch on less than or equal Z + N.V + N.V
BLS branch on lower than or same C + Z
BLT branch on less than N.V + N.V
BMI branch on minus (i.e., negative) N
BNE branch on not equal Z
BPL branch on plus (i.e., positive) N
BVC branch on overflow clear V
BVS branch on overflow set V
Note that there are two types of conditional branch instruction:

11
The 68000's Instruction Set
those that branch on an unsigned condition and those that branch
on a signed condition. For example, $FF is greater than $10 when
the numbers are regarded as unsigned (i.e., 255 is greater than
16). However, if the numbers are signed, $FF is less than $10 (i.e.,
-1 is less than 16).
The signed comparisons are:
BGE branch on greater than or equal
BGT branch on greater than
BLE branch on lower than or equal
BLT branch on less than
The unsigned comparisons are:
BHS BCC branch on higher than or same
BHI branch on higher than
BLS branch on lower than or same
BLO BCS branch on less than
The official mnemonics BCC (branch on carry clear) and BCS (branch
on carry set) can be renamed as BHS (branch on higher than or
same) and BLO (branch on less than), respectively. Many 68000
assemblers support these alternative mnemonics.
Condition codes: X N Z V C
- - - - -
BCHG Test a bit and change
Operation: [Z] ←<bit number> OF [destination]
<bit number> OF [destination] ← <bit number> OF [destination]
Syntax: BCHG Dn,<ea>
BCHG #<data>,<ea>
Attributes: Size = byte, longword
Description: A bit in the destination operand is tested and the state of the
specified bit is reflected in the condition of the Z-bit in the CCR.
After the test operation, the state of the specified bit is changed
in the destination. If a data register is the destination, then the bit
numbering is modulo 32, allowing bit manipulation of all bits in
a data register. If a memory location is the destination, a byte is

12 The 68000's Instruction Set
read from that location, the bit operation performed using the bit
number modulo 8, and the byte written back to the location.
Note that bit zero refers to the least-significant bit. The bit number
for this operation may be specified either statically by an
immediate value or dynamically by the contents of a data register.
Application: If the operation BCHG #4,$1234 is carried out and the contents of
memory location $1234 are 101010102, bit 4 is tested. It is a 0 and
therefore the Z-bit of the CCR is set to 1. Bit 4 of the destination
operand is changed and the new contents of location 123416 are
101110102.
Condition codes: X N Z V C
- - * - -
Z: set if the bit tested is zero, cleared otherwise.
Destination operand addressing modes
Note that data register direct (i.e., Dn) addressing uses a longword
operand, while all other modes use a byte operand.
BCLR Test a bit and clear
Operation: [Z] ←<bit number> OF [destination]
<bit number> OF [destination] ←0
Syntax: BCLR Dn,<ea>
BCLR #<data>,<ea>
Attributes: Size = byte, longword
Description: A bit in the destination operand is tested and the state of the
specified bit is reflected in the condition of the Z-bit in the
condition code. After the test, the state of the specified bit is
cleared in the destination. If a data register is the destination, the
bit numbering is modulo 32, allowing bit manipulation of all bits
in a data register. If a memory location is the destination, a byte
is read from that location, the bit operation performed using the
bit number modulo 8, and the byte written back to the location.

13
The 68000's Instruction Set
Bit zero refers to the least-significant bit. The bit number for this
operation may be specified either by an immediate value or
dynamically by the contents of a data register.
Application: If the operation BCLR #4,$1234 is carried out and the contents of
memory location $1234 are 111110102, bit 4 is tested. It is a 1 and
therefore the Z-bit of the CCR is set to 0. Bit 4 of the destination
operand is cleared and the new contents of $1234 are: 111010102.
Condition codes: X N Z V C
- - * - -
Z: set if the bit tested is zero, cleared otherwise.
Destination operand addressing modes
Note that data register direct (i.e., Dn) addressing uses a longword
operand, while all other modes use a byte operand.
BRA Branch always
Operation: [PC] ←[PC] + d
Syntax: BRA <label>
BRA <literal>
Attributes: Size = byte, word
Description: Program execution continues at location [PC]+d. The displace-
ment, d, is a twos complement value (8 bits for a short branch
and 16 bits for a long branch). The value in the PC corresponds
to the current location plus two. Note that a short branch to the
next instruction is impossible, since the branch code 0 is used to
indicate a long branch with a 16-bit offset.
Application: A BRA is an unconditional relative jump (or goto). You use a BRA
instruction to write position independent code, because the
destination address (branch target address) is specified with respect
to the current value of the PC. A JMP instruction does not produce
position independent code.

14 The 68000's Instruction Set
Condition codes: X N Z V C
- - - - -
BSET Test a bit and set
Operation: [Z] ←<bit number> OF [destination]
<bit number> OF [destination] ←1
Syntax: BSET Dn,<ea>
BSET #<data>,<ea>
Attributes: Size = byte, longword
Description: A bit in the destination operand is tested and the state of the
specified bit is reflected in the condition of the Z-bit of the
condition code. After the test, the specified bit is set in the
destination. If a data register is the destination then the bit
numbering is modulo 32, allowing bit manipulation of all bits in
a data register. If a memory location is the destination, a byte is
read from that location, the bit operation performed using bit
number modulo 8, and the byte written back to the location. Bit
zero refers to the least-significant bit. The bit number for this
operation may be specified either by an immediate value or
dynamically by the contents of a data register.
Condition codes: X N Z V C
- - * - -
Z: set if the bit tested is zero, cleared otherwise.
Destination operand addressing mode for BSET Dn,<ea> form
Note that data register direct (i.e., Dn) addressing uses a longword
operand, while all other modes use a byte operand.
BSR Branch to subroutine
Operation: [SP] ←[SP] - 4; [M([SP])] ←[PC]; [PC] ←[PC] + d

15
The 68000's Instruction Set
Syntax: BSR <label>
BSR <literal>
Attributes: Size = byte, word
Description: The longword address of the instruction immediately following
the BSR instruction is pushed onto the system stack pointed at by
A7. Program execution then continues at location [PC] +
displacement. The displacement is an 8-bit twos complement
value for a short branch, or a 16-bit twos complement value for
a long branch. The value in the PC corresponds to the current
location plus two. Note that a short branch to the next instruction
is impossible, since the branch code 0 is used to indicate a long
branch with a 16-bit offset.
Application: BSR is used to call a procedure or a subroutine. Since it provides
relative addressing (and therefore position independent code),
its use is preferable to JSR.
Condition codes: X N Z V C
- - - - -
BTST Test a bit
Operation: [Z] ←<bit number> OF [destination]
Syntax: BTST Dn,<ea>
BTST #<data>,<ea>
Attributes: Size = byte, longword
Description: A bit in the destination operand is tested and the state of the
specified bit is reflected in the condition of the Z-bit in the CCR.
The destination is not modified by a BTST instruction. If a data
register is the destination, then the bit numbering is modulo 32,
allowing bit manipulation of all bits in a data register. If a memory
location is the destination, a byte is read from that location, the
bit operation performed. Bit 0 refers to the least-significant bit.
The bit number for this operation may be specified either statically
by an immediate value or dynamically by the contents of a data
register.
Condition codes: X N Z V C
- - * - -
Z: set if the bit tested is zero, cleared otherwise.

16 The 68000's Instruction Set
Destination operand addressing modes for BTST Dn,<ea> form
Note that data register direct (i.e., Dn) addressing uses a longword
operand, while all other modes use a byte operand.
CHK Check register against bounds
Operation: IF [Dn] < 0 OR [Dn] > [<ea>] THEN TRAP
Syntax: CHK <ea>,Dn
Attributes: Size = word
Description: The contents of the low-order word in the data register specified
in the instruction are examined and compared with the upper
bound at the effective address. The upper bound is a twos
complement integer. If the data register value is less than zero or
greater than the upper bound contained in the operand word,
then the processor initiates exception processing.
Application: The CHK instruction can be used to test the bounds of an array
element before it is used. By performing this test, you can make
certain that you do not access an element outside an array.
Consider the following fragment of code:
MOVE.W subscript,D0 Get subscript to test
CHK #max_bound,D0 Test subscript against 0 and upper bound
* TRAP on error ELSE continue if ok
Condition codes: X N Z V C
- * U U U
N: set if [Dn] <0; cleared if [Dn] >[<ea>]; undefined otherwise.
Source operand addressing modes

17
The 68000's Instruction Set
CLR Clear an operand
Operation: [destination] ←0
Syntax: CLR <ea>
Sample syntax: CLR (A4)+
Attributes: Size = byte, word, longword
Description: The destination is cleared  loaded with all zeros. The CLR in-
struction can't be used to clear an address register. You can use
SUBA.L A0,A0 to clear A0. Note that a side effect of CLRs imple-
mentation is a read from the specified effective address before the
clear (i.e., write) operation is executed. Under certain circum-
stances this might cause a problem (e.g., with write-only memory).
Condition codes: X N Z V C
- 0 1 0 0
Source operand addressing modes
CMP Compare
Operation: [destination] - [source]
Syntax: CMP <ea>,Dn
Sample syntax: CMP (Test,A6,D3.W),D2
Attributes: Size = byte, word, longword
Description: Subtract the source operand from the destination operand and
set the condition codes accordingly. The destination must be a
data register. The destination is not modified by this instruction.
Condition codes: X N Z V C
- * * * *

18 The 68000's Instruction Set
Source operand addressing modes
CMPA Compare address
Operation: [destination] - [source]
Syntax: CMPA <ea>,An
Sample syntax: CMPA.L #$1000,A4
CMPA.W (A2)+,A6
CMPA.L D5,A2
Attributes: Size = word, longword
Description: Subtract the source operand from the destination address register
and set the condition codes accordingly. The address register is
not modified. The size of the operation may be specified as word
or longword. Word length operands are sign-extended to 32 bits
before the comparison is carried out.
Condition codes: X N Z V C
- * * * *
Source operand addressing modes
CMPI Compare immediate
Operation: [destination] - <immediate data>
Syntax: CMPI #<data>,<ea>
Attributes: Size = byte, word, longword