Motorola 68000 Setup guide

Motorola 68000's
Instruction Set

We have included this appendix to save you the task of having to turn to secondary
material when writing 68000 assembly language programs. Since most
programmers are not interested in the encoding of instructions, details of
instruction encoding have been omitted (i.e., the actual op-code bit patterns).
Applications of some of the instructions have been provided to demonstrate how
they can be used in practice.
Instructions are listed by mnemonic in alphabetical order. The information
provided about each instruction is: its assembler syntax, its attributes (i.e., whether
it takes a byte, word, or longword operand), its description in words, the effect its
execution has on the condition codes, and the addressing modes it may take. The
effect of an instruction on the CCR is specified by the following codes:
UThe state of the bit is undefined (i.e., its value cannot be predicted)
-The bit remains unchanged by the execution of the instruction
*The bit is set or cleared according to the outcome of the instruction.
Unless an addressing mode is implicit (e.g., NOP, RESET, RTS, etc.), the legal
source and destination addressing modes are specified by their assembly language
syntax. The following notation is used to describe the 68000's instruction set.
Dn, An Data and address register direct.
(An) Address register indirect.
(An)+, -(An) Address register indirect with post-incrementing or pre-
decrementing.
(d,An), (d,An,Xi) Address register indirect with displacement, and address
register indirect with indexing and a displacement.
ABS.W, ABS.L Absolute addressing with a 16-bit or a 32-bit address.
(d,PC), (d,PC,Xi) Program counter relative addressing with a 16-bit offset,
or with an 8-bit offset plus the contents of an index
register.
imm An immediate value (i.e., literal) which may be 16 or 32
bits, depending on the instruction.
1
The 68000's Instruction Set

2The 68000's Instruction Set
Two notations are employed for address register indirect addressing. The
notation originally used to indicate address register indirect addressing has been
superseded. However, the Teesside 68000 simulator supports only the older form.
Old notation Current notation
d(An), d(An,Xi) (d,An), (d,An,Xi)
d(PC), d(PC,Xi) (d,PC), (d,PC,Xi)
ABCD Add decimal with extend
Operation: [destination]10 ←[source]10 + [destination]10 + [X]
Syntax: ABCD Dy,Dx
ABCD -(Ay),-(Ax)
Attributes: Size = byte
Description: Add the source operand to the destination operand along with
the extend bit, and store the result in the destination location.
The addition is performed using BCD arithmetic. The only legal
addressing modes are data register direct and memory to memory
with address register indirect using pre-decrementing.
Application: The ABCD instruction is used in chain arithmetic to add together
strings of BCD digits. Consider the addition of two nine-digit
numbers. Note that the strings are stored so that the least-
significant digit is at the high address.
LEA Number1,A0 A0 points at first string
LEA Number2,A1 A1 points at second string
MOVE #8,D0 Nine digits to add
MOVE #$04,CCR Clear X-bit and Z-bit of the CCR
LOOP ABCD -(A0),-(A1) Add a pair of digits
DBRA D0,LOOP Repeat until 9 digits added
Condition codes: X N Z V C
* U * U *
The Z-bit is cleared if the result is non-zero, and left unchanged
otherwise. The Z-bit is normally set by the programmer before
the BCD operation, and can be used to test for zero after a chain
of multiple-precision operations. The C-bit is set if a decimal
carry is generated.

3
The 68000's Instruction Set
ADD Add binary
Operation: [destination] ←[source] + [destination]
Syntax: ADD <ea>,Dn
ADD Dn,<ea>
Attributes: Size = byte, word, longword
Description: Add the source operand to the destination operand and store the
result in the destination location.
Condition codes: X N Z V C
* * * * *
Source operand addressing modes
Destination operand addressing modes
ADDA Add address
Operation: [destination] ←[source] + [destination]
Syntax: ADDA <ea>,An
Attributes: Size = word, longword
Description: Add the source operand to the destination address register and
store the result in the destination address register. The source is
sign-extended before it is added to the destination. For example,
if we execute ADDA.W D3,A4 where A4 = 0000010016 and D3.W =
800216, the contents of D3 are sign-extended to FFFF800216 and
added to 0000010016 to give FFFF810216, which is stored in A4.

4The 68000's Instruction Set
Application: To add to the contents of an address register and not update the
CCR. Note that ADDA.W D0,A0 is the same as LEA (A0,D0.W),A0.
Condition codes: X N Z V C
- - - - -
An ADDA operation does not affect the state of the CCR.
Source operand addressing modes
ADDI Add immediate
Operation: [destination] ←<literal> + [destination]
Syntax: ADDI #<data>,<ea>
Attributes: Size = byte, word, longword
Description: Add immediate data to the destination operand. Store the result
in the destination operand. ADDI can be used to add a literal
directly to a memory location. For example, ADDI.W #$1234,$2000
has the effect [M(200016)]← [M(200016)] +123416.
Condition codes: X N Z V C
* * * * *
Destination operand addressing modes
ADDQ Add quick
Operation: [destination] ←<literal> + [destination]
Syntax: ADDQ #<data>,<ea>

5
The 68000's Instruction Set
Sample syntax: ADDQ #6,D3
Attributes: Size = byte, word, longword
Description: Add the immediate data to the contents of the destination operand.
The immediate data must be in the range 1 to 8. Word and
longword operations on address registers do not affect condition
codes. Note that a word operation on an address register affects
all bits of the register.
Application: ADDQ is used to add a small constant to the operand at the effective
address. Some assemblers permit you to write ADD and then choose
ADDQ automatically if the constant is in the range 1 to 8.
Condition codes: Z N Z V C
* * * * *
Note that the CCR is not updated if the destination operand is an
address register.
Destination operand addressing modes
ADDX Add extended
Operation: [destination] ←[source] + [destination] + [X]
Syntax: ADDX Dy,Dx
ADDX -(Ay),-(Ax)
Attributes: Size = byte, word, longword
Description: Add the source operand to the destination operand along with
the extend bit, and store the result in the destination location.
The only legal addressing modes are data register direct and
memory to memory with address register indirect using pre-
decrementing.
Application: The ADDX instruction is used in chain arithmetic to add together
strings of bytes (words or longwords). Consider the addition of

6The 68000's Instruction Set
two 128-bit numbers, each of which is stored as four consecutive
longwords.
LEA Number1,A0 A0 points at first number
LEA Number2,A1 A1 points at second number
MOVE #3,D0 Four longwords to add
MOVE #$00,CCR Clear X-bit and Z-bit of the CCR
LOOP ADDX -(A0),-(A1) Add pair of numbers
DBRA D0,LOOP Repeat until all added
Condition codes: X N Z V C
* * * * *
The Z-bit is cleared if the result is non-zero, and left unchanged
otherwise. The Z-bit can be used to test for zero after a chain of
multiple precision operations.
AND AND logical
Operation: [destination] ←[source].[destination]
Syntax: AND <ea>,Dn
AND Dn,<ea>
Attributes: Size = byte, word, longword
Description: AND the source operand to the destination operand and store
the result in the destination location.
Application: AND is used to mask bits. If we wish to clear bits 3 to 6 of data
register D7, we can execute AND #%10000111,D7. Unfortunately,
the AND operation cannot be used with an address register as
either a source or a destination operand. If you wish to perform a
logical operation on an address register, you have to copy the
address to a data register and then perform the operation there.
Condition codes: X N Z V C
- * * 0 0
Source operand addressing modes

7
The 68000's Instruction Set
Destination operand addressing modes
ANDI AND immediate
Operation: [destination] ←<literal>.[destination]
Syntax: ANDI #<data>,<ea>
Attributes: Size = byte, word, longword
Description: AND the immediate data to the destination operand. The ANDI
permits a literal operand to be ANDed with a destination other
than a data register. For example, ANDI #$FE00,$1234 or
ANDI.B #$F0,(A2)+.
Condition codes: X N Z V C
- * * 0 0
Destination operand addressing modes
ANDI to CCR AND immediate to condition
code register
Operation: [CCR] ←<data>.[CCR]
Syntax: ANDI #<data>,CCR
Attributes: Size = byte
Description: AND the immediate data to the condition code register (i.e., the
least-significant byte of the status register).

8The 68000's Instruction Set
Application: ANDI is used to clear selected bits of the CCR. For example,
ANDI #$FA,CCR clears the Z- and C-bits, i.e., XNZVC = X N 0 V 0.
Condition codes: X N Z V C
* * * * *
X: cleared if bit 4 of data is zero
N: cleared if bit 3 of data is zero
Z: cleared if bit 2 of data is zero
V: cleared if bit 1 of data is zero
C: cleared if bit 0 of data is zero
ANDI to SR AND immediate to status register
Operation: IF [S] =1
THEN
[SR] ←<literal>.[SR]
ELSE TRAP
Syntax: ANDI #<data>,SR
Attributes: Size = word
Description: AND the immediate data to the status register and store the
result in the status register. All bits of the SR are affected.
Application: This instruction is used to clear the interrupt mask, the S-bit, and
the T-bit of the SR. ANDI #<data>,SR affects both the status byte
of the SR and the CCR. For example, ANDI #$7FFF,SR clears the
trace bit of the status register, while ANDI #$7FFE,SR clears the
trace bit and also clears the carry bit of the CCR.
Condition codes: X N Z V C
* * * * *
ASL,ASR Arithmetic shift left/right
Operation: [destination] ←[destination] shifted by <count>
Syntax: ASL Dx,Dy
ASR Dx,Dy
ASL #<data>,Dy
ASR #<data>,Dy
ASL <ea>
ASR <ea>