Motorola DSP56303 User manual

DSP56303 User’s Manual
24-Bit Digital Signal Processor
DSP56303UM/AD
Revision 1, January 2001

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for
any other application in which the failure of the Motorola product could create a situation where personal injury or death may
occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims,
costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the
design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
OnCE, DigitalDNA, and the DigitalDNA logo are trademarks of Motorola, Inc.
How to reach us:
USA/EUROPE
Motorola Literature Distribution
P.O. Box 5405
Denver, Colorado 80217
1-303-675-2140
1-800-441-2447
Technical Information Center
1-800-521-6274
JAPAN
Motorola Japan Ltd.
SPS, Technical Information Center
3-20-1, Minami-Azabu, Minato-ku
Tokyo 106-8573 Japan
81-3-3440-3569
ASIA/PACIFIC
Motorola Semiconductors H.K. Ltd.
Silicon Harbour Centre
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
852-26668334
Home Page
http://www.mot.com/SPS/DSP
DSP Helpline
http://www.motorola-dsp.com/contact
email: [e-mail]
 MOTOROLA INC., 1996, 2001

1
2
3
5
7
8
A
B
Overview
Signals/Connections
Memory Configuration
Programming the Peripherals
Enhanced Synchronous Serial Interface (ESSI)
Serial Communications Interface (SCI)
Bootstrap Program
Programming Reference
9Triple Timer Module
4Core Configuration
6Host Interface (HI08)

1
2
3
5
7
8
A
B
Overview
Signals/Connections
Memory Configuration
Programming the Peripherals
Enhanced Synchronous Serial Interface (ESSI)
Serial Communications Interface (SCI)
Bootstrap Program
Programming Reference
9
Triple Timer Module
4
Core Configuration
6
Host Interface (HI08)

Contents v
Contents
Chapter 1
Overview
1.1 Manual Organization ............................................................................................................. 1-1
1.2 Manual Conventions.............................................................................................................. 1-2
1.3 Features.................................................................................................................................. 1-4
1.4 DSP56300 Core ..................................................................................................................... 1-4
1.5 DSP56300 Core Functional Blocks.......................................................................................1-5
1.5.1 Data ALU............................................................................................................................... 1-6
1.5.1.1 Data ALU Registers......................................................................................................... 1-6
1.5.1.2 Multiplier-Accumulator (MAC) ...................................................................................... 1-6
1.5.2 Address Generation Unit (AGU)........................................................................................... 1-7
1.5.3 Program Control Unit (PCU).................................................................................................1-7
1.5.4 PLL and Clock Oscillator ...................................................................................................... 1-8
1.5.5 JTAG TAP and OnCE Module.............................................................................................. 1-9
1.5.6 On-Chip Memory................................................................................................................... 1-9
1.5.7 Off-Chip Memory Expansion.............................................................................................. 1-10
1.6 Internal Buses ...................................................................................................................... 1-10
1.7 DMA.................................................................................................................................... 1-11
1.8 Peripherals ........................................................................................................................... 1-12
1.8.1 GPIO Functionality.............................................................................................................. 1-12
1.8.2 HI08 ..................................................................................................................................... 1-12
1.8.3 ESSI ..................................................................................................................................... 1-13
1.8.4 SCI ....................................................................................................................................... 1-13
1.8.5 Timer Module ...................................................................................................................... 1-14
Chapter 2
Signals/Connections
2.1 Power ..................................................................................................................................... 2-3
2.2 Ground ................................................................................................................................... 2-4
2.3 Clock...................................................................................................................................... 2-5
2.4 Phase Lock Loop (PLL)......................................................................................................... 2-5
2.5 External Memory Expansion Port (Port A) ........................................................................... 2-6
2.5.1 External Address Bus............................................................................................................. 2-6
2.5.2 External Data Bus.................................................................................................................. 2-6
2.5.3 External Bus Control ............................................................................................................. 2-6

vi DSP56303 User’s Manual
2.6 Interrupt and Mode Control...................................................................................................2-9
2.7 Host Interface (HI08)........................................................................................................... 2-10
2.7.1 Host Port Usage Considerations .......................................................................................... 2-10
2.7.2 Host Port Configuration.......................................................................................................2-11
2.8 Enhanced Synchronous Serial Interface 0 (ESSI0) .............................................................2-15
2.9 Enhanced Synchronous Serial Interface 1 (ESSI1) .............................................................2-17
2.10 Serial Communication Interface (SCI) ................................................................................ 2-19
2.11 Timers.................................................................................................................................. 2-20
2.12 JTAG/OnCE Interface .........................................................................................................2-21
Chapter 3
Memory Configuration
3.1 Program Memory Space ........................................................................................................ 3-1
3.1.1 Internal Program Memory .................................................................................................... 3-2
3.1.2 Memory Switch Modes—Program Memory......................................................................... 3-2
3.1.3 Instruction Cache................................................................................................................... 3-2
3.1.4 Program Bootstrap ROM....................................................................................................... 3-3
3.2 X Data Memory Space........................................................................................................... 3-3
3.2.1 Internal X Data Memory........................................................................................................ 3-3
3.2.2 Memory Switch Modes—X Data Memory ...........................................................................3-3
3.2.3 Internal I/O Space—X Data Memory.................................................................................... 3-4
3.3 Y Data Memory Space........................................................................................................... 3-4
3.3.1 Internal Y Data Memory........................................................................................................ 3-4
3.3.2 Memory Switch Modes—Y Data Memory ...........................................................................3-4
3.3.3 External I/O Space—Y Data Memory................................................................................... 3-5
3.4 Dynamic Memory Configuration Switching ......................................................................... 3-5
3.5 Sixteen-Bit Compatibility Mode Configuration .................................................................... 3-6
3.6 RAM Configuration Summary .............................................................................................. 3-6
3.7 Memory Maps........................................................................................................................ 3-7
Chapter 4
Core Configuration
4.1 Operating Modes.................................................................................................................... 4-2
4.2 Bootstrap Program ................................................................................................................. 4-8
4.3 Central Processor Unit (CPU) Registers................................................................................ 4-9
4.3.1 Status Register (SR)............................................................................................................... 4-9
4.3.2 Operating Mode Register (OMR)........................................................................................ 4-15
4.4 Configuring Interrupts ......................................................................................................... 4-18
4.4.1 Interrupt Priority Registers (IPRC and IPRP)...................................................................... 4-19
4.4.2 Interrupt Table Memory Map .............................................................................................. 4-20
4.4.3 Processing Interrupt Source Priorities Within an IPL .........................................................4-22
4.5 PLL Control Register (PCTL) .............................................................................................4-24
4.6 Bus Interface Unit (BIU) Registers ..................................................................................... 4-25
4.6.1 Bus Control Register............................................................................................................ 4-25

Contents vii
4.6.2 DRAM Control Register (DCR).......................................................................................... 4-27
4.6.3 Address Attribute Registers (AAR[0–3]) ............................................................................4-30
4.7 DMA Control Registers 5–0 (DCR[5–0]) ...........................................................................4-32
4.8 Device Identification Register (IDR)................................................................................... 4-37
4.9 JTAG Identification (ID) Register....................................................................................... 4-38
4.10 JTAG Boundary Scan Register (BSR)................................................................................. 4-38
Chapter 5
Programming the Peripherals
5.1 Peripheral Initialization Steps................................................................................................ 5-1
5.2 Mapping the Control Registers..............................................................................................5-2
5.3 Reading Status Registers ....................................................................................................... 5-2
5.4 Data Transfer Methods .......................................................................................................... 5-3
5.4.1 Polling.................................................................................................................................... 5-3
5.4.2 Interrupts................................................................................................................................ 5-3
5.4.3 DMA...................................................................................................................................... 5-5
5.4.4 Advantages and Disadvantages ............................................................................................. 5-6
5.5 General-Purpose Input/Output (GPIO).................................................................................. 5-6
5.5.1 Port B Signals and Registers.................................................................................................. 5-7
5.5.2 Port C Signals and Registers.................................................................................................. 5-8
5.5.3 Port D Signals and Registers ................................................................................................. 5-8
5.5.4 Port E Signals and Registers.................................................................................................. 5-9
5.5.5 Triple Timer Signals and Registers ....................................................................................... 5-9
Chapter 6
Host Interface (HI08)
6.1 Features.................................................................................................................................. 6-1
6.1.1 DSP Core Interface................................................................................................................ 6-1
6.1.2 Host Processor Interface........................................................................................................ 6-2
6.2 Host Port Signals ................................................................................................................... 6-3
6.3 Overview................................................................................................................................ 6-4
6.4 Operation ............................................................................................................................... 6-6
6.4.1 Software Polling .................................................................................................................... 6-7
6.4.2 Core Interrupts and Host Commands..................................................................................... 6-7
6.4.3 Core DMA Access................................................................................................................. 6-9
6.4.4 Host Requests ........................................................................................................................ 6-9
6.4.5 Endian Modes ...................................................................................................................... 6-11
6.5 Boot-up Using the HI08 Host Port ...................................................................................... 6-12
6.6 DSP Core Programming Model...........................................................................................6-13
6.6.1 Host Control Register (HCR) ..............................................................................................6-14
6.6.2 Host Status Register (HSR) .................................................................................................6-15
6.6.3 Host Data Direction Register (HDDR)................................................................................ 6-16
6.6.4 Host Data Register (HDR)...................................................................................................6-16
6.6.5 Host Base Address Register (HBAR).................................................................................. 6-17

viii DSP56303 User’s Manual
6.6.6 Host Port Control Register (HPCR)..................................................................................... 6-18
6.6.7 Host Transmit (HTX) Register ............................................................................................ 6-21
6.6.8 Host Receive (HRX) Register.............................................................................................. 6-22
6.6.9 DSP-Side Registers After Reset ..........................................................................................6-22
6.7 Host Programmer Model .....................................................................................................6-23
6.7.1 Interface Control Register (ICR) ......................................................................................... 6-24
6.7.2 Command Vector Register (CVR)....................................................................................... 6-26
6.7.3 Interface Status Register (ISR) ............................................................................................6-27
6.7.4 Interrupt Vector Register (IVR)...........................................................................................6-29
6.7.5 Receive Data Registers (RXH:RXM:RXL)......................................................................... 6-30
6.7.6 Transmit Data Registers (TXH:TXM:TXL)........................................................................6-30
6.7.7 Host-Side Registers After Reset .......................................................................................... 6-31
6.8 Programming Model Quick Reference................................................................................ 6-32
Chapter 7
Enhanced Synchronous Serial Interface (ESSI)
7.1 ESSI Enhancements............................................................................................................... 7-2
7.2 ESSI Data and Control Signals..............................................................................................7-3
7.2.1 Serial Transmit Data Signal (STD)........................................................................................ 7-3
7.2.2 Serial Receive Data Signal (SRD)......................................................................................... 7-3
7.2.3 Serial Clock (SCK)................................................................................................................7-3
7.2.4 Serial Control Signal (SC0)................................................................................................... 7-4
7.2.5 Serial Control Signal (SC1)................................................................................................... 7-4
7.2.6 Serial Control Signal (SC2)................................................................................................... 7-6
7.3 Operation ............................................................................................................................... 7-6
7.3.1 ESSI After Reset....................................................................................................................7-6
7.3.2 Initialization........................................................................................................................... 7-6
7.3.3 Exceptions.............................................................................................................................. 7-7
7.4 Operating Modes: Normal, Network, and On-Demand....................................................... 7-10
7.4.1 Normal/Network/On-Demand Mode Selection................................................................... 7-10
7.4.2 Synchronous/Asynchronous Operating Modes ...................................................................7-11
7.4.3 Frame Sync Selection .......................................................................................................... 7-11
7.4.4 Frame Sync Signal Format ..................................................................................................7-11
7.4.5 Frame Sync Length for Multiple Devices............................................................................ 7-12
7.4.6 Word Length Frame Sync and Data Word Timing.............................................................. 7-12
7.4.7 Frame Sync Polarity............................................................................................................. 7-12
7.4.8 Byte Format (LSB/MSB) for the Transmitter...................................................................... 7-13
7.4.9 Flags..................................................................................................................................... 7-13
7.5 ESSI Programming Model...................................................................................................7-14
7.5.1 ESSI Control Register A (CRA).......................................................................................... 7-14
7.5.2 ESSI Control Register B (CRB) .......................................................................................... 7-18
7.5.3 ESSI Status Register (SSISR).............................................................................................. 7-28
7.5.4 ESSI Receive Shift Register ................................................................................................7-29
7.5.5 ESSI Receive Data Register (RX) ....................................................................................... 7-30
7.5.6 ESSI Transmit Shift Registers.............................................................................................7-30

Contents ix
7.5.7 ESSI Transmit Data Registers (TX[2–0])............................................................................ 7-33
7.5.8 ESSI Time Slot Register (TSR)........................................................................................... 7-33
7.5.9 Transmit Slot Mask Registers (TSMA, TSMB).................................................................. 7-33
7.5.10 Receive Slot Mask Registers (RSMA, RSMB) ................................................................... 7-35
7.6 GPIO Signals and Registers................................................................................................. 7-36
7.6.1 Port Control Registers (PCRC and PCRD).......................................................................... 7-36
7.6.2 Port Direction Registers (PRRC and PRRD)....................................................................... 7-37
7.6.3 Port Data Registers (PDRC and PDRD)..............................................................................7-38
Chapter 8
Serial Communication Interface (SCI)
8.1 Operating Modes.................................................................................................................... 8-1
8.1.1 Synchronous Mode ................................................................................................................ 8-2
8.1.2 Asynchronous Mode.............................................................................................................. 8-2
8.1.3 Multidrop Mode..................................................................................................................... 8-2
8.1.3.1 Transmitting Data and Address Characters..................................................................... 8-3
8.1.3.2 Wired-OR Mode .............................................................................................................. 8-3
8.1.3.3 Idle Line Wakeup............................................................................................................. 8-3
8.1.3.4 Address Mode Wakeup.................................................................................................... 8-3
8.2 I/O Signals ............................................................................................................................. 8-3
8.2.1 Receive Data (RXD).............................................................................................................. 8-4
8.2.2 Transmit Data (TXD)............................................................................................................. 8-4
8.2.3 SCI Serial Clock (SCLK) ...................................................................................................... 8-4
8.3 SCI After Reset...................................................................................................................... 8-5
8.4 SCI Initialization.................................................................................................................... 8-6
8.4.1 Preamble, Break, and Data Transmission Priority................................................................. 8-7
8.4.2 Bootstrap Loading Through the SCI (Boot Mode 2 or A)..................................................... 8-8
8.5 Exceptions.............................................................................................................................. 8-8
8.6 SCI Programming Model....................................................................................................... 8-9
8.6.1 SCI Control Register (SCR) ................................................................................................ 8-12
8.6.2 SCI Status Register (SSR) ................................................................................................... 8-17
8.6.3 SCI Clock Control Register (SCCR) ................................................................................... 8-19
8.6.4 SCI Data Registers............................................................................................................... 8-22
8.6.4.1 SCI Receive Register (SRX).......................................................................................... 8-22
8.6.4.2 SCI Transmit Register (STX) ........................................................................................ 8-23
8.7 GPIO Signals and Registers................................................................................................. 8-24
8.7.1 Port E Control Register (PCRE).......................................................................................... 8-24
8.7.2 Port E Direction Register (PRRE) ....................................................................................... 8-25
8.7.3 Port E Data Register (PDRE)...............................................................................................8-25
Chapter 9
Triple Timer Module
9.1 Overview................................................................................................................................ 9-1
9.1.1 Triple Timer Module Block Diagram.................................................................................... 9-2

xDSP56303 User’s Manual
9.1.2 Individual Timer Block Diagram........................................................................................... 9-2
9.2 Operation ............................................................................................................................... 9-3
9.2.1 Timer After Reset .................................................................................................................. 9-3
9.2.2 Timer Initialization ................................................................................................................ 9-4
9.2.3 Timer Exceptions................................................................................................................... 9-4
9.3 Operating Modes.................................................................................................................... 9-5
9.3.1 Triple Timer Modes...............................................................................................................9-6
9.3.1.1 Timer GPIO (Mode 0) ..................................................................................................... 9-6
9.3.1.2 Timer Pulse (Mode 1)...................................................................................................... 9-8
9.3.1.3 Timer Toggle (Mode 2) ................................................................................................. 9-10
9.3.1.4 Timer Event Counter (Mode 3) .....................................................................................9-12
9.3.2 Signal Measurement Modes................................................................................................. 9-14
9.3.2.1 Measurement Input Width (Mode 4) .............................................................................9-14
9.3.2.2 Measurement Input Period (Mode 5)............................................................................. 9-16
9.3.2.3 Measurement Capture (Mode 6).................................................................................... 9-18
9.3.3 Pulse Width Modulation (PWM, Mode 7)........................................................................... 9-19
9.3.4 Watchdog Modes................................................................................................................. 9-22
9.3.4.1 Watchdog Pulse (Mode 9) ............................................................................................. 9-22
9.3.4.2 Watchdog Toggle (Mode 10)......................................................................................... 9-24
9.3.4.3 Reserved Modes............................................................................................................. 9-25
9.3.5 Special Cases ....................................................................................................................... 9-25
9.3.6 DMA Trigger....................................................................................................................... 9-25
9.4 Triple Timer Module Programming Model......................................................................... 9-25
9.4.1 Prescaler Counter................................................................................................................. 9-25
9.4.2 Timer Prescaler Load Register (TPLR)............................................................................... 9-27
9.4.3 Timer Prescaler Count Register (TPCR) ............................................................................. 9-28
9.4.4 Timer Control/Status Register (TCSR)................................................................................ 9-28
9.4.5 Timer Load Register (TLR).................................................................................................9-33
9.4.6 Timer Compare Register (TCPR)........................................................................................9-34
9.4.7 Timer Count Register (TCR) ............................................................................................... 9-34
Appendix A
Bootstrap Program
A.1 Bootstrap Code ..................................................................................................................... A-1
A.2 Equates for I/O Port Programming....................................................................................... A-8
A.3 Host Interface (HI08) Equates .............................................................................................. A-9
A.4 Serial Communications Interface (SCI) Equates................................................................ A-10
A.5 Enhanced Synchronous Serial Interface (ESSI) Equates.................................................... A-11
A.6 Exception Processing Equates ............................................................................................ A-13
A.7 Timer Module Equates........................................................................................................ A-14
A.8 Direct Memory Access (DMA) Equates............................................................................. A-15
A.9 Phase Locked Loop (PLL) equates..................................................................................... A-17
A.10 Bus Interface Unit (BIU) Equates....................................................................................... A-18
A.11 Interrupt Equates................................................................................................................. A-20