Motorola DSP56309 User manual

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DSP56309 OVERVIEW
SIGNAL/CONNECTION DESCRIPTIONS
MEMORY CONFIGURATION
CORE CONFIGURATION
GENERAL PURPOSE I/O
HOST INTERFACE (HI08)
ENHANCED SYNCHRONOUS SERIAL INTERFACE
SERIAL COMMUNICATION INTERFACE (SCI)
TIMER MODULE
ON-CHIP EMULATION MODULE
JTAG PORT
CBSDL LISTING
IINDEX
DPROGRAMMING REFERENCE
ABOOTSTRAP PROGRAM
BEQUATES

1
2
3
4
6
7
5
11
8
9
10
DSP56309 OVERVIEW
SIGNAL/CONNECTION DESCRIPTIONS
MEMORY CONFIGURATION
CORE CONFIGURATION
GENERAL PURPOSE I/O
HOST INTERFACE (HI08)
ENHANCED SYNCHRONOUS SERIAL INTERFACE
SERIAL COMMUNICATION INTERFACE (SCI)
TIMER MODULE
ON-CHIP EMULATION MODULE
JTAG PORT
CBSDL LISTING
IINDEX
DPROGRAMMING REFERENCE
ABOOTSTRAP PROGRAM
BEQUATES

DSP56309
24-Bit Digital Signal Processor
UserÕs Manual
Motorola, Incorporated
Semiconductor Products Sector
DSP Division
6501 William Cannon Drive West
Austin, TX 78735-8598
Rev. 0

This document (and other documents) can be viewed on the World Wide
Web at http://www.mot.com/SPS/DSP/documentation/
This manual is one of a set of three documents. You need the following
manuals to have complete product information: Family Manual, UserÕs
Manual, and Technical Data.
OnCE
ä
is a trademark of Motorola, Inc.
Intel
Ò
is a registered trademark of the Intel Corporation.
All other trademarks are those of their respective owners.
ã MOTOROLA INC., 1998
Ò Reg. U.S. Pat. & Tm. Off.
Order this document by DSP56309UM/D
Motorola reserves the right to make changes without further notice to any products
herein to improve reliability, function, or design. Motorola does not assume any
liability arising out of the application or use of any product or circuit described
herein; neither does it convey any license under its patent rights nor the rights of
others. Motorola products are not authorized for use as components in life support
devices or systems intended for surgical implant into the body or intended to
support or sustain life. Buyer agrees to notify Motorola of any such intended end use
whereupon Motorola shall determine availability and suitability of its product or
products for the use intended. Motorola and
are registered trademarks of
Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity /Affirmative
Action Employer.

MOTOROLA DSP56309UM/D iii
TABLE OF CONTENTS
SECTION 1 DSP56309 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2 MANUAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 MANUAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.4 DSP56309 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.5 DSP56309 CORE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 1-7
1.5.1 General Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.5.2 Hardware Debugging Support . . . . . . . . . . . . . . . . . . . . . . 1-7
1.5.3 Reduced Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6 DSP56300 CORE FUNCTIONAL BLOCKS . . . . . . . . . . . . . . 1-8
1.6.1 Data ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.1.1 Data ALU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.1.2 Multiplier-Accumulator (MAC) . . . . . . . . . . . . . . . . . . . . 1-9
1.6.2 Address Generation Unit (AGU) . . . . . . . . . . . . . . . . . . . . 1-9
1.6.3 Program Control Unit (PCU) . . . . . . . . . . . . . . . . . . . . . . 1-10
1.6.4 PLL and Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.6.5 JTAG TAP and OnCE Module . . . . . . . . . . . . . . . . . . . . . 1-11
1.6.6 On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.6.7 Off-Chip Memory Expansion . . . . . . . . . . . . . . . . . . . . . . 1-12
1.7 INTERNAL BUSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.8 DSP56309 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.9 DIRECT MEMORY ACCESS (DMA) . . . . . . . . . . . . . . . . . . 1-15
1.10 DSP56309 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . 1-15
1.10.1 GPIO Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.10.2 Host Interface (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1.10.3 Enhanced Synchronous Serial Interface (ESSI) . . . . . . . 1-16
1.10.4 Serial Communications Interface (SCI) . . . . . . . . . . . . . . 1-16
1.10.5 Timer Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
SECTION 2 SIGNAL/CONNECTION DESCRIPTIONS. . . . . . . . 2-1
2.1 SIGNAL GROUPINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2 POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

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2.3 GROUND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.4 CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.5 PHASE-LOCKED LOOP (PLL) . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.6 EXTERNAL MEMORY EXPANSION PORT (PORT A). . . . . 2-9
2.6.1 External Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.6.2 External Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.6.3 External Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.7 INTERRUPT AND MODE CONTROL . . . . . . . . . . . . . . . . . 2-14
2.8 HOST INTERFACE (HI08) . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.8.1 Host Port Usage Considerations. . . . . . . . . . . . . . . . . . . 2-16
2.8.2 Host Port Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.9 ENHANCED SYNCHRONOUS SERIAL INTERFACE . . . . 2-24
2.9.1 ESSI0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.9.2 ESSI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2.10 SERIAL COMMUNICATION INTERFACE (SCI) . . . . . . . . . 2-32
2.11 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
2.12 ONCE/JTAG INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
SECTION 3 MEMORY CONFIGURATION . . . . . . . . . . . . . . . . . 3-1
3.1 MEMORY SPACES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.1.1 Program Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.1.2 Data Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.1.2.1 X Data Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.1.2.2 Y Data Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.1.3 Memory Space Configuration . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2 RAM CONFIGURATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2.1 On-Chip Program Memory (Program RAM) . . . . . . . . . . . 3-6
3.2.2 On-Chip X Data Memory (X Data RAM) . . . . . . . . . . . . . . 3-6
3.2.3 On-Chip Y Data Memory (Y Data RAM) . . . . . . . . . . . . . . 3-7
3.2.4 Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.3 MEMORY CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.3.1 Memory Space Configurations . . . . . . . . . . . . . . . . . . . . . 3-7
3.3.2 RAM Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4 MEMORY MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.5 INTERNAL I/O MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . 3-18

MOTOROLA DSP56309UM/D v
SECTION 4 CORE CONFIGURATION . . . . . . . . . . . . . . . . . . . . 4-1
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.3 BOOTSTRAP PROGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.3.1 Mode 0: Expanded Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.3.2 Modes 1 to 7: Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.3.3 Mode 8: Expanded Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.3.4 Mode 9: Boot from Byte-Wide External Memory . . . . . . . . 4-7
4.3.5 Mode A: Boot from SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.3.6 Mode B: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.3.7 Modes C, D, E, F: Boot from HI08 . . . . . . . . . . . . . . . . . . . 4-8
4.3.7.1 Mode C: In ISA/DSP5630X Mode (8-Bit Bus) . . . . . . . 4-8
4.3.7.2 Mode D: In HC11 Non-multiplexed Mode . . . . . . . . . . 4-8
4.3.7.3 Mode E: In 8051 Multiplexed Bus Mode . . . . . . . . . . . 4-9
4.3.7.4 Mode F: In 68302/68360 Bus Mode . . . . . . . . . . . . . . . 4-9
4.4 INTERRUPT SOURCES AND PRIORITIES . . . . . . . . . . . . . 4-9
4.4.1 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.4.2 Interrupt Priority Levels . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4.4.3 Interrupt Source Priorities Within an IPL . . . . . . . . . . . . . 4-14
4.5 DMA REQUEST SOURCES . . . . . . . . . . . . . . . . . . . . . . . . 4-16
4.6 OPERATING MODE REGISTER (OMR) . . . . . . . . . . . . . . . 4-17
4.7 PLL CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.7.1 PCTL PLL Multiplication Factor Bits 0Ð11 . . . . . . . . . . . . 4-18
4.7.2 PCTL XTAL Disable Bit (XTLD) Bit 16. . . . . . . . . . . . . . . 4-18
4.7.3 PCTL Predivider Factor Bits (PD0ÐPD3) Bits 20Ð23. . . . 4-18
4.8 DEVICE IDENTIFICATION REGISTER (IDR) . . . . . . . . . . . 4-18
4.9 AA CONTROL REGISTERS (AAR0ÐAAR3) . . . . . . . . . . . . 4-19
4.10 JTAG BOUNDARY SCAN REGISTER (BSR) . . . . . . . . . . . 4-20
SECTION 5 GENERAL-PURPOSE I/O . . . . . . . . . . . . . . . . . . . . 5-1
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.2 PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.2.1 Port B Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-3
5.2.2 Port C Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-3
5.2.3 Port D Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-4
5.2.4 Port E Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . 5-4

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5.2.5 Triple Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
SECTION 6 HOST INTERFACE (HI08) . . . . . . . . . . . . . . . . . . . 6-1
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2 HI08 FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.1 Host to DSP Core Interface. . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.2 HI08-to-Host Processor Interface . . . . . . . . . . . . . . . . . . . 6-4
6.3 HI08 HOST PORT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.4 HI08 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.5 HI08 DSP SIDE PROGRAMMERÕS MODEL. . . . . . . . . . . . . 6-8
6.5.1 Host Receive Data Register (HRX). . . . . . . . . . . . . . . . . . 6-8
6.5.2 Host Transmit Data Register (HTX) . . . . . . . . . . . . . . . . . 6-9
6.5.3 Host Control Register (HCR). . . . . . . . . . . . . . . . . . . . . . . 6-9
6.5.3.1 HCR Host Receive Interrupt Enable (HRIE) Bit 0 . . . 6-10
6.5.3.2 HCR Host Transmit Interrupt Enable (HTIE) Bit 1 . . . 6-10
6.5.3.3 HCR Host Command Interrupt Enable (HCIE) Bit 2. . 6-10
6.5.3.4 HCR Host Flags 2,3 (HF[3:2]) Bits 3, 4 . . . . . . . . . . . 6-10
6.5.3.5 HCR Reserved Bits 5-15 . . . . . . . . . . . . . . . . . . . . . . 6-10
6.5.4 Host Status Register (HSR) . . . . . . . . . . . . . . . . . . . . . . 6-11
6.5.4.1 HSR Host Receive Data Full (HRDF) Bit 0 . . . . . . . . 6-11
6.5.4.2 HSR Host Transmit Data Empty (HTDE) Bit 1 . . . . . . 6-11
6.5.4.3 HSR Host Command Pending (HCP) Bit 2 . . . . . . . . 6-11
6.5.4.4 HSR Host Flags 0, 1 (HF[1:0]) Bits 3, 4 . . . . . . . . . . . 6-11
6.5.4.5 HSR Reserved Bits 5-15 . . . . . . . . . . . . . . . . . . . . . . 6-11
6.5.5 Host Base Address Register (HBAR) . . . . . . . . . . . . . . . 6-12
6.5.5.1 HBAR Base Address (BA[10:3]) Bits 0-7 . . . . . . . . . . 6-12
6.5.5.2 HBAR Reserved Bits 8-15 . . . . . . . . . . . . . . . . . . . . . 6-12
6.5.6 Host Port Control Register (HPCR). . . . . . . . . . . . . . . . . 6-12
6.5.6.1 HPCR Host GPIO Port Enable (HGEN) Bit 0 . . . . . . . 6-13
6.5.6.2 HPCR Host Address Line 8 Enable (HA8EN) Bit 1 . . 6-13
6.5.6.3 HPCR Host Address Line 9 Enable (HA9EN) Bit 2 . . 6-13
6.5.6.4 HPCR Host Chip Select Enable (HCSEN) Bit 3 . . . . . 6-13
6.5.6.5 HPCR Host Request Enable (HREN) Bit 4 . . . . . . . . 6-14
6.5.6.6 HPCR Host Acknowledge Enable (HAEN) Bit 5. . . . . 6-14
6.5.6.7 HPCR Host Enable (HEN) Bit 6 . . . . . . . . . . . . . . . . . 6-14
6.5.6.8 HPCR Reserved Bit 7. . . . . . . . . . . . . . . . . . . . . . . . . 6-14

MOTOROLA DSP56309UM/D vii
6.5.6.9 HPCR Host Request Open Drain (HROD) Bit 8 . . . . . 6-14
6.5.6.10 HPCR Host Data Strobe Polarity (HDSP) Bit 9. . . . . . 6-14
6.5.6.11 HPCR Host Address Strobe Polarity (HASP) Bit 10 . . 6-15
6.5.6.12 HPCR Host Multiplexed Bus (HMUX) Bit 11 . . . . . . . . 6-15
6.5.6.13 HPCR Host Dual Data Strobe (HDDS) Bit 12 . . . . . . . 6-15
6.5.6.14 HPCR Host Chip Select Polarity (HCSP) Bit 13 . . . . . 6-16
6.5.6.15 HPCR Host Request Polarity (HRP) Bit 14 . . . . . . . . . 6-16
6.5.6.16 HPCR Host Acknowledge Polarity (HAP) Bit 15 . . . . . 6-16
6.5.7 Host Data Direction Register (HDDR) . . . . . . . . . . . . . . . 6-17
6.5.8 Host Data Register (HDR) . . . . . . . . . . . . . . . . . . . . . . . . 6-17
6.5.9 DSP Side Registers After Reset . . . . . . . . . . . . . . . . . . . 6-18
6.5.10 Host Interface DSP Core Interrupts . . . . . . . . . . . . . . . . . 6-19
6.6 HI08-EXTERNAL HOST PROGRAMMERÕS MODEL . . . . . 6-20
6.6.1 Interface Control Register (ICR) . . . . . . . . . . . . . . . . . . . 6-22
6.6.1.1 ICR Receive Request Enable (RREQ) Bit 0 . . . . . . . . 6-23
6.6.1.2 ICR Transmit Request Enable (TREQ) Bit 1. . . . . . . . 6-23
6.6.1.3 ICR Double Host Request (HDRQ) Bit 2. . . . . . . . . . . 6-23
6.6.1.4 ICR Host Flag 0 (HF0) Bit 3 . . . . . . . . . . . . . . . . . . . . 6-24
6.6.1.5 ICR Host Flag 1 (HF1) Bit 4 . . . . . . . . . . . . . . . . . . . . 6-24
6.6.1.6 ICR Host Little Endian (HLEND) Bit 5 . . . . . . . . . . . . . 6-24
6.6.1.7 ICR Reserved Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
6.6.1.8 ICR Initialize Bit (INIT) Bit 7 . . . . . . . . . . . . . . . . . . . . 6-24
6.6.2 Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . 6-25
6.6.2.1 CVR Host Vector (HV[6:0]) Bits 0Ð6 . . . . . . . . . . . . . . 6-25
6.6.2.2 CVR Host Command Bit (HC) Bit 7. . . . . . . . . . . . . . . 6-26
6.6.3 Interface Status Register (ISR) . . . . . . . . . . . . . . . . . . . . 6-26
6.6.3.1 ISR Receive Data Register Full (RXDF) Bit 0 . . . . . . . 6-26
6.6.3.2 ISR Transmit Data Register Empty (TXDE) Bit 1 . . . . 6-27
6.6.3.3 ISR Transmitter Ready (TRDY) Bit 2 . . . . . . . . . . . . . 6-27
6.6.3.4 ISR Host Flag 2 (HF2) Bit 3 . . . . . . . . . . . . . . . . . . . . 6-27
6.6.3.5 ISR Host Flag 3 (HF3) Bit 4 . . . . . . . . . . . . . . . . . . . . 6-27
6.6.3.6 ISR Reserved Bits 5, 6 . . . . . . . . . . . . . . . . . . . . . . . . 6-27
6.6.3.7 ISR Host Request (HREQ) Bit 7 . . . . . . . . . . . . . . . . . 6-27
6.6.4 Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . . . . 6-28
6.6.5 Receive Byte Registers (RXH: RXM: RXL) . . . . . . . . . . . 6-28
6.6.6 Transmit Byte Registers (TXH:TXM:TXL) . . . . . . . . . . . . 6-29