Motorola Digital DNA MSC8101 Instruction manual

Technical Data
Advance Information
MSC8101/D
Rev. 6, 11/2002
Networking Digital
Signal Processor
(mask set 2K42A)
Figure 1. MSC8101 Block Diagram
UTOPIA
Other
Peripherals
MII
TDMs
CPM
MCC / UART / HDLC / Transparent /
Ethernet / Fast Ethernet / ATM / SCC
PIT
System Protection
Reset Control
Clock Control
SIU
8/16-bit
Host
SC140
Power
Management Clock/PLL 64-bit XA Data Bus
128-bit P-Bus
64-bit XB Data Bus
Extended Core
Interface
64-bit Local Bus
64-bit System Bus
Core
•
•
•
Serial Interface and TSA
3 ×FCC
4 ×SCC
SPI
I2C
2 ×MCC
2 ×SMC
Interrupt
Timers
Baud Rate
Parallel I/O
Generators
Controller
Dual Ported
RAM
Program
Sequencer Address
Register
File
Data ALU
Register
File
Address
ALU Data ALU
64/32-bit
System
Bus
Interrupts
EOnCE™JTAG
2 ×SDMA
RISC
Interface
DMA
Engine
Bridge
Q2PPC
Bridge
Boot
ROM
SRAM
512 KB
128-bit QBus
MEMC
L1 Interface
HDI16
MEMC
{
PIC
EFCOP
SIC_EXT
SIC Interrupts
The Motorola
MSC8101 16-bit
Digital Signal
Processor (DSP) is the
first member of the
family of DSPs based
on the StarCore™
SC140 DSP core. The
MSC8101 is offered in
three core speed levels:
250, 275, and 300 MHz.
The Motorola MSC8101 DSP is a very versatile
device that integrates the high-performance SC140
four-ALU (Arithmetic Logic Unit) DSP core along
with 512 KB of on-chip memory, a
Communications Processor Module (CPM), a
64-bit bus, a very flexible System Integration Unit
(SIU), and a 16-channel DMA engine on a single
device. With its four-ALU core, the MSC8101 can
execute up to four multiply-accumulate (MAC)
operations in a single clock cycle. The MSC8101
CPM is a 32-bit RISC-based communications
protocol enginethat can network to Time-Division
Multiplexed (TDM) highways, Ethernet, and
Asynchronous Transfer mode (ATM) backbones.
The MSC8101 60x-compatible bus interface
facilitates its connection to multi-master system
architectures. The very large on-chip memory, 512
KB, reduces the need for off-chip program and
data memories. The MSC8101 offers 1500 DSP
MMACS (1200 core and 300 EFCOP) or 3600
RISC MIPS performance using an internal 300
MHz clock with a 1.6 V core and independent
3.3 V input/output (I/O). MSC8101 power
dissipation is estimated at less than 0.6 W. Figure
1shows a block diagram of the MSC8101
processor.
Note: This document contains information on a new product. Specifications and information herein are subject to change without notice.
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ii
Table of Contents
MSC8101 Features............................................................................................................................................. iii
Target Applications ............................................................................................................................................ iv
Product Documentation...................................................................................................................................... iv
Chapter 1 Signal/ Connection Descriptions
1.1 Signal Groupings..............................................................................................................................................1-1
1.2 Power Signals................................................................................................................................................... 1-4
1.3 Clock Signals ................................................................................................................................................... 1-5
1.4 Reset, Configuration, and EOnCE Event Signals............................................................................................ 1-6
1.5 System Bus, HDI16, and Interrupt Signals ...................................................................................................... 1-8
1.6 Memory Controller Signals............................................................................................................................ 1-16
1.7 Communications Processor Module (CPM) Ports......................................................................................... 1-18
1.8 JTAG Test Access Port Signals...................................................................................................................... 1-45
1.9 Reserved Signals............................................................................................................................................1-46
Chapter 2 Specifications
2.1 Introduction...................................................................................................................................................... 2-1
2.2 Absolute Maximum Ratings ............................................................................................................................ 2-1
2.3 Recommended Operating Conditions .............................................................................................................. 2-2
2.4 Thermal Characteristics ................................................................................................................................... 2-2
2.5 DC Electrical Characteristics ........................................................................................................................... 2-3
2.6 Clock Configuration......................................................................................................................................... 2-4
2.7 AC Timings...................................................................................................................................................... 2-7
Chapter 3 Packaging
3.1 Pin-Out and Package Information....................................................................................................................3-1
3.2 FC-PBGA Package Description.......................................................................................................................3-1
3.3 FC-PBGA Package Mechanical Drawing...................................................................................................... 3-32
Chapter 4 Design Considerations
4.1 Thermal Design Considerations.......................................................................................................................4-1
4.2 Electrical Design Considerations ..................................................................................................................... 4-2
4.3 Power Considerations....................................................................................................................................... 4-2
4.4 Layout Practices............................................................................................................................................... 4-4
Index
Ordering Information, Disclaimer, and Contact Information..................................................................Back Cover
Data Sheet Conventions
OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when
low.)
“asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is low
“deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is high
Examples: Signal/Symbol Logic State Signal State Voltage
PIN True Asserted VIL/VOL
PIN False Deasserted VIH/VOH
PIN True Asserted VIH/VOH
PIN False Deasserted VIL/VOL
Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

iii
MSC8101 Features
• SC140 Core
— Architecture optimized for efficient C/C++ code compilation
— Four 16-bit ALUs and two 32-bit AGUs
— 1200 DSP MIPS, 1200 MMACS, 3000 RISC MIPS, running at 300 MHz
— Very low power dissipation—less than 0.25 W for the core running full speed at 1.6 V
— Variable-Length Execution Set (VLES) execution model
— JTAG/Enhanced OnCE debug port
• 150 MHz Communications Processor Module (CPM)
— Programmable protocol machine using a 32-bit RISC engine
— 155 Mbps ATM interface (including AAL 0/1/2/5)
— 10/100 Mbit Ethernet interface
— Up to four E1/T1 interfaces or one E3/T3 interface and one E1/T1 interface
— HDLC support up to T3 rates, or 256 channels
• 100 MHz 64- or 32-bit Wide Bus Interface
— Support for bursts for high efficiency
— Glueless interface to 60x-compatible bus systems
— Multi-master support
• Enhanced Filter Coprocessor (EFCOP)
— Independently and concurrently executes long filters (such as echo cancellation)
— Runs at 300 MHz and provides 300 MMACS performance
• Programmable Memory Controller
— Control for up to eight banks of external memory
— User-programmable machines (UPM) allowing glueless interface to various memory types
(SRAM, DRAM, EPROM, and Flash memory) and other user-definable peripherals
— Dedicated pipelined SDRAM memory interface
• Large On-Chip SRAM
— 256K 16-bit words (512 KB)
— Unified program and data space configurable by the application
— Word and byte addressable
•DMAController
— 16 DMA channels, FIFO based, with burst capabilities
— Sophisticated addressing capabilities
• Small Foot Print Package
— 17 mm ×17 mm plastic package
• Very Low Power Consumption
— Estimated power consumption of 570 mW for the entire device
— Separate power supply for internal logic (1.6 V) and for I/O (3.3 V)
• Enhanced 16-bit Parallel Host Interface (HDI16)
— Supports a variety of microcontroller, microprocessor, and DSP bus interfaces
• Phase-Lock Loops (PLLs)
—SystemPLL
— CPM DPLLs (SCC and SCM)
• Process Technology
— Uses 0.13 micron copper interconnect process technology

iv
Target Applications
The MSC8101 targets applications requiring very high performance, very large amounts of on-chip
memory, and such networking capabilities as:
• Third-generation wideband wireless infrastructure systems
• Packet Telephony systems
• Multi-channel modem banks
• Multi-channel xDSL
Product Documentation
The documents listed in Table 1 are required for a complete description of the MSC8101 and are
necessary to design properly with the part. Documentation is available from the following sources (see
back cover for detailed information):
• A local Motorola distributor
• A Motorola semiconductor sales office
• A Motorola Literature Distribution Center
• The World Wide Web (WWW)
Table 1. MSC8101 Documentation
Name Description Order Number
MSC8101
Technical Data
MSC8101 features list and physical, electrical, timing, and
package specifications MSC8101/D
MSC8101
User’s Guide
Detailed functional description of the MSC8101 memory
configuration, operation, and register programming MSC8101UG/D
MSC8101
Pocket Guide
Quick reference information for application development. MSC8101PG/D
MSC8101
Reference Manual
Detailed description of the MSC8101 processor core and
instruction set MSC8101RM/D
SC140 DSP Core
Reference Manual
Detailed description of the SC140 family processor core
and instruction set MNSC140DSPCORERM/D
Application Notes Documents describing specific applications or optimized
device operation including code examples See the MSC8101 product website

1-1
Chapter 1
Signal/
Connection
Descriptions
1.1 Signal Groupings
The MSC8101 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1,
and Figure 1-2. Table 1-1 lists the functional groups, the number of signal connections in each group,
and references the table that gives a detailed listing of multiplexed signals within each group. Figure 1-1
shows MSC8101 external signals organized by function. Figure 1-2 indicates how the parallel
input/output (I/O) ports signals are multiplexed. Because the parallel I/O design supported by the
MSC8101 Communications Processor Module (CPM) is a subset of the parallel I/O signals supported by
the MPC8260 device, port pins are not numbered sequentially.
Table 1-1. MSC8101 Functional Signal Groupings
Functional Group Number of Signal
Connections Detailed Description
Power (VCC, VDD, and GND) 80 Table 1-1 on page 1-4
Clock 6 Table 1-2 on page 1-5
Reset, Configuration, and EOnCE 11 Table 1-3 on page 1-6
System Bus, HDI16, and Interrupts 133 Table 1-4 on page 1-8
Memory Controller 27 Table 1-2 on page 1-16
Communications Processor Module (CPM)
Input/Output Parallel Ports Port A 26 Table 1-3 on page 1-19
Port B 14 Table 1-4 on page 1-27
Port C 18 Table 1-5 on page 1-32
Port D 8 Table 1-6 on page 1-42
JTAG Test Access Port 5 Table 1-7 on page 1-45
Reserved (denotes connections that are always reserved) 5 Table 1-8 on page 1-46

1-2
Signal Groupings
P
O
W
E
R
6
0
x
B
U
S
32 ↔A[0–31]
VDD →14 5↔TT[0–4]
VDDH →25 4↔TSIZ[0–3]
VCCSYN →1 1 ↔TBST
VCCSYN1 →1 1 ↔IRQ1 GBL
3→Reserved BADDR[29–31] IRQ[2–3, 5]
GND →37 1↔BR
GNDSYN →1 1 ↔BG
GNDSYN1 →1 1 ↔ABB IRQ2
1↔TS
C
P
M
I
/
O
P
O
R
T
S
1↔AACK
1←ARTRY
For the signals
multiplexed on
Ports A–D,
see Figure 1-2
Port A 1↔DBG
PA[31–6] ↔26 1↔DBB IRQ3
32 ↔D[0–31]
Port B HDI16 Signals
PB[31–18] ↔14 16 ↔D[32–47] HD[0–15]
4↔D[48–51] HA[0–3]
Port C 1↔D52 HCS1
PC[31–22, 15–12, 7–4] ↔18 Single DS Double DS
1↔D53 HRW HRD/HRD
Port D 1↔D54 HDS/HDS HWR/HWR
PD[31–29, 19–16, 7] ↔8 Single HR Double HR
1↔D55 HREQ/HREQ HTRQ/HTRQ
J
T
A
G
1↔D56 HACK/HACK HRRQ/HRRQ
TMS →1 1 ↔D57 HDSP
TDI →1 1 ↔D58 HDDS
TCK →1 1 ↔D59 H8BIT
TRST →1 1 ↔D60 HCS2
TDO ←1 4 ↔D[61–63] Reserved
1←Reserved DP0 Reserved EXT_Br2
EOnCE Event RESET
Configuration 1↔IRQ1 DP1 IRQ1 EXT_BG2
EED ↔1 1 ↔IRQ2 DP2 Reserved EXT_DBG2
EE0 DBREQ ↔1 1 ↔IRQ3 DP3 Reserved EXT_BR3
EE1 HPE ↔1 1 ↔IRQ4 DP4 DREQ3 EXT_BG3
EE[2–3] ↔2 1 ↔IRQ5 DP5 DREQ4 EXT_DBG3
EE[4–5] BTM[0–1] ↔2 1 ↔IRQ6 DP6 DACK3 IRQ6
PORESET →1 1 ↔IRQ7 DP7 DACK4 IRQ7
RSTCONF →1 1 ↔TA
HRESET ↔1 1 ↔TEA
SRESET ↔1 1 ←NMI
1→NMI_OUT
1↔PSDVAL
1↔IRQ7 INT_OUT
M
E
M
C
8→CS[0–7]
CLKIN →1 1 →BCTL1
BNKSEL[0–2] TC[0–2] MODCK[1–3] →3 2 →BADDR[27–28]
CLKOUT ←1 1 →ALE
DLLIN →1 1 →BCTL0
8→PWE[0–7] PSDDQM[0–7] PBS[0–7]
1→PSDA10 PGPL0
1→PSDWE PGPL1
1→POE PSDRAS PGPL2
TEST →1 1 →PSDCAS PGPL3
THERM[1–2] ↔2 1 ↔PGTA PUPMWAIT PPBS PGPL4
SPARE1, SPARE5 ↔2 1 →PSDAMUX PGPL5
Note: Refer to the System Interface Unit (SIU) chapter in the MCS8101 Reference Manual for details on how to configure these pins.
Figure 1-1. MSC8101 External Signals

1-3
Signal Groupings
FCC1
ATM/UTOPIA
MPHY
Master
mux poll
or Slave
MPHY
Master
dir. poll
FCC1
Ethernet
MII
HDLC/
transp. HDLC
Serial Nibble GPIO
TXENB COL PA31
TXCLAV TXCLAV0 CRS RTS PA30
TXSOC TX_ER PA29
RXENB TX_EN PA28
RXSOC RX_DV PA27
RXCLAV RXCLAV0 RX_ER SDMA PA26
TXD0 MSNUM0 PA25
TXD1 MSNUM1 PA24
TXD2 PA23
TXD3 PA22
TXD4 TXD3 TXD3 PA21
TXD5 TXD2 TXD2 PA20
TXD6 TXD1 TXD1 PA19
TXD7 TXD0 TXD TXD0 PA18
RXD7 RXD0 RXD RXD0 PA17
RXD6 RXD1 RXD1 PA16
RXD5 RXD2 RXD2 PA15
RXD4 RXD3 RXD3 PA14
RXD3 MSNUM2 PA13
RXD2 SI1 MSNUM3 PA12
RXD1 TDMA1 MSNUM4 PA11
RXD0 SMC2 Serial Nibble MSNUM5 PA10
SMTXD L1TXD L1TXD0 PA9
FCC2 SMRXD L1RXD L1RXD0 PA8
Ethernet
MII
HDLC/
transp. HDLC SMSYN L1TSYNC SI2 PA7
Serial Nibble SCC2 L1RSYNC TDMB2 PA6
TX_ER RXD L1TXD PB31
RX_DV TXD L1RXD PB30
TX_EN L1RSYNC PB29
RX_ER RTS RTS/TENA L1TSYNC PB28
COL TDMC2
L1TXD PB27
CRS L1RXD PB26
TXD3 TXD3 L1TXD3 L1TSYNC PB25
TXD2 TXD2 L1RXD3 L1RSYNC PB24
TXD1 TXD1 L1RXD2 TDMD2
L1TXD PB23
TXD0 TXD TXD0 L1RXD1 L1RXD PB22
RXD0 RXD RXD0 L1TXD2 L1TSYNC PB21
RXD1 RXD1 L1TXD1 L1RSYNC I2CPB20
RXD2 RXD2 SDA PB19
RXD3 RXD3 SCL BRGs Clocks Timers PB18
Ext. Req. BRG1O CLK1 TGATE1 PC31
EXT1 BRG2O CLK2 TOUT1 PC30
SCC1
CTS/CLSN BRG3O CLK3 TIN2 PC29
CTS/CLSN SIU Timer Input BRG4O CLK4 TIN1/
TOUT2 PC28
CLK5 BRG5O CLK5 TGATE2 PC27
TMCLK BRG6O CLK6 TOUT3 PC26
DMA
DACK2 BRG7O CLK7 TIN4 PC25
Ext. Req. DREQ2 BRG8O CLK8 TIN3/
TOUT4 PC24
EXT2 DACK1 CLK9 PC23
SCC1 LIST1 DREQ1 CLK10 PC22
TXADDR0 CTS/CLSN SMTXD PC15
RXADDR0 CD/RENA LIST2 PC14
TXADDR1 CTS/CLSN LIST4 PC13
RXADDR1 FCC1 CD/RENA LIST3 PC12
TXADDR2 TXADDR2/
TXCLAV1 CTS LIST1 PC7
RXADDR2 RXADDR2/
RXCLAV1 CD LIST2 PC6
FCC2 SMC1
CTS SMTXD LIST3 PC5
CD SMRXD LIST4 PC4
RXD DRACK1/DONE1 PD31
TXD DRACK2/DONE2 PD30
RXADDR3 RXCLAV2 RTS/TENA SPI PD29
TXADDR4 TXCLAV3 SPISEL BRG1O PD19
RXADDR4 RXCLAV3 SPICLK PD18
RXPRTY SPIMOSI BRG2O PD17
TXPRTY SPIMISO PD16
TXADDR3 TXCLAV2 SMSYN PD7
Figure 1-2. CPM Port A–D Pin Multiplexed Functionality

1-4
Power Signals
1.2 Power Signals
Table 1-1. Power and Ground Signal Inputs
Power Name Description
VDD Internal Logic Power
VDD dedicated for use with the device core. The voltage should be well-regulated and the
input should be provided with an extremely low impedance path to the VDD power rail.
VDDH Input/Output Power
This source supplies power for the I/O buffers. The user must provide adequate external
decoupling capacitors.
VCCSYN System PLL Power
VCC dedicated for use with the system Phase Lock Loop (PLL). The voltage should be
well-regulated and the input should be provided with an extremely low impedance path to the
VCC power rail.
VCCSYN1 SC140 PLL Power
VCC dedicated for use with the SC140 core PLL. The voltage should be well-regulated and
the input should be provided with an extremely low impedance path to the VCC power rail.
GND System Ground
An isolated ground for the internal processing logic. This connection must be tied externally
to all chip ground connections, except GNDSYN and GNDSYN1. The user must provide
adequate external decoupling capacitors.
GNDSYN System PLL Ground
Ground dedicated for system PLL use. The connection should be provided with an extremely
low-impedance path to ground.
GNDSYN1 SC140 PLL Ground 1
Ground dedicated for SC140 core PLL use. The connection should be provided with an
extremely low-impedance path to ground.

1-5
Clock Signals
1.3 Clock Signals
Table 1-2. Clock Signals
Signal
Name Type Signal Description
CLKIN Input Clock In
Primary clock input to the MSC8101 PLL.
MODCK1
TC0
BNKSEL0
Input
Output
Output
Clock Mode Input 1
Defines the operating mode of internal clock circuits.
Transfer Code 0
Supplies information that can be useful for debugging bus transactions initiated by the
MSC8101.
Bank Select 0
Selects the SDRAM bank when the MSC8101 is in 60x-compatible bus mode.
MODCK2
TC1
BNKSEL1
Input
Output
Output
Clock Mode Input 2
Defines the operating mode of internal clock circuits.
Transfer Code 1
Supplies information that can be useful for debugging bus transactions initiated by the
MSC8101.
Bank Select 1
Selects the SDRAM bank when the MSC8101 is in 60x-compatible bus mode.
MODCK3
TC2
BNKSEL2
Input
Output
Output
Clock Mode Input 3
Defines the operating mode of internal clock circuits.
Transfer Code 2
Supplies information that can be useful for debugging bus transactions initiated by the
MSC8101.
Bank Select 2
Selects the SDRAM bank when the MSC8101 is in 60x-compatible bus mode.
CLKOUT Output Clock Out
The system bus clock.
DLLIN Input DLLIN
Synchronizes with an external device.

1-6
Reset, Configuration, and EOnCE Event Signals
1.4 Reset, Configuration, and EOnCE Event Signals
Table 1-3. Reset, Configuration, and EOnCE Event Signals
Signal Name Type Signal Description
DBREQ
EE01
Input
Input
Output
Debug Request
Determines whether to go into SC140 Debug mode when PORESET is deasserted.
Enhanced OnCE (EOnCE) Event 0
After PORESET is deasserted, you can configure EE0 as an input (default) or an output.
Debug request, enable Address Event Detection Channel 0, or generate one of the
EOnCE events.
Detection by Address Event Detection Channel 0. Used to trigger external debugging
equipment.
HPE
EE11
Input
Input
Output
Host Port Enable
When this pin is asserted during PORESET, the Host port is enabled, the system data bus
is 32 bits wide, and the Host
must program the reset configuration word.
EOnCE Event 1
After PORESET is deasserted, you can configure EE1 as an input (default) or an output.
Enable Address Event Detection Channel 1 or generate one of the EOnCE events.
Debug Acknowledge or detection by Address Event Detection Channel 1. Used to trigger
external debugging equipment.
EE21
Input
Output
EOnCE Event 2
After PORESET is deasserted, you can configure EE2 as an input (default) or an output.
Enable Address Event Detection Channel 2 or generate one of the EOnCE events or
enable the Event Counter.
Detection by Address Event Detection Channel 2. Used to trigger external debugging
equipment.
EE31
Input
Output
EOnCE Event 3
After PORESET is deasserted, you can configure EE3 as an input (default) or an output.
See the
Emulation and Debug chapter in the SC140 DSP Core Reference Manual for
details on the ERCV Register.
Enable Address Event Detection Channel 3 or generate one of the EOnCE events.
EOnCE Receive Register (ERCV) was read by the DSP. Used to trigger external
debugging equipment.

1-7
Reset, Configuration, and EOnCE Event Signals
BTM[0–1]
EE41
EE51
Input
Input
Output
Input
Output
Boot Mode 0–1
Determines the MSC8101 boot mode when PORESET is deasserted. See the
Emulation
and Debug
chapter in the SC140 DSP Core Reference Manual for details on how to set
these pins.
EOnCE Event 4
After PORESET is deasserted, you can configure EE4 as an input (default) or an output.
See the
Emulation and Debug chapter in the SC140 DSP Core Reference Manual for
details on the ETRSMT Register.
Enable Address Event Detection Channel 4 or generate one of the EOnCE events
EOnCE Transmit Register (ETRSMT) was written by the DSP. Used to trigger external
debugging equipment.
EOnCE Event 5
After PORESET is deasserted, you can configure EE5 as an input (default) or an output.
Enable Address Event Detection Channel 5.
Detection by Address Event Detection Channel 5. Used to trigger external debugging
equipment.
EED1
Input
Output
Enhanced OnCE (EOnCE) Event Detection
After PORESET is deasserted, you can configure EED as an input (default) or output:
Enable the Data Event Detection Channel.
Detection by the Data Event Detection Channel. Used to trigger external debugging
equipment.
PORESET Input Power-On Reset
When asserted, this line causes the MSC8101 to enter power-on reset state.
RSTCONF Input Reset Configuration
Used during reset configuration sequence of the chip. A detailed explanation of its function
is provided in the “Power-On Reset Flow” and “Hardware Reset Configuration” sections of
the
MSC8101 Reference Manual .
HRESET Input Hard Reset
When asserted, this open-drain line causes the MSC8101 to enter hard reset state.
SRESET Input Soft Reset
When asserted, this open-drain line causes the MSC8101 to enter soft reset state.
Note: See the
Emulation and Debug chapter in the SC140 DSP Core Reference Manual for details on how to
configure these pins.
Table 1-3. Reset, Configuration, and EOnCE Event Signals (Continued)
Signal Name Type Signal Description

1-8
System Bus, HDI16, and Interrupt Signals
1.5 System Bus, HDI16, and Interrupt Signals
The system bus, HDI16, and interrupt signals are grouped together because they use a common set of
signal lines. Individual assignment of a signal to a specific signal line is configured through registers in
the System Interface Unit (SIU) and the Host Interface (HDI16). Table 1-4 describes the signals in this
group.
Note: To boot from the host interface, the HDI16 must be enabled by pulling up the HPE signal line
during PORESET. If the HPE signal is pulled up, the configuration word must then be loaded
from the host. The configuration word must set the Internal Space Port Size bit in the Bus
Control Register (BCR[ISPS]) to change the system data bus width from 64 bits to 32 bits and
reassign the upper 32 bits to their HDI16 functions. Never set the Host Port Enable (HEN) bit in
the Host Port Control Register (HPCR) to enable the HDI16, unless the bus size is first changed
from 64 bits to 32 bits by setting the BCR[ISPS] bit. Otherwise, unpredictable operation may
occur.
Although there are eight interrupt request (IRQ) connections to the core processor, there are multiple
external lines that can connect to these internal signal lines. After reset, the default configuration includes
two IRQ1 and two IRQ7 input lines. The designer must select one line for each required interrupt and
reconfigure the other external signal line or lines for alternate functions.
Table 1-4. System Bus, HDI16, and Interrupt Signals
Signal Data Flow Description
A[0–31] Input/Output Address Bus
When the MSC8101 is in external master bus mode, these pins function as the
address bus. The MSC8101 drives the address of its internal bus masters and
responds to addresses generated by external bus masters. When the MSC8101 is
in Internal Master Bus mode, these pins are used as address lines connected to
memory devices and are controlled by the MSC8101 memory controller.
TT[0–4] Input/Output Bus Transfer Type
The bus master drives these pins during the address tenure to specify the type of
transaction.
TSIZ[0–3] Input/Output Transfer Size
The bus master drives these pins with a value indicating the number of bytes
transferred in the current transaction.
TBST Input/Output Bus Transfer Burst
The bus master asserts this pin to indicate that the current transaction is a burst
transaction (transfers four quad words).
IRQ1
GBL
Input
Input/Output
Interrupt Request 11
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Global1
When a master within the chip initiates a bus transaction, it drives this pin. When
an external master initiates a bus transaction, it should drive this pin. Assertion of
this pin indicates that the transfer is global and it should be snooped by caches in
the system.

1-9
System Bus, HDI16, and Interrupt Signals
Reserved
BADDR29
IRQ2
Output
Output
Input
The primary configuration is reserved.
Burst Address 291
One of five outputs of the memory controller. These pins connect directly to
memory devices controlled by the MSC8101 memory controller.
Interrupt Request 21
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Reserved
BADDR30
IRQ3
Output
Output
Input
The primary configuration is reserved.
Burst Address 301
One of five outputs of the memory controller. These pins connect directly to
memory devices controlled by the MSC8101 memory controller.
Interrupt Request 31
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Reserved
BADDR31
IRQ5
Output
Output
Input
The primary configuration is reserved.
Burst Address 311
One of five outputs of the memory controller. These pins connect directly to
memory devices controlled by the MSC8101 memory controller.
Interrupt Request 51
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
BR Input/Output
Output
Input
Bus Request2
An output when an external arbiter is used. The MSC8101 asserts this pin to
request ownership of the bus.
An input when an internal arbiter is used. An external master should assert this pin
to request bus ownership from the internal arbiter.
BG Input/Output
Output
Input
Bus Grant2
An output when an internal arbiter is used. The MSC8101 asserts this pin to grant
bus ownership to an external bus master.
An input when an external arbiter is used. The external arbiter should assert this
pin to grant bus ownership to the MSC8101.
ABB
IRQ2
Input/Output
Output
Input
Input
Address Bus Busy1
TheMSC8101asserts thispin for the duration oftheaddress bus tenure. Following
an address acknowledge (AACK) signal, which terminates the address bus tenure,
the MSC8101 deasserts ABB for a fraction of a bus cycle and then stops driving
this pin.
The MSC8101 does not assume bus ownership as long as it senses that this pin is
asserted by an external bus master.
Interrupt Request 21
One of the eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued)
Signal Data Flow Description

1-10
System Bus, HDI16, and Interrupt Signals
TS Input/Output Bus Transfer Start
Signals the beginning of a new address bus tenure. The MSC8101 asserts this
signal when one of its internal bus masters (SC140 core or DMA) begins an
address tenure. When the MSC8101 senses this pin being asserted by an external
bus master, it responds to the address bus tenure as required (snoop if enabled,
access internal MSC8101 resources, memory controller support).
AACK Input/Output Address Acknowledge
A bus slave asserts this signal to indicate that it identified the address tenure.
Assertion of this signal terminates the address tenure.
ARTRY Input Address Retry
Assertion of this signal indicates that the bus transaction should be retried by the
bus master. The MSC8101 asserts this signal to enforce data coherency with its
internal cache and to prevent deadlock situations.
DBG Input/Output
Output
Input
Data Bus Grant2
An output when an internal arbiter is used. The MSC8101 asserts this pin as an
output to grant data bus ownership to an external bus master.
An input when an external arbiter is used. The external arbiter should assert this
pin as an input to grant data bus ownership to the MSC8101.
DBB
IRQ3
Input/Output
Output
Input
Input
Data Bus Busy1
The MSC8101 asserts this pin as an output for the duration of the data bus tenure.
Following a TA, which terminates the data bus tenure, the MSC8101 deasserts
DBB for a fraction of a bus cycle and then stops driving this pin.
The MSC8101 does not assume data bus ownership as long as it senses DBB is
asserted by an external bus master.
Interrupt Request 31
One of the eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
D[0–31] Input/Output Data Bus Most Significant Word
In write transactions the bus master drives the valid data on this bus. In read
transactions the slave drives the valid data on this bus. In Host Port Disabled
mode, these 32 bits are part of the 64-bit data bus. In Host Port Enabled mode,
these bits are used as the bus in 32-bit mode.
D[32–47]
HD[0–15]
Input/Output
Input/Output
Data Bus Bits 32–47
In write transactions the bus master drives the valid data on this bus. In read
transactions the slave drives the valid data on this bus.
Host Data2
When the HDI16 interface is enabled, these signals are lines 0-15 of the
bidirectional tri-state data bus.
D[48–51]
HA[0–3]
Input/Output
Input
Data Bus Bits 48–51
In write transactions the bus master drives the valid data on these pins. In read
transactions the slave drives the valid data on these pins.
Host Address Line 0–33
When the HDI16 interface bus is enabled, these lines address internal host
registers.
Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued)
Signal Data Flow Description

1-11
System Bus, HDI16, and Interrupt Signals
D52
HCS1
Input/Output
Input
Data Bus Bit 52
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Chip Select3
When the HDI16 interface is enabled, this is one of the two chip-select pins. The
HDI16 chip select is a logical OR of HCS1 and HCS2.
D53
HRW
HRD/HRD
Input/Output
Input
Input
Data Bus Bit 53
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Read Write Select3
When the HDI16 interface is enabled in Single Strobe mode, this is the read/write
input (HRW).
Host Read Strobe3
When the HDI16 is programmed to interface with a double data strobe host bus,
this pin is the read data strobe Schmitt trigger input (HRD/HRD). The polarity of the
data strobe is programmable.
D54
HDS/HDS
HWR/HWR
Input/Output
Input
Input
Data Bus Bit 54
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Data Strobe3
When the HDI16 is programmed to interface with a single data strobe host bus, this
pin is the data strobe Schmitt trigger input (HDS/HDS). The polarity of the data
strobe is programmable.
Host Write Data Strobe3
When the HDI16 is programmed to interface with a double data strobe host bus,
this pin is the write data strobe Schmitt trigger input (HWR/HWR). The polarity of
the data strobe is programmable.
D55
HREQ/HREQ
HTRQ/HTRQ
Input/Output
Output
Output
Data Bus Bit 55
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Request3
When the HDI16 is programmed to interface with a single host request host bus,
this pin is the host request output (HREQ/HREQ). The polarity of the host request
is programmable. The host request may be programmed as a driven or open-drain
output.
Transmit Host Request3
When the HDI16 is programmed to interface with a double host request host bus,
this pin is the transmit host request output (HTRQ/HTRQ). The signal can be
programmed as driven or open drain. The polarity of the host request is
programmable.
Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued)
Signal Data Flow Description

1-12
System Bus, HDI16, and Interrupt Signals
D56
HACK/HACK
HRRQ/HRRQ
Input/Output
Output
Output
Data Bus Bit 56
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Acknowledge3
When the HDI16 is programmed to interface with a single host request host bus,
this pin is the host acknowledge Schmitt trigger input (HACK). The polarity of the
host acknowledge is programmable.
Receive Host Request3
When the HDI16 is programmed to interface with a double host request host bus,
this pin is the receive host request output (HRRQ/HRRQ). The signal can be
programmed as driven or open drain. The polarity of the host request is
programmable.
D57
HDSP
Input/Output
Input
Data Bus Bit 57
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Data Strobe Polarity3
When the HDI16 interface is enabled, this pin is the host data strobe polarity
(HDSP).
D58
HDDS
Input/Output
Input
Data Bus Bit 58
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Dual Data Strobe3
When the HDI16 interface is enabled, this pin is the host dual data strobe (HDDS).
D59
H8BIT
Input/Output
Input
Data Bus Bit 59
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
H8BIT3
When the HDI16 interface is enabled, this bit determines if the interface is in 8-bit
or 16-bit mode.
D60
HCS2
Input/Output
Input
Data Bus Bit 60
In write transactions the bus master drives the valid data on this pin. In read
transactions the slave drives the valid data on this pin.
Host Chip Select 3
When the HDI16 interface is enabled, this is one of the two chip-select pins. The
HDI16 chip select is a logical OR of HCS1 and HCS2.
D[61–63]
Reserved
Input/Output Data Bus Bits 61–63
Used only in 60x-mode-only mode. In write transactions the bus master drives the
valid data on this bus. In read transactions the slave drives the valid data on this
bus.
These dedicated signals are reserved when the HDI16 is enabled.3
Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued)
Signal Data Flow Description

1-13
System Bus, HDI16, and Interrupt Signals
Reserved
DP0
EXT_BR2
Input
Input/Output
Input
The primary configuration is reserved.
Data Parity 01
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity zero pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 0 and D[0–7].
External Bus Request 21,2
An external master asserts this pin to request bus ownership from the internal
arbiter.
IRQ1
DP1
EXT_BG2
Input
Input/Output
Output
Interrupt Request 11
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 11
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity one pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 1 and D[8–15].
External Bus Grant 21,2
The MSC8101 asserts this pin to grant bus ownership to an external bus master.
IRQ2
DP2
EXT_DBG2
Input
Input/Output
Output
Interrupt Request 21
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 21
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity two pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 2 and D[16–23].
External Data Bus Grant 21,2
The MSC8101 asserts this pin to grant data bus ownership to an external bus
master.
IRQ3
DP3
EXT_BR3
Input
Input/Output
Input
Interrupt Request 31
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 31
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity three pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 3 and D[24–31].
External Bus Request 31,2
An external master asserts this pin to request bus ownership from the internal
arbiter.
Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued)
Signal Data Flow Description

1-14
System Bus, HDI16, and Interrupt Signals
IRQ4
DP4
DREQ3
EXT_BG3
Input
Input/Output
Input
Output
Interrupt Request 41
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 41
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity four pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 4 and D[32–39].
DMA Request 31
An external peripheral uses this pin to request DMA service.
External Bus Grant 31,2
The MSC8101 asserts this pin to grant bus ownership to an external bus master.
IRQ5
DP5
DREQ4
EXT_DBG3
Input
Input/Output
Input
Output
Interrupt Request 51
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 51
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity five pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 5 and D[40–47].
DMA Request 41
An external peripheral uses this pin to request DMA service.
External Data Bus Grant 31,2
The MSC8101 asserts this pin to grant data bus ownership to an external bus
master.
IRQ6
DP6
DACK3
Input
Input/Output
Output
Interrupt Request 61
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 61
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity six pin should give odd parity (odd number of ones) on the
group of signals that includes data parity 6 and D[48–55].
DMA Acknowledge 31
The DMA drives this output to acknowledge the DMA transaction on the bus.
IRQ7
DP7
DACK4
Input
Input/Output
Output
Interrupt Request 71
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 71
The master or slave that drives the data bus also drives the data parity signals. The
value driven on the data parity seven pin should give odd parity (odd number of
ones) on the group of signals that includes data parity 7 and D[56–63].
DMA Acknowledge1
The DMA drives this output to acknowledge the DMA transaction on the bus.
TA Input/Output Transfer Acknowledge
Indicates that a data beat is valid on the data bus. For single beat transfers,
assertion of TA indicates the termination of the transfer. For burst transfers, TA is
asserted four times to indicate the transfer of four data beats with the last assertion
indicating the termination of the burst transfer.
Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued)
Signal Data Flow Description

1-15
System Bus, HDI16, and Interrupt Signals
TEA Input/Output Transfer Error Acknowledge
Indicates a bus error. masters within the MSC8101 monitor the state of this pin.
The MSC8101 internal bus monitor can assert this pin if it identifies a bus transfer
that is hung.
NMI Input Non-Maskable Interrupt
When an external device asserts this line, the MSC8101 NMI input is asserted.
NMI_OUT Output Non-Maskable Interrupt
Driven from the MSC8101 internal interrupt controller. Assertion of this output
indicates that a non-maskable interrupt, pending in the MSC8101 internal interrupt
controller, is waiting to be handled by an external host.
PSDVAL Input/Output Data Valid
Indicates that a data beat is valid on the data bus. The difference between the TA
pin and PSDVAL is that the TA pin is asserted to indicate data transfer terminations
while the PSDVAL signal is asserted with each data beat movement. Thus, when
TA is asserted, PSDVAL is asserted, but when PSDVAL is asserted, TA is not
necessarily asserted. For example when the SDMA initiates a double word (2x64
bits) transfer to a memory device that has a 32-bit port size, PSDVAL is asserted
three times without TA, and finally both pins are asserted to terminate the transfer.
IRQ7
INT_OUT
Input
Output
Interrupt Request 71
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Interrupt Output1
Driven from the MSC8101 internal interrupt controller. Assertion of this output
indicates that an unmasked interrupt is pending in the MSC8101 internal interrupt
controller.
Notes: 1. See the
System Interface Unit (SIU) chapter in the MCS8101 Reference Manual for details on how to
configure these pins.
2. When used as the bus control arbiter for the system bus, the MSC8101 can support up to three
external bus masters. Each master uses its own set of Bus Request, Bus Grant, and Data Bus Grant
signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3).
Each of these signal sets must be configured to indicate whether the external master is or is not a
MSC8101 master device. See the Bus Configuration Register (BCR) description in the
System
Interface Unit (SIU)
chapter in the MCS8101 Reference Manual for details on how to configure these
pins. The second and third set of pins is defined by EXT_xxx to indicate that they can only be used
with external master devices. The first set of pins (BR/BG/DBG) have a dual function. When the
MSC8101 is not the bus arbiter, these signals (BR/BG/DBG) are used by the MSC8101 to obtain
master control of the bus.
3. See the
Host Interface (HDI16) chapter in the MCS8101 Reference Manual for details on how to
configure these pins.
Table 1-4. System Bus, HDI16, and Interrupt Signals (Continued)
Signal Data Flow Description

1-16
Memory Controller Signals
1.6 Memory Controller Signals
Refer to the Memory Controller chapter in the MSC8101 Reference Manual (MSC8101RM/D) for
detailed information about configuring these signals.
Table 1-2. Memory Controller Signals
Signal Data
Flow Description
CS[0–7] Output Chip Select
Enable specific memory devices or peripherals connected to MSC8101 buses.
BCTL1 Output Buffer Control 1
Controls buffers on the data bus. Usually used with BCTL0. The exact function of
this pin is defined by the value of SIUMCR[BCTLC]. See the
System Interface Unit
(SIU)
chapter in the MS8101 Technical Reference manual for details.
BADDR[27–28] Output Burst Address 27–28
Two of five outputs of the memory controller. These pins connect directly to
memory devices controlled by the MSC8101 memory controller.
ALE Output Address Latch Enable
Controls the external address latch used in external master bus configuration.
BCTL0 Output Buffer Control 0
Controls buffers on the data bus. The exact function of this pin is defined by the
value of SIUMCR[BCTLC]. See the
System Interface Unit (SIU) chapter in the
MS8101 Technical Reference manual for details.
PWE[0–7]
PSDDQM[0–7]
PBS[0–7]
Output
Output
Output
Bus Write Enable
Outputs of the bus General-Purpose Chip-select Machine (GPCM). These pins
select byte lanes for write operations.
Bus SDRAM DQM
Outputs of the SDRAM control machine. These pins select specific byte lanes of
SDRAM devices.
Bus UPM Byte Select
Outputs of the User-Programmable Machine (UPM) in the memory controller.
These pins select specific byte lanes during memory operations. The timing of
these pins is programmed in the UPM. The actual driven value depends on the
address and size of the transaction and the port size of the accessed device.
PSDA10
PGPL0
Output
Output
Bus SDRAM A10
Output from the bus SDRAM controller. This pin is part of the address when a row
address is driven. It is part of the command when a column address is driven.
Bus UPM General-Purpose Line 0
One of six general-purpose output lines of the UPM. The values and timing of this
pin are programmed in the UPM.
PSDWE
PGPL1
Output
Output
Bus SDRAM Write Enable
Outputfrom the bus SDRAM controller. This pin should connect to the SDRAM WE
input signal.
Bus UPM General-Purpose Line 1
One of six general-purpose output lines from the UPM. The values and timing of
this pin are programmed in the UPM.