Motorola DSP56600 User manual

Motorola’s High-Performance DSP Technology
APR20/D
DSP56300/DSP56600
Application
Optimization
forthe
DigitalSignal
Processors

MOTOROLA Optimizing DSP56300/DSP56600 Applications iii
TABLE OF CONTENTS
SECTION 1 INTRODUCTION . . . . . . . . . . . . . . . 1-1
1.1 DSP56300 CORE FAMILY . . . . . . . . . . . . . . 1-1
1.2 DSP56600 CORE FAMILY . . . . . . . . . . . . . . 1-2
1.3 ENHANCEMENTS OVER THE DSP56000. . 1-3
1.3.1 Instruction Set Enhancements. . . . . . . . . . 1-3
1.3.2 Architectural Enhancements . . . . . . . . . . . 1-5
1.4 APPLICATION NOTE STRUCTURE. . . . . . . 1-6
1.4.1 DSP56300 and DSP56600 Features
Description and Use . . . . . . . . . . . . . . . . . 1-6
1.4.2 Optimizing the Code for Best Performance 1-7
1.4.3 Appendixes . . . . . . . . . . . . . . . . . . . . . . . . 1-8
SECTION 2 DATA OPERATIONS. . . . . . . . . . . . 2-1
2.1 USING THE DUAL DATA PATHS . . . . . . . . . 2-1
2.2 16-BIT ARITHMETIC MODE
(DSP56300 ONLY). . . . . . . . . . . . . . . . . . . . . 2-6
2.3 THE MAX INSTRUCTION . . . . . . . . . . . . . . . 2-7
2.4 USING THE BARREL SHIFTER . . . . . . . . . . 2-8
2.5 BIT MANIPULATION INSTRUCTIONS . . . . 2-10
2.6 DOUBLE PRECISION ARITHMETIC. . . . . . 2-11
2.7 USING LESS STRAIGHT-FORWARD
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . 2-13
SECTION 3 PROGRAM CONTROL . . . . . . . . . . 3-1
3.1 HARDWARE LOOPS. . . . . . . . . . . . . . . . . . . 3-1
3.2 THE HARDWARE STACK. . . . . . . . . . . . . . . 3-3
3.3 USING THE STACK EXTENSION. . . . . . . . . 3-7
3.4 TASK SWITCHING WITH THE STACK
EXTENSION . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.5 CONDITIONAL DALU INSTRUCTIONS . . . 3-11
3.6 PC RELATIVE INSTRUCTIONS . . . . . . . . . 3-13
3.7 USING FAST INTERRUPTS . . . . . . . . . . . . 3-17

iv Optimizing DSP56300/DSP56600 Applications MOTOROLA
SECTION 4 USING THE DMA . . . . . . . . . . . . . . .4-1
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . .4-1
4.2 CONSERVING CORE MIPS BY WORKING IN
PARALLEL. . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.3 USING SLOW, LOW-COST MEMORIES . . . .4-4
4.4 SERVICING A PERIPHERAL . . . . . . . . . . . . .4-6
4.5 DATA TRANSFER OPTIMIZATION HINTS. .4-12
SECTION 5 INSTRUCTION CACHE AND
MEMORY FEATURES . . . . . . . . . . .5-1
5.1 THE INSTRUCTION CACHE. . . . . . . . . . . . . .5-1
5.1.1 Cache Sectors. . . . . . . . . . . . . . . . . . . . . . .5-3
5.1.2 Control of Sector Allocation. . . . . . . . . . . . .5-4
5.1.3 Cache Burst Mode. . . . . . . . . . . . . . . . . . . .5-6
5.2 MEMORY SWITCH . . . . . . . . . . . . . . . . . . . . .5-9
5.3 USING THE BOOTSTRAP ROM. . . . . . . . . .5-11
SECTION 6 PIPELINE INTERLOCKS . . . . . . . . .6-1
6.1 DATA ALU PIPELINE INTERLOCKS . . . . . . .6-1
6.1.1 What are the Data ALU Pipeline
Interlocks?. . . . . . . . . . . . . . . . . . . . . . . . . .6-2
6.1.2 Avoiding Data ALU Pipeline Interlocks . . . .6-3
6.1.2.1 Code Reorder. . . . . . . . . . . . . . . . . . . . .6-3
6.1.2.2 Loop Unrolling. . . . . . . . . . . . . . . . . . . . .6-4
6.1.2.2.1 Loop Unrolling in N Array Scale
Routine. . . . . . . . . . . . . . . . . . . . . . . .6-4
6.1.2.2.2 Unrolling in Memory Array Copy
Routine. . . . . . . . . . . . . . . . . . . . . . . .6-5
6.1.2.3 Saving Interlocks by Using the TFR
Instruction. . . . . . . . . . . . . . . . . . . . . . . .6-6
6.2 ADDRESS GENERATION PIPELINE
INTERLOCKS . . . . . . . . . . . . . . . . . . . . . . . . .6-7
6.2.1 What are the Address Generation Pipeline
Interlocks. . . . . . . . . . . . . . . . . . . . . . . . . . .6-7
6.2.2 Avoiding Address Generation Pipeline
Interlocks. . . . . . . . . . . . . . . . . . . . . . . . . . .6-8

MOTOROLA Optimizing DSP56300/DSP56600 Applications v
6.3 STACK EXTENSION DELAYS . . . . . . . . . . . 6-8
6.3.1 Stack Extension Full/Empty Cases . . . . . . 6-9
6.3.2 Avoiding Stack Extension Delays . . . . . . . 6-9
6.4 PROGRAM FLOW-CONTROL PIPELINE
INTERLOCKS . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.4.1 What are the Program Flow-Control Pipeline
Interlocks?. . . . . . . . . . . . . . . . . . . . . . . . 6-10
6.4.1.1 MOVE to the Status Register (SR) . . . 6-10
6.4.1.2 MOVE to the System Stack High/Low
(SSH/SSL) . . . . . . . . . . . . . . . . . . . . . 6-11
6.4.1.3 JMP to Last Addresses of a Do-Loop
(LA or LA-1) . . . . . . . . . . . . . . . . . . . . 6-11
6.4.1.4 RTI to Last Addresses of a Do-Loop
(LA or LA-1) . . . . . . . . . . . . . . . . . . . . 6-11
6.4.1.5 MOVE from the System Stack High
(SSH) . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.4.1.6 Conditional Instructions. . . . . . . . . . . . 6-11
6.4.2 Avoiding Program Flow-Control Pipeline
Interlocks. . . . . . . . . . . . . . . . . . . . . . . . . 6-11
SECTION 7 COMPACT OPCODE USE . . . . . . . 7-1
7.1 CYCLE COUNT OF AN INSTRUCTION . . . . 7-1
7.1.1 Opening small REP and DO Loops. . . . . . 7-1
7.1.2 Replacing Jumps with Conditional Execution
Instructions . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.1.3 Inverting Condition in Conditional Jump
Instructions . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.2 ADDRESSING MODES. . . . . . . . . . . . . . . . . 7-5
7.2.1 Single Cycle Addressing Modes . . . . . . . . 7-5
7.2.2 Short Addressing Mode. . . . . . . . . . . . . . . 7-5
7.2.3 Short Immediate Mode . . . . . . . . . . . . . . . 7-6
7.2.4 Short Immediate Operands . . . . . . . . . . . . 7-6
7.2.5 Register Addressing . . . . . . . . . . . . . . . . . 7-6
7.2.6 Word Count . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.3 PERIPHERAL ADDRESSING . . . . . . . . . . . . 7-7
7.4 SPECIAL INSTRUCTIONS . . . . . . . . . . . . . . 7-7

vi Optimizing DSP56300/DSP56600 Applications MOTOROLA
7.4.1 Dual Data Spaces . . . . . . . . . . . . . . . . . . . .7-7
7.4.2 Using the TFR instructions . . . . . . . . . . . . .7-8
7.4.3 Clearing Registers. . . . . . . . . . . . . . . . . . . .7-8
APPENDIX A SAVING POWER. . . . . . . . . . . . . . . A-1
A.1 LOW POWER MODES . . . . . . . . . . . . . . . . . A-1
A.1.1 Wait Standby Mode. . . . . . . . . . . . . . . . . . A-1
A.1.2 Stop Standby Mode. . . . . . . . . . . . . . . . . . A-2
A.1.3 Low-Power Clock Divider . . . . . . . . . . . . . A-2
A.2 DISABLING FUNCTIONAL BLOCKS . . . . . . A-3
APPENDIX B DEBUG AND TEST SUPPORT. . . . B-1
B.1 ONCE PORT FEATURES . . . . . . . . . . . . . . . B-1
B.2 JTAG PORT FEATURES. . . . . . . . . . . . . . . . B-2
B.3 ADDRESS TRACING . . . . . . . . . . . . . . . . . . B-3
APPENDIX C USING THE PROFILER . . . . . . . . . C-1
C.1 SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
C.2 CREATING A PROFILER . . . . . . . . . . . . . . . C-1
C.3 THE PROFILING REPORT . . . . . . . . . . . . . . C-2
C.3.1 Basic Report . . . . . . . . . . . . . . . . . . . . . . . C-2
C.3.2 Symbol Report. . . . . . . . . . . . . . . . . . . . . . C-3
C.3.3 Instruction Set Usage Report . . . . . . . . . . C-3
C.3.4 Code Coverage Report . . . . . . . . . . . . . . . C-5
C.3.5 Basic Subroutine Report . . . . . . . . . . . . . . C-6
C.3.6 Subroutine Call Graph Report. . . . . . . . . . C-6
C.3.7 Subroutine Dependency Report . . . . . . . . C-7
C.3.8 Subroutine Call Report . . . . . . . . . . . . . . . C-8
C.4 USING THE PROFILE REPORT. . . . . . . . . . C-8

MOTOROLA Optimizing DSP56300/DSP56600 Applications vii
LIST OF FIGURES
Figure 2-1 The Fast Normalization Operation for the
DSP56300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Figure 2-2 48 × 48-bit Multiplication with 48 Bits of the Result
Kept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Figure 3-1 State of the Stack When IRQA Is Serviced. . . . 3-5
Figure 4-1 DMA Addressing Modes for SCI
Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Figure 5-1 DSP56302 Memory Maps. . . . . . . . . . . . . . . . 5-10

viii Optimizing DSP56300/DSP56600 Applications MOTOROLA
LIST OF TABLES
Table 1-1 New Instructions in DSP56300 and
DSP56600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3
Table 2-1 Parallel Move Instructions . . . . . . . . . . . . . . . . .2-2
Table 2-2 Registers Used in Parallel XY Moves . . . . . . . .2-4
Table 2-3 Registers used in Long Addressing. . . . . . . . . .2-5
Table 2-4 Data Operations Using Multi-shift . . . . . . . . . . .2-8
Table 2-5 Bit manipulation instructions . . . . . . . . . . . . . .2-10
Table 3-1 Implicit Stack Activity . . . . . . . . . . . . . . . . . . . . .3-4
Table 3-2 Registers Involved in Stack Extension
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
Table 3-3 Stack Status Information . . . . . . . . . . . . . . . . . .3-9
Table 3-4 Options for Parallel Moves and Conditional
Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
Table 3-5 Instructions with Program Memory
Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
Table 5-1 Example for Cycle Count with Cache
Enabled Versus Disabled. . . . . . . . . . . . . . . . . .5-2
Table 5-2 Cycle Count Example With and Without
Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7

MOTOROLA Optimizing DSP56300/DSP56600 Applications 1-1
This application
note describes how
to optimize an
application for the
DSP56300 and
DSP56600 new
DSP cores
Section 1
INTRODUCTION
The DSP56300 and DSP56600 are the new high-performance 24-bit
and 16-bit cores in Motorola’s family of Digital Signal Processors.
They are based on the same pipeline structure. This structure is
capable of executing an instruction on every clock cycle. At the
same time these cores maintain a Harvard architecture and
programming model similar to the older 24-bit DSP56000 core.
Code written for the DSP56300 or the DSP56600 may be based on
previously developed code written for the DSP56000, or it may be
new code that was developed initially for these new DSP cores. The
intent of this document is to describe the new and the
DSP56000-based features of the DSP56300 and DSP56600 cores in
order to help the DSP software engineer to fully utilize the
processor resources and generate an optimized application.
The document is a supplement to the detailed DSP56300 and
DSP56600 Family Manuals.
1.1 DSP56300 CORE FAMILY
The DSP56300 core consists of the Expansion Port and DRAM
Controller, Data ALU, Address Generation Unit, Instruction Cache
Controller, Program Control Unit, DMA Controller, PLL Clock
Oscillator, On-Chip Emulation (OnCE™) module, JTAG Test Access
Port (TAP), and the Peripheral and Memory Expansion Busses. The
main features of this high performance CPU include:
• Object code compatibility with the DSP56000 core
• Harvard Architecture with 24-bit instruction width and
24-bit data width
• Fully pipelined 24
× 24-bit parallel Multiplier-Accumulator
(MAC)
• 56-bit parallel barrel shifter
• 16-bit Arithmetic mode of operation
• Highly parallel instruction set

1-2 Optimizing DSP56300/DSP56600 Applications MOTOROLA
Introduction
DSP56600 Core Family
• Position Independent Code (PIC) instruction-set support
• Unique DSP addressing modes
• On-chip memory-expandable hardware stack
• Nested hardware DO loops
• Fast auto-return interrupts
• On-chip instruction cache
• On-chip concurrent six-channel DMA controller
• On-chip Phase Lock Loop (PLL)
• On-Chip Emulation (OnCE) module
• Program address tracing support
• JTAG port compatible with the IEEE 1149.1 Standard
The first members of DSP chips that use the DSP56300 core are the
DSP56301, DSP56302, DSP56303, and DSP56305. The main
differences between these derivatives are the size of the on-chip
memory and the types of on-chip peripherals and hardware
accelerators.
1.2 DSP56600 CORE FAMILY
The DSP56600 core consists of the External Memory Interface port,
Data ALU, Address Generation Unit, Program Control Unit, PLL
Clock Oscillator, On-Chip Emulation module, and the Peripheral
and Memory Expansion Busses. The main differences between the
DSP56300 and the DSP56600 cores are:
• The DSP56600 uses a 16-bit data bus, while the DSP56300
uses a 24-bit data bus.
• The Multiplier-Accumulator in the DSP56600 is 16
× 16 bit
while the DSP56300 is 24
× 24 bit.
• The DSP56600’s barrel shifter is 40 bits wide, while the
DSP56300’s barrel shifter is 56 bits wide.
• The DSP56600 does not include an instruction cache
controller.
• The DSP56600 does not include a six-channel DMA
controller.

Introduction
Enhancements over the DSP56000
MOTOROLA Optimizing DSP56300/DSP56600 Applications 1-3
The first members of DSP chips that use the DSP56600 core are the
DSP56602 and the DSP56603. The main differences between these
derivatives are the size of the on-chip memory and the types of
on-chip peripherals.
1.3 ENHANCEMENTS OVER THE DSP56000
The DSP56300 and the DSP56600 include many architectural
enhancements over the older generation 24-bit DSP family, the
DSP56000. The following tables shortly describe these
enhancements.
1.3.1 Instruction Set Enhancements
Many instructions were added in order to support the target
applications of the new DSP cores:
Table 1-1 New Instructions in DSP56300 and DSP56600
Opcodes Opcodes Exist in
DSP56300? Exist in DSP56600?
MAX Transfer by Signed Value √√
MAXM Transfer by Magnitude √√
INSERT INSERT Bit Field √√
EXTRACT Extract Bit Field √√
EXTRACTU Extract Unsigned Bit Field √√
MERGE Merge Two Half Words √√
CLB Count Leading Bits √√
NORMF Fast Accumulator
Normalize
√√
CMPU Compare Unsigned √√
Multibit
Shifts Arithmetic and Logical Shifts
√√

1-4 Optimizing DSP56300/DSP56600 Applications MOTOROLA
Introduction
Enhancements over the DSP56000
MAC (uu) Unsigned MAC √√
DMAC Double-Precision MAC √√
PLOCK Lock Cache Sector √
PUNLOCK Unlock Cache Sector √
PFLUSH Flush Cache Sectors √
PFLUSHUN Flush Unlocked Cache
Sectors
√
PFREE free all locked sectors √
LRA Load Relative Address √√
BSR / BScc Branch Subroutine
always/conditionally
√√
BRA / Bcc Branch Target
always/conditionally
√√
BSset / BSclr Branch Subroutine on Bit
Set/Clear
√
BRset /
BRclr Branch Target on Bit Set/Clear
√
DO Forever DO-Loop Forever √√
DOR Forever DO-Loop Forever Relative √
BRKcc Break Loop Conditionally √√
TRAPcc TRAP Conditionally √√
IFcc Execute Instruction
Conditionally
√√
VSL Viterbi Shift Left √√
Table 1-1 New Instructions in DSP56300 and DSP56600
Opcodes Opcodes Exist in
DSP56300? Exist in DSP56600?

Introduction
Enhancements over the DSP56000
MOTOROLA Optimizing DSP56300/DSP56600 Applications 1-5
1.3.2 Architectural Enhancements
The programmer’s model of the new DSP cores were also enhanced
by the following:
• An instruction cache controller was added to the DSP56300.
A Burst mode can be used to lower the off-chip traffic if
external DRAMs are used.
• A six-channel DMA controller was added to the DSP56300.
• A true barrel shifter (56-bit in DSP56300 and 40-bit in
DSP56600) was added to support multibit operations.
• The address and offset registers of the DSP56300 (R0–R7,
N0–N7) were extended to 24-bit wide to support larger
memory sizes.
• The DSP56300 has a 16-bit Arithmetic operating mode such
that 16-bit exact algorithms can be implemented without any
overhead.
• The DSP56300 and the DSP56600 have an on-chip Hardware
Stack Extension mechanism that makes the Stack depth
practically unlimited.
• Rounding and Saturation modes were added to the
Arithmetic Unit of the DSP56300 and DSP56600.
• New addressing modes were added to the DSP56300 and
DSP56600:
– Short/Long address displacement
– PC-Relative for Position Independent Code
– Short/Long Immediate operands to Arithmetic and
Logical operations

1-6 Optimizing DSP56300/DSP56600 Applications MOTOROLA
Introduction
Application Note Structure
1.4 APPLICATION NOTE STRUCTURE
This document has three main component parts:
• DSP56300 and DSP56600 features description and use
• Optimizing the code for best performance
• Appendices
1.4.1 DSP56300 and DSP56600 Features
Description and Use
The first five sections in this application note describe all the
architectural and instruction set enhancements in the new DSP
cores and how they can be used to optimize applications.
• Section 1—Introduction
– DSP56300 core family
– DSP56600 core family
– Enhancements over the DSP56000
• Section 2—Data Operations
– How to organize data in memory to use parallel moves
– How to use the barrel shifter in various applications
– The benefit and use of the 16-bit Arithmetic support
– Some examples that show the benefit of few of the new
arithmetic and logical instructions
• Section 3—Program Control
– How to use the on-chip hardware stack
– Benefit and usage of the Stack Extension
– Usage of the conditional arithmetic and logical
instructions
– How to use the PC relative instructions for code
relocation and saving of program words
– Using fast interrupts

Introduction
Application Note Structure
MOTOROLA Optimizing DSP56300/DSP56600 Applications 1-7
• Section 4—Using the DMA
– How to reduce core MIPS by using the DMA
– How to service peripherals using the DMA
– How to use slow, inexpensive memory chips without
loosing performance
– How to handle complex data structures by using the
DMA
• Section 5—Instruction Cache and Other Memory Features
– Basic instruction cache tutorial
– Data organization for efficient sector allocation
– Sector locking for critical loops
– Flushing the cache after task switching.
– Burst mode for DRAMs
– Memory banks between program and data
– Using the bootstrap ROM
1.4.2 Optimizing the Code for Best Performance
The next two sections include general explanation of the various
pipeline stall conditions and how they can be avoided in order to
get faster execution times. In addition, some observations on the
instruction set are included along with recommended usage for
optimization purposes.
• Section 6—Pipeline Interlocks
– Description of the various types of interlocks
– Ways to avoid each type of interlock
– Program flow and control
– Understanding timing of conditional change of flow
– How to reorder code at the end of DO loops
– When to use the repeat instruction
• Section 7—Compact Opcode Use

1-8 Optimizing DSP56300/DSP56600 Applications MOTOROLA
Introduction
Application Note Structure
– Cycle count of an instruction
– Addressing modes
– Word count of an instruction
– Peripheral addressing
1.4.3 Appendixes
There are three appendices providing supplementary information
about application design guidelines:
• Appendix A—Saving Power
• Appendix B—Debug and Test Support
• Appendix C—Using the Profiler

MOTOROLA Optimizing DSP56300/DSP56600 Applications 2-1
This section
discusses
important features
and new additions
to the DSP56000
core Data
Arithmetic Unit
Section 2
DATA OPERATIONS
2.1 USING THE DUAL DATA PATHS
The DSP56300/DSP56600 core can execute a new instruction every
clock cycle. This performance can be used efficiently only if data can
be fed to the core and its results moved out of it at a sufficient rate.
The DSP56300/DSP56600 core’s highly parallel architecture was
designed to allow performing the following operations in parallel:
• Data ALU instruction execution
• Up to two parallel moves of data operands or results to/from
the Data ALU
• Up to two address calculations for the next instruction
• Fetch of next instruction
The two data paths (the X bus and Y bus) connect two data memory
sections (the X memory and the Y memory) with the Data ALU.
This parallelism allows the DSP56300/DSP56600 core to execute
more effectively, for example, executing a FIR tap in one clock cycle:
Data that is moved in parallel
into a register is ready for use in the
next instruction, and does not interfere with the current value of the
operands in execution. In the above example, the values of X0 and
Y0 are updated only after the “MAC” instruction uses its operands.
Similarly, data moved
from a register will hold the data before it was
updated as a result of execution. For example:
mac x0,y0,a a,x:(r0)+
The value of the accumulator A that is moved to the memory is the
value before its update by the “MAC” instruction.
Opcode + operands
Data for next
iteration via the X
data bus +
increment pointer
Data for next
iteration via the Y
data bus +
increment pointer
____________________________________________ ___________________________________ ____________________________________
mac x0,y0,a x:(r0)+,x0 y:(r4)+,y0

2-2 Optimizing DSP56300/DSP56600 Applications MOTOROLA
Data Operations
Using the Dual Data Paths
There are two ways to generate the operand addresses for parallel
moves:
•XY addressing—Two address registers are used
independently, one generating an operand address for the X
memory and the other for the Y memory. The FIR example
above is of this kind. The address registers must be of
different “banks”, meaning that if an address register R0–3 is
used for one data field, an address register R4–7 should be
used for the other data field. No absolute addresses are
allowed in this mode.
•Long addressing—One address register or absolute address
is used to generate the address for both the X memory and
the Y memory. For example:
mac x0,x1,a l:(r0)+,X
The syntax L:(R0)+,X is equivalent to moving X:(R0) to X0 and
Y:(R0) to X1, then incrementing R0. The name “long addressing”
refers to the fact that such addressing enables to access two data
registers as if they were one 48-bit long register.
Not all the DSP56300/DSP56600 instructions support parallel
moves. In general, the instructions that do are a subset of the
arithmetic instructions. The full list of these instructions appears in
Table 2-1.
Table 2-1 Parallel Move Instructions
Instruction Mnemonic Relevant
Opcode variants
Absolute Value ABS
Add Long with Carry ADC
Add ADD Non-immediate
Shift Left and Add Accumulators ADDL
Shift Right and Add Accumulators ADDR
Logical AND AND Non-immediate
Arithmetic Shift Accumulator Left ASL Single bit,
non-immediate

Data Operations
Using the Dual Data Paths
MOTOROLA Optimizing DSP56300/DSP56600 Applications 2-3
Arithmetic Shift Accumulator Right ASR Single bit,
non-immediate
Clear Accumulator CLR
Compare CMP Non-immediate
Compare Magnitude CMPM
Logical Exclusive OR EOR Non-immediate
Logical Shift Left LSR
Logical Shift Right LSR
Multiply and Accumulate MAC Signed operands
Signed Multiply and Accumulate and
Round MACR
Transfer by Signed Value MAX
Transfer by Magnitude MAXM
Signed Multiply MPY
Signed Multiply and Round MPYR
Negate Accumulator NEG
Logical Complement NOT
Logical Inclusive OR OR Non-immediate
Round Accumulator RND
Rotate Left ROL
Rotate Right ROR
Subtract Long with Carry SBC
Subtract SUB Non-immediate
Shift Right and Subtract Accumulators SUBR
Shift Left and Subtract Accumulators SUBL
Table 2-1 Parallel Move Instructions (Continued)
Instruction Mnemonic Relevant
Opcode variants

2-4 Optimizing DSP56300/DSP56600 Applications MOTOROLA
Data Operations
Using the Dual Data Paths
Parallel moves are also restricted in their use of registers as source
and destination to a part of the Data ALU registers. The register
options available for XY Addressing are listed in Table 2-2. Any
register in the X field column can appear with any register in the Y
column, with the obvious exception of updating the same
accumulator from both the X and Y fields.
The register options available for long addressing are listed in
Table 2-3.
Note: Some syntax combinations of the accumulators differ only in
shifting/limiting (if the register is the source) or implicit
register updates (if they are destination). For example,
compare “A10” with “A”. In the “AB” and “BA”
combinations, each accumulator has same behavior as a
regular move, such as:
move a, x:(r0)+.
Transfer Data ALU Register TFR
Test Accumulators TST
Table 2-2 Registers Used in Parallel XY Moves
X Field Y Field Comments
X0 Y0
X1 Y1
AAAs source: undergoes shifting and
limiting
As destination: A2/B2 sign
extended, A0/B0 zero filled
BB
Table 2-1 Parallel Move Instructions (Continued)
Instruction Mnemonic Relevant
Opcode variants

Data Operations
Using the Dual Data Paths
MOTOROLA Optimizing DSP56300/DSP56600 Applications 2-5
Keeping those restrictions in mind, writing a critical data processing
loop efficiently should be done after careful planning of register use
and the data allocations in the memory space according to the
parallelism possible in the calculation at hand. For example, in the
FIR tap calculation given above, the coefficients occupy the X
memory with pointer R0, and the data buffer occupies the Y
memory with pointer R4 (or vice versa). In other cases, the division
may not be so straight forward. For example, in many algorithms
involving complex numbers, the efficient solution uses one memory
space for the real part of the numbers, while the other memory
space is used for the imaginary part. In those examples, there is a
logical separating criterion between the data placed in the X and Y
memories. In many applications, however, variables may be split up
between the X and Y memories based on no other criterion than the
ability to transfer them in parallel to the core at the time they are
called for by the algorithm.
Table 2-3 Registers used in Long Addressing
Assembler
Syntax X Field Y Field
Shifting/
Limitingif
source
Sign
extension
if
destination
Zero fill if
destination
A10 A1 A0 no no no
B10 B1 B0 no no no
XX1X0no no no
YY1Y0no no no
A A1 A0 yes A2 no
B B1 B0 yes B2 no
AB A1 B1 yes A2,B2 A0,B0
BA B1 A1 yes A2,B2 A0,B0