Nuvoton ISD2360 Guide

ISD2360 Design Guide
Publication Release Date:Nov 20, 2014
Revision V1.14
ISD ChipCorder
ISD2360
Design Guide

ISD2360 Design Guide
Publication Release Date:Nov 20, 2014
Revision V1.14
© 2012 by Nuvoton Technology Corporation.
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ISD2360 Design Guide
Release Date: Nov 20, 2014
- iii - Revision v1.14
Table of Contents-
LIST OF TABLES-.......................................................................................................................................VII
1. GENERAL DESCRIPTION.................................................................................................................... 1
OVERVIEW...........................................................................................................................................................1
FEATURES...........................................................................................................................................................1
2. PIN CONFIGURATIONS ....................................................................................................................... 3
2.1 PIN DIAGRAMS........................................................................................................................................3
2.2 PIN DESCRIPTIONS .................................................................................................................................4
3. BLOCK DIAGRAM ................................................................................................................................ 7
4. DEVICE STATUS................................................................................................................................... 8
4.1 DEVICE STATUS REGISTER ....................................................................................................................8
4.2DEVICE INTERRUPT REGISTER...............................................................................................................9
5. DEVICE CONFIGURATION................................................................................................................ 10
5.1 DEVICE ID.............................................................................................................................................10
5.2 CLOCK CONFIGURATION.......................................................................................................................10
5.3 GPIO CONFIGURATION ........................................................................................................................10
5.3.1 GPIO Pin Function Definition....................................................................................................10
5.3.2 Special 3 V Registers ................................................................................................................11
5.3.3 GPIO Pin Structure ....................................................................................................................11
5.4 SIGNAL PATH CONFIGURATION ............................................................................................................12
5.5 DEVICE CHECKSUM ..............................................................................................................................13
5.6 INDIRECT REFERENCE REGISTERS ......................................................................................................14
5.7 GPIO4 CONFIGURATION FOR DIGITAL READ/WRITE ..........................................................................14
5.8 FAST DE-BOUNCE FOR GPIO TRIGGER ..............................................................................................15
5.9 THERMAL SHUTDOWN...........................................................................................................................15
6. OPERATIONAL DESCRIPTION......................................................................................................... 16
6.1OVERVIEW.............................................................................................................................................16
6.2 AUDIO STORAGE...................................................................................................................................16
6.3 SAMPLE RATES.....................................................................................................................................16
6.4 AUDIO COMPRESSION AND DE-COMPRESSION ...................................................................................17
6.5 SYSTEM VOICE MACRO FLOW CHART.................................................................................................17
6.6 GPIO TRIGGER.....................................................................................................................................18
6.6.1 GPIO Trigger Basics..................................................................................................................18
6.6.2 SPI or GPIO Trigger...................................................................................................................19
6.6.2.1 Pulling SSB low automatically claims the SPI interface.................................................................... 19
6.6.2.2 Pulling SSB Low does not affect the triggering capability ................................................................ 20
6.6.2.3 GPIO Trigger Execution is preemptive................................................................................................ 20
6.6.2.4 SPI vs. GPIO Triggering Reliability...................................................................................................... 20
6.6.3 Volume Control via GPIO Trigger............................................................................................21
6.7 MULTI-CHANNEL FEATURE...................................................................................................................21
6.7.1 SPI Multi Channel.......................................................................................................................21
6.7.2Multi Channel GPIO Trigger .....................................................................................................21
6.8 VM JUMP AND CHANNEL COUNTER COMMANDS.................................................................................22
6.8.1 VM Branch Commands .............................................................................................................22
6.8.2 Channel Counter Command.....................................................................................................22
7. MEMORY MANAGEMENT ................................................................................................................. 23
7.1 MEMORY HEADER.................................................................................................................................24

ISD2360 Design Guide
Release Date: Nov 20, 2014
- iv - Revision v1.14
7.1.1 Memory Format .......................................................................................................................... 24
7.1.2 Memory Protection..................................................................................................................... 25
7.2 VOICE PROMPT.....................................................................................................................................26
7.3 VOICE MACRO.......................................................................................................................................26
7.3.1 Voice Macro Commands...........................................................................................................26
7.3.2 System-Reserved Voice Macros.............................................................................................. 28
7.3.3 Sample Project Voice Macros ..................................................................................................28
7.3.3.1 Sample_1: A Simple Trigger-To-Play Project .................................................................................... 28
7.3.3.2 Sample_2: Channel Mixing with Volume Control............................................................................... 30
7.3.3.3 Sample_3: Driving GPIO Using the Channel Counter...................................................................... 32
7.4 USER DATA...........................................................................................................................................34
8. SERIAL PERIPHERAL INTERFACE................................................................................................. 35
8.1 SPI FEATURES......................................................................................................................................35
8.2 SPI COMMANDS....................................................................................................................................37
8.3 SPI COMMAND VS.STATUS..................................................................................................................38
8.4SPI COMMAND DESCRIPTIONS.............................................................................................................39
8.4.1 Audio Play Commands..............................................................................................................39
8.4.1.1 PLAY_VP –Play Voice Prompt............................................................................................................ 39
8.4.1.2 PLAY_VP@Rn –Play Voice Prompt @ Rn ....................................................................................... 40
8.4.1.3 PLAY_VP_LP –Play Voice Prompt Loop........................................................................................... 40
8.4.1.4 PLAY_VP@Rn_LP –Loop Play Voice Prompt Referenced by RnCnt Times............................... 40
8.4.1.5 EXE_VM –Execute Voice Macro.......................................................................................................... 41
8.4.1.6 EXE_VM@Rn –Execute Voice Macro Referenced by Rn............................................................... 41
8.4.1.7 PLAY_SIL –Play Silence...................................................................................................................... 41
8.4.1.8 STOP –Stop the Play Operations....................................................................................................... 42
8.4.1.9 STOP_LP –Stop Loop Play Operations............................................................................................. 42
8.4.1.10 SPI_PCM_READ –SPI Read De-Compressed PCM Data from Memory ................................ 42
8.4.1.11 SPI_SND_DEC –SPI Send Compressed Data for Decoding..................................................... 43
8.4.2 Device Status Commands.........................................................................................................44
8.4.2.1 READ_STATUS –Read Status........................................................................................................... 44
8.4.2.2 READ_INT –Read Interrupt................................................................................................................. 44
8.4.2.3 READ_ID - Read Device ID.................................................................................................................. 45
8.4.3 Digital Commands......................................................................................................................45
8.4.3.1 DIG_READ –Digital Read.................................................................................................................... 45
8.4.3.2 DIG_WRITE –Digital Write................................................................................................................... 46
8.4.3.3 ERASE_MEM –Sector Erase Memory............................................................................................... 46
8.4.3.4 CHIP_ERASE –Erase Entire Memory................................................................................................ 47
8.4.3.5 CHECKSUM –Calculate Hardware Checksum................................................................................. 47
8.4.4 Device Configuration Commands............................................................................................48
8.4.4.1 PWR_UP –Power Up Device .............................................................................................................. 48
8.4.4.2 PWR_DN –Power Down Device......................................................................................................... 48
8.4.4.3 SET_CLK_CFG –Set Clock Configuration Register ........................................................................ 48
8.4.4.4 RD_CLK_CFG –Read Clock Configuration Register....................................................................... 49
8.4.4.5 WR_CFG_REG –Write Configuration Register ................................................................................ 49
8.4.4.6 RD_CFG_REG –Read Configuration Register................................................................................. 49
8.4.4.7 RESET –Reset Device......................................................................................................................... 49
9. REGISTER OPERATIONS.................................................................................................................. 50
10. APPLICATION DIAGRAMS................................................................................................................ 57
10.1 SPI APPLICATION UNDER MCU CONTROL ..........................................................................................57
10.2 GPIO TRIGGER STANDALONE APPLICATION .......................................................................................58
11. ELECTRICAL CHARACTERISTICS.................................................................................................. 59
11.1 OPERATING CONDITIONS......................................................................................................................59
11.2 AC PARAMATERS..................................................................................................................................59
11.2.1 Internal Oscillator........................................................................................................................59

ISD2360 Design Guide
Release Date: Nov 20, 2014
- v - Revision v1.14
11.2.2 Speaker Outputs......................................................................................................................... 59
11.2.3 DC Parameters...........................................................................................................................60
11.2.4 SPI Timing...................................................................................................................................60
12. PACKAGE DIMENSIONS................................................................................................................... 62
13. ORDERING INFORMATION............................................................................................................... 64
14. REVISION HISTORY........................................................................................................................... 65

ISD2360 Design Guide
Release Date: Nov 20, 2014
- vi - Revision v1.14
List of Figures-
Figure 2-1 ISD2360 QFN 32-Lead Package.................................................................................. 3
Figure 2-2 ISD2360 SOP 16-Lead 300 mil Package ..................................................................... 4
Figure 3-1 ISD2360 Block Diagram................................................................................................ 7
Figure 5-1 GPIO Pad Structure.................................................................................................... 11
Figure 5-2 ISD2360 Signal Path................................................................................................... 12
Figure 5-3 PWM Output Thermal Shutdown................................................................................ 15
Figure 6-1 System Reserved Voice Macro Flow Chart................................................................ 18
Figure 6-2 POR Reset Failure from Power Supply Glitches........................................................ 20
Figure 7-1 ISD2360 Memory Organization................................................................................... 23
Figure 7-2 Sample_Project_1 Configuration................................................................................ 29
Figure 7-3 Sample_Project_2 Configuration................................................................................ 31
Figure 7-4 Sample_Project_3 Configuration................................................................................ 33
Figure 8-1 SPI Data Transaction Waveform ................................................................................ 35
Figure 8-2 RDY/BSYB Timing for SPI Write Transactions........................................................... 36
Figure 8-3 RDY/BSYB Ignored for SPI Transactions................................................................... 36
Figure 8-4 SPI Read De-Compressed Data (Playback)............................................................... 43
Figure 8-5 SPI Send Compressed Data to Decode ..................................................................... 44
Figure 10-1 SPI Application under MCU Control ......................................................................... 57
Figure 10-2 GPIO Trigger Standalone Application....................................................................... 58
Figure 11-1 SPI Timing................................................................................................................. 60
Figure 12-1 QFN 32-Lead Package............................................................................................. 62
Figure 12-2 SOP 16-Lead Package............................................................................................. 63

ISD2360 Design Guide
Release Date: Nov 20, 2014
- vii - Revision v1.14
List of Tables-
Table 2-1 32-Lead QFN Pin Descriptions ...................................................................................... 4
Table 2-2 SOP 16-Lead Pin Descriptions ...................................................................................... 6
Table 4-1 Device Status Register Description ............................................................................... 8
Table 4-2 Interrupt Status Register Description............................................................................. 9
Table 5-1 AF1/AF0 Bit Combinations for GPIO Pin Function Mode ............................................ 10
Table 5-2 GPIO Pin Function Modes ........................................................................................... 11
Table 5-3 Checksum Register Result Data Storage.................................................................... 13
Table 5-4 C Code Example Fletcher-32 Checksum Calculation.................................................. 13
Table 5-5 Indirect Reference Registers R0-R7............................................................................ 14
Table 5-6 GPIO Pin and Indirect Reference Register Association .............................................. 14
Table 6-1 Available Sample Rates............................................................................................... 17
Table 7-1 Memory Data Sequence without Reserved User Data................................................ 24
Table 7-2 Memory Header MP_CFG Byte................................................................................... 25
Table 7-3 Memory Protection Scheme......................................................................................... 25
Table 7-4 Voice Macro Commands.............................................................................................. 27
Table 8-1 SPI Commands............................................................................................................ 37
Table 8-2 SPI Commands vs. Status ........................................................................................... 38
Table 9-1 Register Operations ..................................................................................................... 50
Table 11-1 Operating Conditions (Industrial Packaging) ............................................................. 59
Table 11-2 SPI Timing.................................................................................................................. 61

ISD2360 Design Guide
Release Date: Nov 20, 2014
- 1 - Revision v1.14
1. General Description
Overview
The ISD2360 3-channel digital ChipCorder®provides single-chip storage and playback of high
quality audio. The ISD2360 features digital de-compression, comprehensive memory
management, Flash storage, an integrated audio signal path with up to 3 channel concurrent
playback and a Class D speaker driver capable of delivering 1 W of power. The ISD2360
utilizes Flash memory, in 1-Kbyte sectors, to provide non-volatile audio playback for a single-
chip audio playback solution for up to 64 seconds duration (based on 8 kHz/4-bit ADPCM
compression). This eliminates the need for additional EEPROM/Flash devices.
The ISD2360 can be controlled and programmed through a Serial Peripheral Interface (SPI)
or can operate in standalone mode by triggers applied to the device’s six General Purpose
Input/Output (GPIO) pins.
The ISD2360 includes an internal oscillator and requires no external clock sources or
components other than a speaker to deliver quality audio prompts or sound effects to
enhance user interfaces. The ISD2360 also provides higher sampling frequencies, improved
Signal-to-Noise Ratios (SNR), reduced power consumption, fast programming time and
integrated program verification.
Features
Performance Enhancements
o3-channel mixing playback
oGPIO parallel processing: supports dynamic change on GPIO output during
playback
oEMI, EFT, ESD improvements
o1 W power output at 5 V
Duration—64 sec. based on 8 kHz/4-bit ADPCM in 2 Mbits of Flash storage (256 KB)
Audio Management
oStore pre-recorded audio (Voice Prompts) using high quality digital compression
oUse simple index-based commands for playback –no address needed
oExecute pre-programmed macro scripts (Voice Macros) designed to control the
configuration of the device and playback Voice Prompts sequences
Path and Playback Control
oAudio streaming for up to 3 channels can be mixed and played back concurrently
oIndependent counters for each channel enable user micro-management on Voice
Macro execution
oMask Jump for branch execution; based on internal register or external GPIO pin
Control
oSerial Peripheral Interface (SPI) for microprocessor control and programming
oStandalone control when customized Voice Macro scripts are assigned to GPIO
trigger pins
Sample Rates
o8 sampling frequencies available: 4, 5.3, 6.4, 8, 10.67, 12.8, 16 and 32 kHz
oEach Voice Prompt can have its own optimal sample rate
De-Compression Algorithms
oµ-Law: 6, 7 or 8 bits per sample.
oDifferential µ-Law: 6, 7 or 8 bits per sample
oPCM: 8, 10 or 12 bits per sample

ISD2360 Design Guide
Release Date: Nov 20, 2014
- 2 - Revision v1.14
oEnhanced ADPCM: 2, 3, 4 or 5 bits per sample
oVariable bit-rate optimized compression allows best possible compression given a
metric of Signal-to-Noise Ratios (SNR) and background noise levels
Clock Source: Internal oscillator with internal reference, factory trimmed to ±1%
deviation at room temperature
Output
oPulse Wave Modulation (PWM): Class D speaker driver to direct drive an 8 Ω
speaker or buzzer
oDelivers 1W at 5V supply
oDelivers 400mW at 3V supply
I/Os
oSPI interface: MISO, MOSI, SCLK, SSB for commands and digital audio data
o6 General Purpose I/O (GPIO) pins multiplexed with the SPI interface
Flash Storage
o2 Mbits of storage for combined audio/data content
oFast programming time (20 µs/byte)
oErase sector size 1 Kbyte, sector erase time 2 ms
oIntegrated memory checksum calculation for fast verification
oEndurance >100K cycles; retention > 10 years
Operating Voltage: 2.4-5.5 V
Packages, Green:
oQFN 32-Lead
oSOP 16-Lead 300 mil
Temperature Range: Industrial: -40C to 85C

ISD2360 Design Guide
Release Date: Nov 20, 2014
- 3 - Revision v1.14
2. Pin Configurations
2.1 Pin Diagrams
The ISD2360 ChipCorder is available in QFN 32-Lead and SOP 16-Lead 300 mil packages,
as shown in Figure 2-1 and Figure 2-2.
Figure 2-1 ISD2360 QFN 32-Lead Package
Note: The large center exposed pad under the QFN 32-Lead package should be connected
to VSSD on the board to ensure good heat dissipation and mechanical stability.
NC
NC
GPIO0/MOSI
VSSD
NC
NC
NC
NC
NC
NC
GPIO4/RDY/BSYB
GPIO3/INTB
NC
NC
NC
NC
NC
VCC_PWM
SPK+
VSS_PWM VSS_PWM
SPK-
VCC_PWM
NC
NC
SSB
GPI1/SCLK
GPIO2/MISO
NC
GPIO5
VCCD
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
ISD2360
QFN32
NC
NC
GPIO0/MOSI
VSSD
NC
NC
NC
NC
NC
NC
GPIO4/RDY/BSYB
GPIO3/INTB
NC
NC
NC
NC
NC
VCC_PWM
SPK+
VSS_PWM VSS_PWM
SPK-
VCC_PWM
NC
NC
SSB
GPI1/SCLK
GPIO2/MISO
NC
GPIO5
VCCD
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
ISD2360
QFN32

ISD2360 Design Guide
Release Date: Nov 20, 2014
- 4 - Revision v1.14
16
15
14
13
12
11
10
9
GPIO0/MOSI
VSSD
GPIO2/MISO
GPI1/SCLK
SSB
VCC_PWM
SPK+
VSS_PWM
GPIO4/RDY/BSYB
GPIO3/INTB
NC
GPIO5
VCCD
VCC_PWM
SPK-
VSS_PWM
ISD2360
SOP16
1
2
3
4
5
6
7
8
Figure 2-2 ISD2360 SOP 16-Lead 300 mil Package
2.2 Pin Descriptions
The pin descriptions for the ISD2360 in QFN 32-Lead package and in SOP 16-Lead 300 mil
package are provided in Table 2-1 and Table 2-2, respectively.
Table 2-1 32-Lead QFN Pin Descriptions
Pin
Pin Name
I/O
Function
1
NC
This pin should remain Not Connected.
2
NC
This pin should remain Not Connected.
3
GPIO0/MOSI
I
Master-Out-Slave-In. Serial input to the ISD2360 from the host.
Can be configured as a General Purpose I/O pin.
4
VSSD
Digital Ground.
5
NC
This pin should remain Not Connected.
6
NC
This pin should remain Not Connected.
7
NC
This pin should remain Not Connected.
8
NC
This pin should remain Not Connected
9
NC
This pin should remain Not Connected.
10
VCC_PWM
I
Digital Power for the Pulse Wave Modulator (PWM) Driver.
11
SPK+
O
PWM driver positive output.
The SPK+ output and the SPK- pin provide a differential output
to drive an 8 Ωspeaker or buzzer. During power down, this
pin is in tri-state.
12
VSS_PWM
I
Digital Ground for the PWM Driver.
13
VSS_PWM
I
Digital Ground for the PWM Driver.
14
SPK-
O
PWM driver negative output.
The SPK- output and the SPK+ pin provide a differential output
to drive an 8 Ωspeaker or buzzer. During power down, this
pin is tri-state.
15
VCC_PWM
I
Digital Power for the PWM Driver.

ISD2360 Design Guide
Release Date: Nov 20, 2014
- 5 - Revision v1.14
Pin
Pin Name
I/O
Function
16
NC
This pin should remain Not Connected
17
NC
This pin should remain Not Connected
18
NC
This pin should remain Not Connected
19
NC
This pin should remain Not Connected
20
NC
This pin should remain Not Connected
21
GPIO3/INTB
O
Active low interrupt request pin.
This pin is an open-drain output.
Can be configured as a General Purpose I/O pin.
22
GPIO4/RDY/
BSYB
O
Output pin reports the status of data transfer on the SPI
interface. ―High‖ indicates the ISD2360 is ready to accept new
SPI commands or data. Can be configured as a General
Purpose I/O pin.
23
NC
This pin should remain Not Connected
24
NC
This pin should remain Not Connected
25
NC
This pin should remain Not Connected
26
VCCD
I
Digital Power.
27
GPIO5
I/O
General Purpose I/O pin
28
NC
This pin should remain Not Connected
29
GPIO2/MISO
O
Master-In-Slave-Out. Serial output from the ISD2360 to the
host. This pin is in tri-state when SSB=1.
Can be configured as a general purpose I/O pin.
30
GPI1/SCLK
I
Serial Clock input to the ISD2360 from the host.
Can be configured as a General Purpose input pin.
31
SSB
I
Slave Select input to the ISD2360 from the host.
When SSB is low, the device is selected and responds to
commands on the SPI interface. When asserted, GPIO0/1/2
automatically configure to MOSI/SCLK and MISO respectively.
SSB has an internal pull-up to VCCD.
32
NC
This pin should remain Not Connected.
-
center
exposed pad
The center pad under the QFN 32-Lead package is connected
to VSSD internally.

ISD2360 Design Guide
Release Date: Nov 20, 2014
- 6 - Revision v1.14
Table 2-2 SOP 16-Lead Pin Descriptions
Pin
Pin Name
I/O
Function
1
GPIO2/MISO
O
Master-In-Slave-Out. Serial output from the ISD2360 to the
host. This pin is in tri-state when SSB=1.
Can be configured as a general purpose I/O pin.
2
GPI1/SCLK
I
Serial Clock input to the ISD2360 from the host.
Can be configured as a General Purpose input pin.
3
SSB
I
Slave Select input to the ISD2360 from the host.
When SSB is low, the device is selected and responds to
commands on the SPI interface. When asserted, GPIO0/1/2
automatically configure to MOSI/SCLK and MISO respectively.
SSB has an internal pull-up to VCCD.
4
GPIO0/MOSI
I
Master-Out-Slave-In. Serial input to the ISD2360 from the host.
Can be configured as a General Purpose I/O pin.
5
VSSD
Digital Ground.
6
VCC_PWM
I
Digital Power for the Pulse Wave Modulator (PWM) Driver.
7
SPK+
O
PWM driver positive output.
The SPK+ output and the SPK- pin provide a differential output
to drive an 8 Ωspeaker or buzzer. During power down, this
pin is in tri-state.
8
VSS_PWM
I
Digital Ground for the PWM Driver.
9
VSS_PWM
I
Digital Ground for the PWM Driver.
10
SPK-
O
PWM driver negative output.
The SPK- output and the SPK+ pin provide a differential output
to drive an 8 Ωspeaker or buzzer. During power down, this
pin is tri-state.
11
VCC_PWM
I
Digital Power for the Pulse Wave Modulator (PWM) Driver.
12
NC
This pin should remain Not Connected
13
GPIO3/INTB
O
Active low interrupt request pin.
This pin is an open-drain output.
Can be configured as a General Purpose I/O pin.
14
GPIO4/RDY/
BSYB
O
Output pin reports the status of data transfer on the SPI
interface. ―High‖ indicates the ISD2360 is ready to accept new
SPI commands or data. Can be configured as a General
Purpose I/O pin.
15
VCCD
I
Digital Power.
16
GPIO5
I/O
General Purpose I/O pin

ISD2360 Design Guide
Release Date: Nov 20, 2014
- 7 - Revision v1.14
3. Block Diagram
The major functional blocks of the ISD2360 ChipCorder, as shown in Figure 3-1 include:
SPI and GPIO Interfaces
Memory Management and Command Interpreters
De-Compression
Digital Signal Path Filtering, Mixing, Sampling and Volume Control
PWM Control
Internal Flash Memory
Power Conditioning
Flash Memory Controller
Digital Signal Path
Digital Filters
Digital Mixing
Resampling
Volume Control
Flash Memory Controller
De-Compression
De-Compression
De-Compression
Memory management and
Command Interpreter Ch3
Memory management and
Command Interpreter Ch1
Memory management and
Command Interpreter Ch2
PWM
Control
SP+
SP-
Internal Flash
Memory
Power
Conditioning
VCCD
VSSD
VCCDPWM
VSSDPWM
GPI1/SCLK
GPIO2/MISO
GPIO3/INTB
GPIO0/MOSI
GPIO5
SSB
GPIO4/RDY/BSYB
SPI Interface
GPIO
Interface
Figure 3-1 ISD2360 Block Diagram
The ISD2360 can be controlled and programmed through a Serial Peripheral Interface (SPI)
or can operate in standalone mode by triggers applied to the device’s six General Purpose
Input/Output (GPIO) pins. Voice Prompt and Voice Macro commands facilitate fast
programming.
The ISD2360 ChipCorder provides 2 Mbits of Flash storage for combined audio/data content.
Memory is available in 1-Kbyte sectors, eliminating the need for additional serial
EEPROM/Flash devices. The Flash memory provides non-volatile audio playback for a single-
chip audio playback solution for up to 64 seconds duration (based on 8 kHz/4-bit ADPCM
compression).

ISD2360 Design Guide
Release Date: Nov 20, 2014
- 8 - Revision v1.14
4. Device Status
The ISD2360 status can be acquired by querying the Device Status Register and the Interrupt
Status Register. After receiving a READ_STATUS command, the ISD2360 ChipCorder
continues to send back the device status byte and the interrupt status byte in turn, as long as
the master provides the clock.
During an SPI transaction, the ISD2360 continually sends back its current status via MISO.
When executing an SPI command or a Voice Macro command (refer to section 7.3 for details
of Voice Macro) script, the ISD2360 continually updates its device status register bits. Upon
completion of an SPI command or a Voice Macro command, the ISD2360 updates its
interrupt status register bits.
4.1 Device Status Register
During an SPI transaction, for all commands except digital reading commands, the device
status byte is sent back from device via MISO for every byte of data sent to the ISD2360.The
details of the device status bits are shown in Table 4-1.
Table 4-1 Device Status Register Description
Status Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PD
DBUF_RDY
INT
-
CH2_BSY
CH1_BSY
CH0_BSY
DIG_BSY
The individual bits of the Device Status Register refer to the following conditions:
PD If this bit is set, the device is powered down. The DBUF_RDY bit will be low.
When PD is high, only the READ_STATUS, READ_INT and PWR_UP
commands are accepted. If any other command is sent, it is ignored and no
interrupt for an error is generated.
DBUF_RDY In Power Down status, this bit is low indicating the device can only accept a
PWR_UP (power up) command. When PD is low, this bit reflects the state of
the RDY/BSY pin.
INT Indicates that an interrupt has been generated. The interrupt is cleared by the
READ_INT command. The Interrupt type can be determined by the bits of the
Interrupt Status Byte.
CHx_BSY When high, this bit indicates that channel [x] is in one of the following
conditions:
- Processing a Voice Macro
- Processing a Voice Prompt
- Channel is waiting to process existing command in command buffer
- GPIO command is pending
Once set, Channel [x] will not respond to a new audio command until it returns
low.
DIG_BUSY When high, this bit indicates that the Flash controller is still processing a digital
memory access. For device erase commands, such as ERASE_MEM and
CHIP_ERASE, the user can poll this bit to determine if the erasure is complete.

ISD2360 Design Guide
Release Date: Nov 20, 2014
- 9 - Revision v1.14
4.2 Device Interrupt Register
Whenever the ISD2360 generates an interrupt, the Interrupt Status Register holds flags that
indicate the type of interrupt that was generated. The interrupt bits are shown in Table 4-2.
These flags will remain set until a READ_INT command clears them and the hardware
interrupt pin (INTB) is set. Some interrupts require further servicing to remove the condition
generating the interrupt; for instance, a FIFO full or empty interrupts. If the condition is not
serviced before a READ_INT, the device will immediately generate a new interrupt. To
respond to an interrupt, use the following procedure:
READ_STATUS to determine which interrupt flags are set.
Service the interrupt appropriately.
READ_INT to determine if a new interrupt has occurred during the service routines.
If a new interrupt is detected, go to step 2. READ_INT will clear the interrupt status.
Table 4-2 Interrupt Status Register Description
Interrupt Status Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TALARM_INT
MPT_ERR
WR_FIN
CMD_ERR
OVF_ERR
CH2_FIN
CH1_FIN
CH0_FIN
The individual bits of the Interrupt Status Register refer to the following conditions:
INT An interrupt has been generated. The interrupt is cleared by the READ_INT
command.
TALARM_INT Indicates that a temperature alarm has been set.
MPT_ERR Indicates a memory protection error. Digital access is attempted for protected
memory.
WR_FIN Indicates a digital write command has finished writing to the Flash memory.
CMD_ERR An invalid command was sent to the device. The invalid command will be
ignored because the command buffer was full, a Voice Macro has been
active, or the device was not ready to respond to an erase command.
OVF_ERR This error is generated if the host illegally tries to read or write data while the
RDY/BSYB pin is low. It is also generated if a digital read or write attempts to
read or write past the end of memory.
CHx_FIN This bit indicates an interrupt was generated because a command finished
executing on Channel X. A CHx_FIN interrupt will be generated each time a
Voice Macro or Voice Prompt play finishes.

ISD2360 Design Guide
Release Date: Nov 20, 2014
- 10 - Revision v1.14
5. Device Configuration
The ISD2360 is configured by writing to a set of configuration registers. This can be
accomplished either by sending an SPI command, such as WR_CFG_REG, or by executing
Voice Macros that contain configuration commands.
All configuration registers are reset to their default values when there is a reset condition.
When the ISD2360 is in Power Down Mode, a group of 3 V registers will retain their values
while all other registers lose their content. Note the difference between Power Down and
Power Off: Power Down means the device is entering the standby state with the PD bit set;
Power Off means the device no longer has power
Refer to Section 9 REGISTER OPERATIONS for more detailed register information.
5.1 Device ID
The ISD2360 responds to an SPI READ_ID command by sending out its 4-byte identification
data through the MISO line. Within these 4 bytes, the first byte is the ISD digital ChipCorder
family ID which is 0x05 for ISD2360. The following three bytes are a JEDEC compliant code
indicating the memory type; they are manufacturer ID, memory type ID and memory size byte
with values of 0xEF, 0x20 and 0x60 respectively, for an ISD2360 device.
5.2 Clock Configuration
The ISD2360 has an internal oscillator trimmed at manufacturing that requires no external
components to operate. This oscillator provides an internal clock source that operates the
ISD2360 at a maximum audio sample rate Fsmax of 32 kHz. The ISD2360 user should always
use the clock from the internal oscillator with an internal reference that is the device default
setting. By default, the ISD2360 device sets the clock register value as 0x00, which uses the
internal oscillator with an internal reference. The user should not change the clock source.
5.3 GPIO Configuration
5.3.1 GPIO Pin Function Definition
The ISD2360 includes 6 GPIO pins. Each pin can be individually configured as an I/O pin with
internal pull up/down capability, as an alternate function pin, or as a triggering pin. More
specifically, the functional configuration of each GPIO pin may be one of the following four
choices: an I/O pin, an alternate function pin, a falling-edge-triggering pin or a rising-and-
falling-edge-triggering pin. Alternate function control registers, AF1 (0x1E) and AF0 (0x1F),
define the specific function mode of each pin. The function mode of a GPIO pin is defined by
AF1 bit0 and AF0 bit0, shown in Table 5-1.The configuration choices for each mode are
identified in Table 5-2. The upper two bits of the AF1 and AF0 registers are don’t care bits.
Table 5-1 AF1/AF0 Bit Combinations for GPIO Pin Function Mode
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Alternate
Function
Control 1
(0x1E)
-
-
GPIO5
Function
Mode
GPIO4
Function
Mode
GPIO3
Function
Mode
GPIO2
Function
Mode
GPI1
Function
Mode
GPIO0
Function
Mode
Alternate
Function
Control 0
(0x1F)
-
-

ISD2360 Design Guide
Release Date: Nov 20, 2014
- 11 - Revision v1.14
Table 5-2 GPIO Pin Function Modes
AF1 Bit
AF0 Bit
Configuration
0
0
IO pin
0
1
Alternate Function
1
0
Falling-edge Trigger
1
1
Rising-and-falling edge Trigger
Notes: GPIO1 is permanently low to guarantee SPI operation. Do not use as an output.
GPIO5 does not have an alternate function.
5.3.2 Special 3 V Registers
The ISD2360 device contains a group of special registers that can keep their value during
power down. This special group includes registers in the range of 0x14-0x16 and 0x19-0x2F,
and they are powered by an internal regulated 3V power supply.
During power down with 1µA typical standby current, the GPIO triggering configuration in
those 3V registers is still in effect; therefore, the ISD2360 can continue detecting a GPIO
trigger during power down.
5.3.3 GPIO Pin Structure
Once a GPIO pin is configured as an I/O pin, additional configuration of this I/O pin can be
done by configuring the Output Data Control Register(0x19), Output Enable Control Register
(0x1A), Pull Enable Control Register(0x1B), Input Data Control Register(0x1C) and Pull
Select Control Register(0x1D). When the GPIO is selected for its alternate function, the
DOUT and OE connections to the pin are driven by sources other than the DOUT and OE
registers. The structure of the GPIO pads is shown in Figure 5-1.
Logic
GPIO
Pin
PS
OE
PE
DIN
DOUT
Figure 5-1 GPIO Pad Structure
Regardless of the configuration of GPIO pins 0,1 and 2, these pins turn into the SPI interface

ISD2360 Design Guide
Release Date: Nov 20, 2014
- 12 - Revision v1.14
whenever the SSB pin goes low and revert back to their former configurations when the SSB
pin goes back to high. On the contrary, GPIO pins 3, 4 and 5 do not automatically change
their configurations when the SSB pin goes low. Users must especially pay attention to the
GPIO4 (RDY/BSYB) as RDY/BSYB pin is required when performing a digital-read or digital-
write. This requires manual configuration of GPIO4 to the RDY/BSYB function before the
digital operation is required. GPI03 can be configured as an INTB pin so the user can monitor
this pin for task completion.
Transitions on the GPIO pins can generate a GPIO_INT interrupt. At the moment when the
ISD2360 goes into a power down state, the status of the GPIO pins are latched. If the GPIO
pin is configured as a triggering pin (interrupt enabled) and toggling on the pin is the valid
triggering type indicated by AF1 and AF0, then when the toggling happens the ISD2360
device will execute a wake-up event.
5.4 Signal Path Configuration
The signal path involves filtering, sample rate conversion, volume control and decompression.
A block diagram of the signal path is shown in Figure 5-2.The two PWM driver output pins
SPK-and SPK+ provide a differential output to drive an 8 Ωspeaker or buzzer. Note that
during power down, these pins are in tri-state.
Pre-compressed audio signals transfer from memory or the SPI interface through the de-
compressor block to the PWM driver or SPI out. The audio level is adjustable via VOLC
before going out to the PWM driver path. As shown in Figure 5-2, the possible path
combinations are:
MEMORY → DECOMPRESS → SPKR (Playback to Speaker)
MEMORY → DECOMPRESS → SPI_OUT (SPI Playback)
SPI_IN → DECOMPRESS → SPKR (SPI Decode to Speaker)
To configure a signal path, such as a playback path from memory to the PWM output, the
user should enable decompression and PWM (write 0x44 to register 0x02). Later, audio can
be played through the PWM output by issuing a PLAY_VP command.
Figure 5-2 ISD2360 Signal Path

ISD2360 Design Guide
Release Date: Nov 20, 2014
- 13 - Revision v1.14
5.5 Device Checksum
The ISD2360 is able to calculate the hardware checksum from the beginning of memory to a
specified end address. To start a checksum calculation, the user should first reset the circuit
by writing one followed by a zero, to the RST_CHECKSUM bit in Checksum Reset Register,
and then issue the SPI CHECKSUM command to initiate the calculation. The calculation is
based on the Fletcher-32 algorithm, and the calculated checksum is stored in read-only
Checksum Register 0x10-0x13, with the order of CHK_SUM1[7:0], CHK_SUM1[15:8],
CHK_SUM2[7:0] and CHK_SUM2[15:8] respectively, as shown in Table 5-3.
Table 5-3 Checksum Register Result Data Storage
Address
Access Mode
Value At Reset
Nominal Value
0x10-0x13
R
0x0000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x10
CHK_SUM1[7:0]
0x11
CHK_SUM1[15:8]
0x12
CHK_SUM2[7:0]
0x13
CHK_SUM2[15:8]
Note that the hardware Fletcher-32 algorithm calculation starts from the specified end address
and continues backwards until the data address reaches 0. Therefore, the software checksum
calculation should follow the same sequence fetching data. An example of the ISD2360
Fletcher-32 calculation routine is shown in Table 5-4:
Table 5-4 C Code Example Fletcher-32 Checksum Calculation
unsigned int fletcher32_RevrseCalculate(unsigned char *data, size_tlen)
{
int temp;
unsigned int sum1 = 0xffff, sum2 = 0xffff;
while (len) {
unsignedtlen = len> 360 ? 360 : len;
len -= tlen;
do {
sum1 += *data;
data--;
sum2 += sum1;
} while (--tlen);
sum1 = (sum1 & 0xffff) + (sum1 >> 16);
sum2 = (sum2 & 0xffff) + (sum2 >> 16);
}
// Second reduction step to reduce sums to 16 bits
sum1 = (sum1 & 0xffff) + (sum1 >> 16);
sum2 = (sum2 & 0xffff) + (sum2 >> 16);
return sum2 << 16 | sum1;
}