NXP Semiconductors freescale MPC837xE-RDS User manual

Document Number: MPC837xERDSUG
Rev. 1.0
12/2008
Preliminary, Subject to Change without Notice
MPC837xE-RDS
Reference Design Platform User’s Guide

Document Number: MPC837xERDSUG
Rev. 1.0
12/2008
Preliminary, Subject to Change without Notice
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MPC837xE-RDS, Rev. 1.0
Freescale Semiconductor 3
Preliminary, Subject to Change without Notice
Contents
About This Book
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapters
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 MPC837xE-RDS Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Board-Level Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.1 Reset and Reset Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.3 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.4 DDR2 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.5 Local Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.6 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.7 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.8 SATA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.9 PCI Express Interface (PCI-E & Mini PCI-E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.10 10/100/1000 BaseT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.11 RS-232 Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.12 USB 2.0 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.13 PCI Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1.14 COP/JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 MPC837xE-RDS Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.1 COP Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.2 RS-232C Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.3 Serial ATA (SATA) Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.4 Mini PCI Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.5 Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4.1 Power-on LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4.2 RDS Programmable LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4.3 Ethernet LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5 MPC837xE-RDS Board Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.1 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.2 PCI Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

MPC837xE-RDS, Rev. 1.0
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2.5.3 Reset Configuration Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.5.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.5.5 Chip-Select Assignments and Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.6 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.7 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3 Board Bootup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1 Board Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2 External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4 MPC837xE-RDS Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1 Application Features for MPC837xE-RDS reference software . . . . . . . . . . . . . . . . . . . . . . 34
4.2 Application Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5 Unit Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.1 Assembling the Enclosure and Board Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2 Attaching a Wi-Fi Card to the Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3 Attaching a SATA hard disk to the Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

MPC837xE-RDS, Rev. 1.0
Freescale Semiconductor 5
Preliminary, Subject to Change without Notice
About This Book
This document presents system architecture, board-level functions, external connections, and software
features for the MPC837xE-RDS board. It provides guidance of how to operate this product, making it
easy for the user to connect with the outside world. The front part of this book focuses primarily on the
board and functions. The latter part of the book focuses on the mechanical aspects.
Audience
Users who want to become familiar with the MPC837xE-RDS board, its characteristics, and how to
program the device.
Organization
Chapter 1, Introduction,describes the features and block diagram for the MPC837xE-RDS board.
Chapter 2, MPC837xE-RDS Board,describes the board in terms of its hardware: board-level functions,
connectors, configurations, and board mechanical data.
Chapter 3, Board Bootup,describes the board settings and physical connections needed to boot the
MPC837xE-RDS board.
Chapter 4, MPC837xE-RDS Software,describes the main software features for MPC837xE-RDS board.
Definitions, Acronyms, and Abbreviations
The following list defines the acronyms and abbreviations used in this document.
NAS Network-Attached Storage
RAID Redundant Array of Inexpensive Disks
CPU Central Processing Unit
PoE Power over Ethernet
DDR2 SDRAM Double-Data-Rate Two Synchronous Dynamic Random Access Memory
NOR Flash Nor Gate Flash
eTSEC Enhanced Three-Speed Ethernet Controller
RGMII Reduced Gigabit Media Independent Interface
WAN Wide Area Network
LAN Local Area Network
USB Universal Serial Bus
ULPI USB Low-Pin Count Interface
SATA Serial Advanced Technology Attachment (computer bus)
PCI Peripheral Component Interconnect (computer bus)
PCI-E Peripheral Component Interconnect Express (computer bus)
SDHC Secure Digital High Capacity (SD 2.0 memory card)

MPC837xE-RDS, Rev. 1.0
6Freescale Semiconductor
Preliminary, Subject to Change without Notice
I2C Inter-Integrated Circuit (computer bus)
EEPROM Electrically Erasable Programmable Read-Only Memory
JTAG Joint Test Action Group
DHCP Dynamic Host Configuration Protocol
DNS Domain Name System
VLAN Virtual Local Area Networks
NAT Network Address Translation
PAT Port Address Translation
RIP Routing Information Protocol
VRRP Virtual Router Redundancy Protocol
PPPoE Point-to-Point Protocol over Ethernet
IGMP Internet Group Management Protocol
UPnP Universal Plug and Play (computer protocol)
SNMP Simple Network Management Protocol
QoS Quality of Service
IPsec Internet Protocol Security
PPTP Point-to-Point Tunneling Protocol
L2TP Layer 2 Tunneling Protocol
References
The following sources were referenced to produce this book:
•MPC8379E PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual
(MPC8379ERM)
•MPC8379E PowerQUICC II Pro Integrated Host Processor Hardware Specifications
(MPC8379EEC
•Hardware and Layout Design Considerations for DDR Memory Interfaces (AN2582)

Introduction
MPC837xE-RDS, Rev. 1.0
Freescale Semiconductor 7
Preliminary, Subject to Change without Notice
1Introduction
This section presents the features and block diagram for the MPC837xE-RDS board.
1.1 Overview
The MPC837xE-RDS is a reference design based on the MPC8377E PowerQUICCTMII Pro processor. It
supports applications of Wi-Fi Router, DMS (Digital Media Server), NAS with RAID, or Office in BOX,
etc. The documentation for manufacturing the MPC837xE-RDS—including schematic, Gerber files,
reference software, Bill Of Material (BOM)—is on the product CD. With the documentation, original
equipment manufacturers (OEMs) and original design manufacturers (ODMs) can accelerate the
development process and speed time-to-market for their real product.
1.2 Features
This section presents the features, specification, and block diagram of the MPC837xE-RDS board. The
features are as follows:
•CPU
— Freescale MPC8377E @ 667 MHz
•Power
— PoE power solution based on LM5072 up to 30 W output, designed as one daughter
module board
— 48 V DC input used as the alternative power source when PoE is not available
• Memory subsystem
— On-board 512-MByte DDR2 unbuffered SDRAM
— 64-MByte NOR Flash
• Interfaces
— 10/100/1000 BaseT Ethernet ports
– eTSEC1
– RGMII interface: WAN, 1 x 10/100/1000 BaseT with RJ-45 interface, using
RealtekTM RTL8211B single port 10/100/1000 BaseT PHY. This port
supports PoE feature
– eTSEC 2
– RGMII interface: LAN, 1 x 10/100/1000 BaseT with RJ-45 interface, using
RealtekTM RTL8211B single port 10/100/1000 BaseT PHY
— USB 2.0 Host
– ULPI interface: 1 x USB 2.0 Type A Receptacle interface, using SMSCTM
USB3300 Hi-Speed USB PHY
— Serial ATA Controller

MPC837xE-RDS, Rev. 1.0
8Freescale Semiconductor
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Introduction
– Two standard External SATA connectors
— PCI: 32-bit PCI interface up to 66 Mhz
– 2x 32-bit 3.3 V mini PCI slots
— PCI Express
– Two mini PCI Express Connectors, or
– One mini PCI Express connector and one PCI Express x1 connector
—SDHC
– One SDHC Card Connector
—I
2C
–I
2C connected to ST M24256 Serial EEPROM
— Board Connectors
– One DC power jack
– One internal 2 x 5 RS-232 connector
– JTAG / COP for debugging
— Form factor
– Mini ITX form factor (170 mm x 170 mm, or 6693 mils x 6693 mils)
• 6-layer PCB (4 layers signals and separate power and ground layers)
• Certification
—CE/FCC
• Lead-Free (RoHS)

MPC837xE-RDS Board
MPC837xE-RDS, Rev. 1.0
Freescale Semiconductor 9
Preliminary, Subject to Change without Notice
Figure 1 shows the MPC837xE-RDS board block diagram.
Figure 1. MPC837xE-RDS Board Block Diagram
2 MPC837xE-RDS Board
This section presents the board-level functions, specifications, and mechanical data for the
MPC837xE-RDS board.
e 300 Core
32 KB
D-Cache
DUART
Dual I2C
Timers
GPIO, SPI
Interrupt
Controller
Security DDR
Controller Local Bus
USB
Hi-Speed
Host Device
PHY
ULPI RGMII RGMII
RTL8211
Nor Flash
(x 16)
PCI
DDR2 (x64)
I2C1
PHY
UART1
DDR2
MPC8377E
PCI-E
SATAII
eSATA
con
PCI
SD
miniPCI
Socket
miniPCI
Socket
SD
Card
Clock Gen
PCI- E 1X
JTAG/COP
RTL8211 PHY PHY
EEPROM
miniPCI-E
Socket
miniPCI-E
Socket
USB Type A
LM5072
48V PoE 48V AC/DC
1.8 1.5 1.0
5V 3.3V
PoE
Card
32 KB
I-Cache
10/100/1000
Ethernet
eTSEC1
10/100/1000
Ethernet
eTSEC2

MPC837xE-RDS, Rev. 1.0
10 Freescale Semiconductor
Preliminary, Subject to Change without Notice
MPC837xE-RDS Board
2.1 Board-Level Functions
The board-level functions discussed in this section are reset, interrupts, clock distribution, and interface
specification.
2.1.1 Reset and Reset Configurations
The MPC837xE-RDS reset module generates a single reset to reset the MPC837xE and other peripherals
on the board. The reset unit provides power-on reset, hard reset, and soft reset signals in compliance with
the MPC837xE hardware specification. Figure 2 shows the reset circuitry.
Figure 2. Reset Circuitry of the MPC837xE
• The COP/JTAG port or the MPC837xE generates the signal for hard reset.
• The Maxim MAX6829 device generates the power-on reset. When MR is de-asserted and 3.3 V is
ready, the MAX6829 internal timeout guarantees a minimum reset active time of 140 ms before
PORESET is de-asserted. This circuitry guarantees a 140 ms PORESET pulse width after 3.3 V
reaches the right voltage level, and this meets the specification of the PORESET input of
MPC837xE.
• The COP/JTAG port reset provides convenient hard-reset capability for a COP/JTAG controller.
The RESET line is available at the COP/JTAG port connector. The COP/JTAG controller can
directly generate the hard-reset signal by asserting this line low.
• The pushbutton reset interfaces the MR signal with a debounce capability to produce a manual
master reset of the processor.
MAX6829
3.3 V
Push Button
HRESET from COP
SRESET from COP
TRST from COP
SRESET to MPC837xE
PORESET to MPC837xE
FLASH
10/100/1000 PHY
MPC837xE
TRST to MPC837xE
GND
1.0 V
MR
Watchdog Input from MPC837xE
PCI-E & Mini PCI-E

MPC837xE-RDS Board
MPC837xE-RDS, Rev. 1.0
Freescale Semiconductor 11
Preliminary, Subject to Change without Notice
• The COP/JTAG port also generates the soft reset for the system. Assertion of SRESET causes the
MPC837xE to abort all current internal and external transactions and set most registers to their
default values.
2.1.2 External Interrupts
Figure 3 shows the external interrupt circuitry to the MPC837xE.
Figure 3. MPC837xE Interrupt Circuitry
The following items describe the interrupt signals shown in Figure 3:
• PHY interrupt (TSEC1_IRQ, TSEC2_IRQ). Two RTL8211B GBE PHY interrupts are connected
to IRQ1 and IRQ2 of the MPC837xE. The system software can detect the status of the Ethernet
link and the PHY internal status.
• SD Card Write Protect interrupt (SD_WP). The SD card socket has a mechanical pin that can
indicate whether the SD card inserted is write-protected or not. It is connected to IRQ4 of the
MPC837xE.
• PCI interrupt (PCI_INTA, PCI_INTB). Two mini PCI slots INTA and INTB drive IRQ5 and IRQ6
of the MPC837xE, respectively
TSEC1_IRQ
SD_WP
PCI_INTA
PCI_INTB
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
MPC837xE
External Logic
IRQ0
TSEC2_IRQ

MPC837xE-RDS, Rev. 1.0
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MPC837xE-RDS Board
2.1.3 Clock Distribution
Figure 4 and Table 1 show the clock distribution on the MPC837xE-RDS board.
Figure 4. MPC837xE-RDS Clock Distribution Diagram
MPC837xE
Local Bus CLK
DDR2 SDRAM
LCLKx
MCKx
MCKx
200 MHz
50 MHz to 133 MHz
eTSEC
local bus
DLL
DDR
DLL
PCI
DIV
66.666 MHz
OSC
CLKIN
33/66 MHz
33/66 MHz
Mini PCI Slot
Mini PCI Slot
OCCR
2
PCI_SYNC_OUT
PCI_SYNC_IN
System
PLL
CFG_CLKIN_DIV
USB3300
GND GND
24 MHz
Crystal
25 MHz
OSC
RTL8211B
RTL8211B
M66EN
CLK (DDR400)
125 MHz
25 MHz
OSC
PI6C557-03
PI6C557-03
SD_REF_CLKx
SD_REF_CLKx
PCIE_CLKx
PCIE_CLKx
100 MHz
SerDes Interface
100 MHz
Mini PCI-e or
PCI-e x1 Interface

MPC837xE-RDS Board
MPC837xE-RDS, Rev. 1.0
Freescale Semiconductor 13
Preliminary, Subject to Change without Notice
2.1.4 DDR2 SDRAM Controller
MPC837xE uses DDR2 SDRAM as the system memory. The DDR2 interface uses the SSTL2
driver/receiver and 1.8 V power. A Vref 1.8V/2 is needed for all SSTL2 receivers in the DDR2 interface.
For details on DDR timing design and termination, refer to the Freescale application note entitled
Hardware and Layout Design Considerations for DDR Memory Interfaces (AN2582). Figure 5 shows the
DDR SDRAM controller connection.
Table 1. Clock Distribution
Clock Frequency Module Generated by Description
66.666 MHz MPC837xE CLKIN 66.666 MHz oscillator The MPC837xE uses CLKIN to generate the
PCI_SYNC_OUT clock signal, which is fed back to
the internal system PLL through the PCI_SYNC_IN
signal. From the power-on reset configuration, the
internal PLL generates the CSB clock, which is fed to
the e300 core PLL for generating the e300 core clock.
The PCI M66EN pin is inverted for
CFG_CLKIN_DIV configuration input, which
selects whether the PCI_SYNC_OUT signal is
CLKIN or CLkIN/2.
125 MHz MPC837xE eTSEC RTL8211B The gigabit Ethernet PHY (RTL8211B) provides a
125-MHZ clock for eTSEC operation.)
200 MHz DDR2 SDRAM MPC837xE The DDR memory controller is configured to use the
1:1 mode CSB to DDR clock for the DDR interface.
The local bus clock uses CCB/n clock, where n is
configured from the LCRR register.
25 MHz GBE PHY (RTL8211B) 25 MHz oscillator The 25 MHz oscillator generates the clock for
RTL8211B.
33/66 MHz Mini PCI slot MPC837xE The PCI module uses the PCI_SYNC_IN as its clock
source. The trace of the PCI_SYNC_IN/
PCI_SYNC_OUT signal is synchronized with all the
PCI signals of the PCI slots.
24 MHz USB PHY (USB3300) 24 MHz crystal
100 MHz SerDes Interface 25 MHz oscillator and
PI6C557-03 clock
generator
The SerDes reference clock uses 100 MHz.
100 MHz Mini PCI-e and PCI-e x1
Interface
25 MHz oscillator and
PI6C557-03 clock
generator

MPC837xE-RDS, Rev. 1.0
14 Freescale Semiconductor
Preliminary, Subject to Change without Notice
MPC837xE-RDS Board
Figure 5. DDR2 SDRAM Connection
2.1.5 Local Bus Controller
The MPC837xE local bus controller has a 32-bit LAD[0–31] address that consists of data multiplex bus
and control signals. The local bus speed is up to 133 MHz. To interface with the standard memory device,
an address latch must provide the address signals. The LALE is used as the latching signal. To reduce the
load of the high speed 32-bit local bus interface, there is a data buffer for all low-speed devices attached
to the memory controller. The local bus only drives the 64MB NOR Flash menory on the MPC837xE-RDS
board:
DDR2
SDRAM
Controller
Vref
Generator
Vref 0.9 V
1.8 V Input Vref
MSYNC_OUT
MSYNC_IN
MPC837xE
DDR2
SDRAM
Vref
Vref
DQ[0:63]
DQ[32:47]
DQ[0:15]
DM[0:7] DM[0,1]
DM[4,5]
DQS[0:7] DQS[0,1]
DQS[4,5]
A[0:12], BA[0:2],CTRL
MCK[0:3] pairs
MCK0
MCK2 pair
DDR2
SDRAM
DDR2
SDRAM
DQ[48:63]
DQ[16:31]
DM[2,3]
DM[6,7]
DQS[2,3]
DQS[6,7]
MCK1 pair
MCK3 pair
DDR2
SDRAM
Vref
Vref
1Gb(X16) 1Gb(X16)
1Gb(X16) 1Gb(X16)
pair

MPC837xE-RDS Board
MPC837xE-RDS, Rev. 1.0
Freescale Semiconductor 15
Preliminary, Subject to Change without Notice
Figure 6 shows the block diagram and connections for the local bus.
Figure 6. Local Bus Connections
2.1.6 Flash Memory
MPC837xE-RDS provides 64Mbytes NOR Flash memory using general-purpose chip-select machine
(GPCM). The NOR Flash is 16-bit port size in the system. It is selected as the boot Flash when J12 pins 2
and 3 are jumpered together.
2.1.7 I2C
The MPC837xE has two I2C interfaces. On the MPC837xE-RDS board, the MPC837xE serves as I2C
master for both I2C buses (I2C1 and I2C2). I2C1 is connected to the following:
• Serial EEPROM M24256 at address 0x50.
• PCI-E and mini PCI-E socket.
The M24256 serial EEPROM can store the reset configuration word of the MPC837xE, as well as store
the configuration registers values if the boot sequencer of MPC837xE is enabled. The I2C address of the
M24256 EEPROM on I2C1 bus is 0x50.
A[24:0]
CS
S29GL512N
NOR Flash (16-bit)
MPC837xE
LAD[0:31]
BADDR[27:30]
D[15:0]
LALE
Address
LE
Local Bus
LCS0
Control
OE
D[0:15]
A[6:30]
LCS0
Latch
LCS0
Control
LAD[6:26]
LAD[0:15]
Controller
GND
Control Signals
LSYNC_OUT LSYNC_IN LCKE LCLK0 LCLK1

MPC837xE-RDS, Rev. 1.0
16 Freescale Semiconductor
Preliminary, Subject to Change without Notice
MPC837xE-RDS Board
2.1.8 SATA Controller
MPC837xE has a SATA controller for storage applications as shown in Figure 7. There are two SATA
channels for MPC8377E. It requires a 100-MHz input clock, which is provided by the clock generator.
2.1.9 PCI Express Interface (PCI-E & Mini PCI-E)
MPC8377E supports the PCI Express (PCI-E) interface. It can be configured as two mini PCI-E interfaces
or one mini PCI-E interface and one 1X PCI-E interface as shown in Figure 7. It also requires a 100-MHz
input clock, which is provided by the clock generator.
Figure 7. SATA and PCI-E Connections
2.1.10 10/100/1000 BaseT Interface
On the MPC837xE-RDS board, eTSEC1 and eTSEC2 use RGMII mode. The eTSEC1 and eTSEC2 drive
two on-board 10/100/1000 PHYs (RTL8211B), respectively. The I/O voltage is set to 3.3 V RGMII for
RTL8211B. The RGMII (1000 BaseT) is a source synchronous bus. For a transmit bus connection, it is
synchronous to GTX_CLK from the TSEC module. The receive bus connection is synchronous to
RX_CLK generated from the PHY device. The MPC837xE MII management interface also connects to
MPC8377E
SATA
eSATA Channel
eSATA Channel
PCI-E (1X)
Mini PCI-E
& PCI-E
Or
Mini PCI-E

MPC837xE-RDS Board
MPC837xE-RDS, Rev. 1.0
Freescale Semiconductor 17
Preliminary, Subject to Change without Notice
the RTL8211B. Figure 8 shows the connection between the MPC837xE eTSEC1 and eTSEC2 to the
RTL8211B.
Figure 8. RGMII Interface Connection for 10/100/1000 BaseT Ethernet
2.1.11 RS-232 Port
Figure 9 illustrates the serial port connection using a SP3232 3.3 V RS-232 driver to interface with a 2 x
5 Header. This serial connection runs at up to 115.2 Kbps.
Figure 9. UART Debug Port Connection
2.1.12 USB 2.0 Interface
The MPC837xE has a internal USB modules (dual-role (DR) module). On the MPC837xE-RDS board, it
connects to the USB PHY (USB3300) through the 8-bit UTMI low-pin-count interface (ULPI). The
RJ-45
eTSEC1
MPC837xE
RTL8211B
MDIO
MDC
EC_MDIO
EC_MDC
RGMII interface
PHY addr = 0x02
eTSEC2
3.3 V
LVDD2
RJ-45
(Enet0, supports PoE)
(Enet1)
3.3 V
LVDD1
RGMII interface RTL8211B
MDIO
MDC
PHY addr = 0x03
SP3232
TXD
RXD
CTS
RX
TX
TX
DO
DI
DI
MPC837xE
RTS
RS-232
Serial
Port
RXRXD
RTS
TXD
CTS
DO
UART0
4
6
8
3
7
5
2
1
910
TXD
RTS

MPC837xE-RDS, Rev. 1.0
18 Freescale Semiconductor
Preliminary, Subject to Change without Notice
MPC837xE-RDS Board
USB3300 PHY connects to a Type A receptacle connector that serves as a host interface. Figure 10 shows
the connection of USB.
Figure 10. USB Port Connections
2.1.13 PCI Subsystem
The MPC837xE has PCI interfaces. It connects to two 32-bit 3.3 V mini PCI slots, as shown in Figure 11.
Figure 11. PCI Subsystem
2.1.14 COP/JTAG Port
The common on-chip processor (COP) is part of the MPC837xE JTAG module and is implemented as a
set of additional instructions and logic. This port can connect to a dedicated emulator for extensive system
debugging. Several third-party emulators in the market can connect to the host computer through the
MPC837xE
ULPI_D[7:0]
ULPI_STP
ULPI_NXT
ULPI_CLK
DIR
USB3300
D[7:0]
STP
NXT
CLKOUT
ULPI_DIR VBUS
DM
ID
5V
DP
USB_TYPE_A_RECEPTACLE
MPC837xE
32-Bit PCI
PCI-AD[0:31]
PCI-CBE[0:3]
PCI-REQ0
PCI-GNT0
PCI-CTRL 32-Bit 3.3 V
Mini PCI Slot
32-Bit 3.3 V
Mini PCI Slot
PCI-REQ1
PCI-GNT1
AD15
AD14

MPC837xE-RDS Board
MPC837xE-RDS, Rev. 1.0
Freescale Semiconductor 19
Preliminary, Subject to Change without Notice
Ethernet port, USB port, parallel port, RS-232, etc. Figure 12 shows a typical setup using a USB port
emulator.
Figure 12. Connecting the MPC837xE-RDS Board to a Parallel Emulator
The 16-pin generic header connector carries the COP/JTAG signals and the additional signals for system
debugging. Figure 13 shows the connector pinout.
Figure 13. MPC837xE-RDS Board COP Connector
PC
MPC837xE-RDS
J4
USB
Emulator
TDI
Pull-up
TCK
TMS
SRESET
HRESET
CKSTP_OUT
GND
TRST
Pull-up
NC
NC
GND
1
TDO
NC
NC

MPC837xE-RDS, Rev. 1.0
20 Freescale Semiconductor
Preliminary, Subject to Change without Notice
MPC837xE-RDS Board
2.2 MPC837xE-RDS Assembly
Figure 14 shows the MPC837xE-RDS board top view, with the references of LEDs, jumpers, headers, and
switches.
Figure 14. MPC837xE-RDS Top View
CAUTION
Use 3.3 V mini PCI cards only for mini PCI slots. Power down before
insertion or removal.
48 V DC Power
J13
J15
J14
P1 WAN (supports PoE)
P2 LAN
MPC837xE
JP1 J4
COP Connector
Pin 1
J12
eSATA
J16
SW1
Reset
J7
J6
RS232 COM1
P3
Mini PCI (Top)
P4
Mini PCI (Bottom)
P5
Mini PCI-E
P6
Mini PCI-E
J10 P7
PCI-E (1x)
J5
USB
D7
D8
D9
Pin 1
D14
D15
D11