NXP Semiconductors QorIQ LX2160A User manual

QorIQ LX2160A Reference Design
Board Reference Manual
Supports LX2160ARDB Revision B
Document Number: LX2160ARDBRM
Rev. 0, 09/2018

QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
2 NXP Semiconductors

Contents
Section number Title Page
Chapter 1
LX2160ARDB Overview
1.1 Acronyms and abbreviations...........................................................................................................................................7
1.2 Related documentation....................................................................................................................................................9
1.3 Block diagrams............................................................................................................................................................... 10
1.4 Board features................................................................................................................................................................. 12
1.5 Board top view................................................................................................................................................................14
Chapter 2
LX2160ARDB Functional Description
2.1 Power supplies................................................................................................................................................................ 17
2.2 Clocks............................................................................................................................................................................. 25
2.3 DDR interface................................................................................................................................................................. 28
2.4 SerDes interface..............................................................................................................................................................31
2.5 Ethernet controller interface........................................................................................................................................... 33
2.6 Ethernet management interface.......................................................................................................................................35
2.7 eSDHC interface............................................................................................................................................................. 36
2.8 XSPI interface.................................................................................................................................................................38
2.9 USB interface .................................................................................................................................................................40
2.10 I2C interface....................................................................................................................................................................41
2.11 UART interface...............................................................................................................................................................45
2.12 CAN interface................................................................................................................................................................. 47
2.13 JTAG port....................................................................................................................................................................... 48
2.14 Interrupt controller..........................................................................................................................................................48
2.15 GPIO access....................................................................................................................................................................50
2.16 Temperature measurement..............................................................................................................................................51
2.17 LEDs............................................................................................................................................................................... 52
2.18 DIP switches................................................................................................................................................................... 55
2.19 System controller ........................................................................................................................................................... 58
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Section number Title Page
Chapter 3
Qixis Programming Model
3.1 Register Conventions......................................................................................................................................................67
3.2 Resets..............................................................................................................................................................................67
3.3 Identification Registers................................................................................................................................................... 68
3.4 Identification (ID)........................................................................................................................................................... 68
3.5 Board Version (VER)..................................................................................................................................................... 69
3.6 Qixis Version (QVER)....................................................................................................................................................70
3.7 Programming Model (MODEL)..................................................................................................................................... 71
3.8 Minor Revision (MINOR).............................................................................................................................................. 72
3.9 Control and Status Registers...........................................................................................................................................73
3.10 General Control (CTL)................................................................................................................................................... 74
3.11 Auxiliary (AUX).............................................................................................................................................................75
3.12 System Status (STAT_SYS)...........................................................................................................................................76
3.13 Alarm (ALARM)............................................................................................................................................................ 77
3.14 Presence Detect 1 (STAT_PRES1).................................................................................................................................78
3.15 Presence Detect 2 (STAT_PRES2).................................................................................................................................80
3.16 LED Control (LED)........................................................................................................................................................ 80
3.17 Reconfiguration Registers...............................................................................................................................................81
3.18 Reconfiguration Control (RCFG)................................................................................................................................... 82
3.19 SFP CSR 1 (SFP1)..........................................................................................................................................................83
3.20 SFP CSR 2 (SFP2)..........................................................................................................................................................84
3.21 SFP CSR 3 (SFP3)..........................................................................................................................................................85
3.22 LOS Status (LOS)...........................................................................................................................................................86
3.23 Watchdog (WATCH)......................................................................................................................................................87
3.24 Power Control/Status Registers...................................................................................................................................... 89
3.25 Power Control 2 (PWR_CTL2)...................................................................................................................................... 89
3.26 Power Event Trace (PWR_EVENT).............................................................................................................................. 90
3.27 Power Status 0 (PWR_MSTAT).....................................................................................................................................91
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Section number Title Page
3.28 Power Status 1 (PWR_STAT1)...................................................................................................................................... 92
3.29 Power Status 2 (PWR_STAT2)...................................................................................................................................... 94
3.30 Clock Control Registers..................................................................................................................................................95
3.31 Clock Speed 1 (CLK_SPD1).......................................................................................................................................... 95
3.32 Clock ID/Status (CLK_ID).............................................................................................................................................96
3.33 Reset Control Registers...................................................................................................................................................97
3.34 Reset Control (RST_CTL)..............................................................................................................................................98
3.35 Reset Status (RST_STAT)..............................................................................................................................................99
3.36 Reset Event Trace (RST_REASON).............................................................................................................................. 100
3.37 Reset Force 1 (RST_FORCE1).......................................................................................................................................101
3.38 Reset Force 2 (RST_FORCE2).......................................................................................................................................102
3.39 Reset Force 3 (RST_FORCE3).......................................................................................................................................103
3.40 Reset Mask 1 (RST_MASK1)........................................................................................................................................ 104
3.41 Reset Mask 2 (RST_MASK2)........................................................................................................................................ 106
3.42 Reset Mask 2 (RST_MASK3)........................................................................................................................................ 107
3.43 Board Configuration Registers....................................................................................................................................... 108
3.44 Board Configuration 0 (BRDCFG0)...............................................................................................................................108
3.45 Board Configuration 1 (BRDCFG1)...............................................................................................................................109
3.46 Board Configuration 2 (BRDCFG2)...............................................................................................................................110
3.47 Board Configuration 3 (BRDCFG3)...............................................................................................................................111
3.48 Board Configuration 4 (BRDCFG4)...............................................................................................................................112
3.49 DUT Configuration Registers.........................................................................................................................................114
3.50 DUT Configuration 0 (DUTCFG0)................................................................................................................................ 114
3.51 DUT Configuration 1 (DUTCFG1)................................................................................................................................ 115
3.52 DUT Configuration 2 (DUTCFG2)................................................................................................................................ 116
3.53 DUT Configuration 6 (DUTCFG6)................................................................................................................................ 117
3.54 DUT Configuration 11 (DUTCFG11)............................................................................................................................ 118
3.55 DUT Configuration 12 (DUTCFG12)............................................................................................................................ 119
3.56 IRQ Management Registers............................................................................................................................................120
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Section number Title Page
3.57 Interrupt Status 0 (IRQSTAT0)...................................................................................................................................... 120
3.58 Interrupt Status 1 (IRQSTAT1)...................................................................................................................................... 122
3.59 Interrupt Control 0 (IRQCTL0)...................................................................................................................................... 123
3.60 Interrupt Control 2 (IRQCTL2)...................................................................................................................................... 124
3.61 Interrupt Drive 0 (IRQDRV0)........................................................................................................................................ 125
3.62 Interrupt Drive 1 (IRQDRV1)........................................................................................................................................ 126
3.63 Interrupt Drive 2 (IRQDRV2)........................................................................................................................................ 127
3.64 Interrupt Drive 5 (IRQDRV5)........................................................................................................................................ 128
3.65 Core Management Space Registers................................................................................................................................ 129
3.66 Core Management Address (CMSA)..............................................................................................................................130
3.67 Core Management Data (CMSD)................................................................................................................................... 131
3.68 Switch Manager Registers.............................................................................................................................................. 131
3.69 Switch Control (SWS_CTL)...........................................................................................................................................132
3.70 Switch Sample Status (SWS_STAT)..............................................................................................................................133
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Chapter 1
LX2160ARDB Overview
The QorIQ®LX2160A reference design board (RDB) provides a comprehensive
platform that enables design and evaluation of the QorIQ LX2160A processor. The
LX2160ARDB comes pre-loaded with a board support package (BSP) based on a
standard Linux kernel. The board comes in a 1U rackmount chassis form factor. It is
lead-free and RoHS-compliant.
The board:
• Enables network intelligence with the next generation Datapath (DPPA2) which
provides differentiated offload and a rich set of input/output, including 10/25/40
Gigabit Ethernet and PCIe Gen 4
• Delivers unprecedented efficiency and new virtualized networks
• Supports designs in 5G packet processing, network function virtualization, storage
controller, white box switching, network interface cards, and mobile edge computing
• Supports all three LX2 family members (16-core LX2160A, 12-core LX2120A, and
8-core LX2080A)
This document provides detailed information about LX2160ARDB interfaces, power
supplies, clocks, DIP switches, LEDs, and CPLD system controller.
1.1 Acronyms and abbreviations
The table below lists and explains the acronyms and abbreviations used in this document.
Table 1-1. Acronyms and abbreviations
Term Description
ATX Advanced Technology eXtended
CAN Controller area network
CCI Cache coherency interconnect
CCS CodeWarrior connection server
CPLD Complex programmable logic device
Table continues on the next page...
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Table 1-1. Acronyms and abbreviations (continued)
Term Description
CTS Clear to send
DCM Development system control monitor
DDR SDRAM Double data rate synchronous dynamic random-access memory
DIMM Dual inline memory module
DIP Dual inline package
DPAA Data path acceleration architecture
DUT Device under test
EC Ethernet controller
ECC Error correcting code
ECID Electronic chip identification
EDINK e500 core demonstrative interactive nanokernel
EMI Ethernet management interface
eMMC Embedded multimedia card
eSDHC Enhanced secure digital host controller
FET Field-effect transistor
FlexSPI Flexible serial peripheral interface
FPGA Field-programmable gate array
GbE Gigabit Ethernet
GPIO General purpose input/output
HDLC High-level data link control
HSSI High-speed serial interface
I2C Inter-integrated circuit
JTAG Joint Test Action Group (IEEE®Standard 1149.1™)
LOS Loss of signal
MDIO Management data input/output
OCM Offline configuration manager
OTG On-The-Go
PBL Pre-boot loader
PLL Phase-locked loop
POR Power-on reset
PSU Power supply unit
PTP Precision time protocol
PWM Pulse width modulation
QSPI Quad serial peripheral interface
RCW Reset configuration word
RDIMM Registered dual inline memory module
RTC Real time clock
RTS Request to send
SATA Serial advanced technology attachment
Table continues on the next page...
Acronyms and abbreviations
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8 NXP Semiconductors

Table 1-1. Acronyms and abbreviations (continued)
Term Description
SDRAM Synchronous dynamic random-access memory
SerDes Serializer/deserializer
SGMII Serial gigabit media independent interface
SPD Serial presence detect
SPI Serial peripheral interface
SS Spread spectrum
SSC Spread spectrum clocking
TCXO Temperature compensated crystal (Xtal) oscillator
UART Universal asynchronous receiver/transmitter
UDIMM Unbuffered dual inline memory module
UFT Universal frequency translator
USB Universal serial bus
USXGMII Universal serial 10 gigabit media independent interface
XGT 10GBase-T
XSPI Octal serial peripheral interface
1.2 Related documentation
The table below lists and explains the additional documents and resources that you can
refer to for more information on the LX2160ARDB.
Some of the documents listed below may be available only under a non-disclosure
agreement (NDA). To request access to these documents, contact your local field
applications engineer (FAE) or sales representative.
Table 1-2. Related documentation
Document Description Location / how to access
QorIQ LX2160A Reference
Design Board Getting
Started Guide
Explains the LX2160ARDB settings and physical connections
needed to boot the board
QorIQ LX2160A Reference
Design Board Getting
Started Guide
QorIQ LX2160A Reference
Design Board Errata
Describes known errata and workarounds for the LX2160ARDB QorIQ LX2160A Reference
Design Board Errata
QorIQ LX2160A Product
Brief
Provides a brief overview of the LX2160A processor QorIQ LX2160A Product
Brief
QorIQ LX2160A Data Sheet Provides information about electrical characteristics, hardware
design considerations, and ordering information
Contact FAE / sales
representative
QorIQ LX2160A Family
Reference Manual
Provides a detailed description about the LX2160A QorIQ
multicore processor and its features, such as memory map, serial
interfaces, power supply, chip features, and clock information
Contact FAE / sales
representative
Table continues on the next page...
Chapter 1 LX2160ARDB Overview
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
NXP Semiconductors 9

Table 1-2. Related documentation (continued)
Document Description Location / how to access
QorIQ LX2160A Chip Errata Lists the details of all known silicon errata for the LX2160A Contact FAE / sales
representative
QorIQ LX2160A Design
Checklist, AN5407
This document provides recommendations for new designs
based on the LX2160A. This document can also be used to
debug newly designed systems by highlighting those aspects of a
design that merit special attention during initial system start-up.
Contact FAE / sales
representative
Layerscape LX2160A BSP This document explains how to use the QorIQ LX2160A BSP,
which is a Linux-based development kit, to evaluate and explore
the features of the LX2160A SoC.
Contact FAE / sales
representative
CodeWarrior Development
Studio for QorIQ LS series -
ARM V8 ISA, Targeting
Manual
This manual explains how to use the CodeWarrior Development
Studio for QorIQ LS series - ARM V8 ISA product.
CodeWarrior Development
Studio for QorIQ LS series -
ARM V8 ISA, Targeting
Manual
CodeWarrior TAP Probe
User Guide
Provides details of CodeWarrior®TAP, which enables target
system debugging through a standard debug port (usually JTAG)
while connected to a developer workstation through Ethernet or
USB
CodeWarrior TAP Probe
User Guide
1.3 Block diagrams
This section provides block diagrams showing major functional units of the LX2160A
processor and LX2160ARDB.
The figure below shows the LX2160A processor block diagram.
Block diagrams
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10 NXP Semiconductors

Core Complex
Basic Peripherals and Interconnect
Accelerators and Memory Control
Networking Elements
SMMUs
2 MB Packet Express Buffer
DCE - 100G
QBMan
WRIOP
SEC - 50G
SATA3 SATA3
SATA3 SATA3
24 lanes at up to 25 GHz
x8 Gen4 PCIe
x8 Gen4 PCIe
x4 Gen4 PCIe
x4 Gen4 PCIe
x4 Gen4 PCIe
x4 Gen4 PCIe
Cache Coherent Interconnect
4 x UART
8 x I2C
2 x SDHC/eMMC
3 x SPI Flash
FlexSPI
2 x USB 3.0
+ PHY
4 x GPIO
2 x WDOG
System control
Internal
BootROM
Security fuses
Security Monitor
Power
Management
Service Processor
System interfaces
2 x CAN-FD
2 x Flextimers
72-bit
(64-bit
+ ECC)
DDR4
memory
controller
72-bit
(64-bit
+ ECC)
DDR4
memory
controller
130 Gbps
1 / 2.5 / 10 / 25 / 40 / 50 / 100
Ethernet
qDMA
1 MB Chonerent
L2 Cache
Arm®
A72 core
ARM®
A72 Core
1 MB Coherent
L2 Cache
1 MB Chonerent
L2 Cache
Arm®
A72 core
Arm®
A72 core
1 MB Coherent
L2 Cache
1 MB Chonerent
L2 Cache
Arm®
A72 core
Arm®
A72 core
1 MB Coherent
L2 Cache
1 MB Chonerent
L2 Cache
Arm®
A72 core
Arm®
A72 core
1 MB Coherent
L2 Cache
1 MB Chonerent
L2 Cache
Arm®
A72 core
Arm®
A72 core
1 MB Coherent
L2 Cache
1 MB Chonerent
L2 Cache
Arm®
A72 core
Arm®
A72 core
1 MB Coherent
L2 Cache
1 MB Chonerent
L2 Cache
Arm®
A72 core
Arm®
A72 core
1 MB Coherent
L2 Cache
1 MB Chonerent
L2 Cache
Arm®
A72 core
Arm®
A72 core
1 MB Coherent
L2 Cache
8 MB Platform Cache
1 MB Chonerent
L2 Cache
Arm®
A72 core
1 MB Coherent
L2 Cache
Figure 1-1. LX2160A block diagram
The figure below shows the LX2160ARDB block diagram.
Chapter 1 LX2160ARDB Overview
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NXP Semiconductors 11

Qualcomm
AR8035
Aquantia
AQR107
PCIe x4 slot
Gen 1-4
LX2160A
Power supplies
VDD USB_HVDD
GVDD SD_SVDD
OVDD
USB 3.0
type A
SDHC
1
JTAG
RS232 IO
USB
3.0
I2C1
I2C devices
SPD SFP+
INA220 Temp
Fan PWM DCM
Qix CPLD Clocks
SystemID
UART
DB9 stack
JTAG
x4
Inphi
CS4223
SDHC
2
PWR
QSFP+
40G-SR4
40G-CR4
40G-KR4
S
E
R
D
E
S
1
12V
5V
3.3V
5VSB
RST
Dual RJ45
USXGMII
2x 10G
QixMin CPLD
system controller
Dual cage
SFP+
2x 25G
x4
CFG
C
L
O
C
K
S
uATX
Switches
USB 3.0
micro AB
SD slot
eMMC
128 GB
Aquantia
AQR107
Inphi
IN112525
x2
x2
x4
x2
x2
H,G
0,1
F,E
2,3
D-A
4-7
x4
S
E
R
D
E
S
2
A-D
0-3
E-H
4-7
S
E
R
D
E
S
3
PCIe x8 slot
Gen 1-4
x8
A-H
0-7
Protocol #19
Protocol #5
Protocol #2
DDR
1
DDR4 slot
288 pins
DDR
2
DDR4 slot
288 pins
x2
x2
x2
DB9 stack CAN IO x2 CAN1
CAN2
Up to 32 GB at 3200 MT/s
Qualcomm
AR8035 Dual RJ45
2x 1G
RGMII
HS
Mux
HS
mux IEEE
header
HS
Mux
HS
mux XSPI
A
SPI
emulator
MT35XU512
XSPI 64 MB
MT35XU512
XSPI 64 MB
Up to 32 GB at 3200 MT/s
SD1
161.13 MHz
SYS
DDR
100.00 MHz
SiliconLabs
Si52208
SD2
100 MHz
SD3
100 MHz
To
slots
125.00 MHz EC
To
10G
25G
40G
PHYs
UEFI memory
1 MB
PWM fans
100.00 MHz
SiliconLabs
Si5341
156.25 MHz
100.00 MHz
25.00 MHz
SATA 3.0SATA 3.0
I2C5
RTC
Figure 1-2. LX2160ARDB block diagram
1.4 Board features
The table below lists the features of the LX2160ARDB.
Board features
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Table 1-3. LX2160ARDB features
LX2160ARDB feature Specification Description
Processor 16-core processor 16 Arm®Cortex®-A72 processor cores based on 32-/64-bit Armv8
architecture, supporting speeds of up to 2.2 GHz
NOTE: For more details on the LX2160A processor, see QorIQ LX2160A
Family Reference Manual.
DDR memory Two 72-bit DDR4
ports (64-bit data, 8-bit
ECC)
Each DDR4 port supports:
• Two 288-pin DIMM connectors
• Four chip selects
• Single-/dual-rank, unbuffered/registered DDR4 memory modules
• 64-bit data bus
• x4, x8, and x16 data width memory
• Data rates of up to 3.2 GigaTransfers/second (GT/s)
• Double-bit error detection and single-bit error correction ECC (8-bit
check word across 64-bit data)
High-speed serial ports
(SerDes)
Three SerDes
controllers (24 lanes)
• SerDes1:
• Lanes 0-1: Supports two 10 GbE RJ45 USXGMII connectors,
each connected through an Aquantia AQR107 PHY
• Lanes 2-3: Supports two 25 GbE SFP+ modules, connected
through an Inphi IN112525 PHY
• Lanes 4-7: Supports one 40 GbE (40G-SR4, 40G-CR4, or
40G-KR4) QSFP+ module, connected through an Inphi
CS4223 PHY
• SerDes2:
• Lanes 0-3: Supports one PCIe x4 (Gen 1/2/3/4) connector
• Lanes 4-7: Supports four SATA 3.0 connectors
• SerDes3:
• Lanes 0-7: Supports one PCIe x8 (Gen 1/2/3/4) connector
• Each SerDes lane supports speeds of up to 25 GHz
eSDHC eSDHC1 Supports a secure digital (SD) connector (J42) for connecting an SD card
eSDHC2 Supports 128 GB Micron MTFC128GAJAECE-IT embedded multimedia
card (eMMC), supporting HS-400 high-speed transfer mode
Octal SPI (XSPI) One XSPI controller
(XSPI_A)
• Supports two 64 MB onboard octal SPI flash memories
• Supports a QSPI emulator for offboard QSPI emulation
I2C Six I2C controllers
(I2C1, I2C2, I2C3,
I2C4, I2C5, and I2C6)
• Most system devices (other than UEFI) are accessed via I2C1,
which is multiplexed to isolate address conflicts and reduce
capacitive load
• I2C1 is translated to 3V3_SB, allowing programming access to
devices, such as power controllers, clocks, and memories, while the
system is off
• I2C2 is only used for SDHC1_CD_B and SDHC1_WP
• I2C3 is only used for CAN1 input/output
• I2C4 is only used for CAN2 input/output
• I2C5 is used for UEFI support (memory and RTC)
• I2C6 is used for optional AQR107 PHY access
Serial ports Two UART ports
(UART1 and UART2)
A dual-stack DB9 male connector providing two UART connectors, each
connected through an RS-232 transceiver
USB 3.0 Two high-speed USB
3.0 ports with
integrated PHYs
• Supports super-speed (5 Gbit/s), high-speed (480 Mbit/s), full-speed
(12 Mbit/s), and low-speed (1.5 Mbit/s) operations
• USB#1 3.0 port is connected to a Type A host connector
• USB#2 3.0 port is configured as On-The-Go (OTG) with a Micro-AB
connector
Table continues on the next page...
Chapter 1 LX2160ARDB Overview
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Table 1-3. LX2160ARDB features (continued)
LX2160ARDB feature Specification Description
Ethernet Two tri-speed RGMII
interfaces
• 10 Mb / 100 Mb / 1 Gb Ethernet is supported
• An RJ45 connector with link and activity status is used with each
RGMII interface
• IEEE 1588™precision time protocol (PTP) is supported through an
onboard header (J29)
Clocks System clock
(SYSCLK) and DDR
clock (DDRCLK)
• 100 MHz differential clock to DIFF_SYSCLK
• 100 MHz single-ended clock to DDRCLK
SerDes clocks • 161.1328125 MHz clock to SerDes1 PLL 1 and PLL 2
• 100 MHz clock to SerDes2 PLL 1 and PLL 2
• 100 MHz clock to SerDes3 PLL 1 and PLL 2
• 100 MHz clock to AQR107 10 GbE PHY 1 and 2
• 25 MHz clock to IN112525 25 GbE PHY
• 156.25 MHz clock to CS4223 40 GbE PHY
• 100 MHz clock to x4 and x8 PCIe slots
Ethernet clocks 125 MHz clocks to Ethernet controllers and IEEE 1588 port
Power supplies • 12 V, 5 V, 3.3 V, and 5 V (standby) ATX power supplies
• 0.8 V (VDD) for the LX2160A core
• 1.2 V (G1VDD and G2VDD) for DDR4
• 0.92 V (SD_SVDD) for SerDes cores
• 1.8 V (SD_OVDD) for SerDes I/O drivers
• 0.9 V (SD_AVDD) for SerDes PLLs
• 1.8 V (OVDD) for general I/O
• 1.8 V (standby) and 3.3 V (standby) for CPLD core and I/O
• 0.8 V for USB_SVDD and USB_SDVDD
• 3.3 V for USB_HVDD
• 0.8 V (TA_BB_VDD) for the LX2160A secure monitor
• 1.8 V for TA_PROG_SFP and PROG_MTR
Debug features Arm Cortex 10-pin JTAG connector
Package • Package type is 40 mm x 40 mm, 1517 Flip Chip, Plastic-ball, Grid
Array (FC-PBGA)
• Socket and heat sink are included
System logic CPLD • Manages the following:
• System power sequencing
• System reset sequencing
• System and SerDes clock speed selections
• SoC POR configuration at reset
• Implements registers for system control and monitoring
• General fault monitoring and logging
1.5 Board top view
The figure below shows the top-side view of the LX2160ARDB.
Board top view
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14 NXP Semiconductors

Figure 1-3. LX2160ARDB top view
Chapter 1 LX2160ARDB Overview
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NXP Semiconductors 15

Board top view
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16 NXP Semiconductors

Chapter 2
LX2160ARDB Functional Description
The LX2160ARDB architecture is primarily determined by the LX2160A processor, with
the need to evaluate the LX2160A processor features and to deliver an easily usable, off-
the-shelf software development platform.
This chapter explains all major functional components of the LX2160ARDB. The chapter
is divided into the following sections:
•Power supplies
•Clocks
•DDR interface
•SerDes interface
•Ethernet controller interface
•Ethernet management interface
•eSDHC interface
•XSPI interface
•USB interface
•I2C interface
•UART interface
•CAN interface
•JTAG port
•Interrupt controller
•GPIO access
•Temperature measurement
•LEDs
•DIP switches
•System controller
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NXP Semiconductors 17

2.1 Power supplies
The LX2160ARDB provides all the voltages necessary for the correct operation of the
LX2160A processor, DDR4 UDIMM, PHYs, and numerous other peripherals. All power
is derived from an external power supply, which supplies bulk +12 V, +5 V, +3.3 V, as
well as +5 V standby power.
The ATX-compatible supply is managed by the system controller CPLD and drives the
power supplies shown in the figures below.
LX2160A VDD
Power
stage VDD
0.5mW(7W)
PS_VDD_EN
PS_VDD_PG
LTC3882
I2C1_CH1
INA220INA220
Power
stage
from CPLD
VDDo
0.825V @ 70A
SMBALERT_B
LTC7150
PS_GVDD_EN
PS_GVDD_PG
from CPLD
12V0 VIN LX2160A GVDD
VTT1 VDD
VTT2 VDD
DIMM[1:4] VDD
GVDD
0.5mW(7W)
MC34717EP/R2
PS_SD_VDD_EN
PS_SD_VDD_PG
SD_OVDD
1.80V @ 5A
LPFLPF
SD_OVDD_FLT
SD_VDD_FLT
LPFLPF
LPFx4LPFx4
AVDD_xyz
SD3_OVDD_FLT
from CPLD
5V0 VIN[1:2]
LX2160A SD3_OVDD
LX2160A SD_OVDD
SD_SVDD
0.92V @ 5A LX2160A SD_SVDD
LX2160A AVDD[1:5]
LX2160A AVDD_D[1:2]
LX2160A PROG_MTR
HDR 1x2
LX2160A TA_PROG_SFP
HDR 1x2 1K
1K
PS_SD_OVDD_SEL
LTC7150
PS_OVDD_EN
PS_OVDD_PG
from CPLD
12V0 VIN
LX2160A OVDD
LX2160A TH_VDD
LX2160A PROG_MTR
CS4223 40GE
AQR107_1 VDD_IO
AQR107_2 VDD_IO
XSPI / eMMC
OVDD
LPFLPF
SD3_VDD_FLT LX2160A SD3_SVDD
PS_SD_SVDD_SEL LPFLPF
GVDDo
1.20V @ 20A
OVDDo
1.80V @ 20A
12V0 VIN
Figure 2-1. Power supplies - Part 1
Power supplies
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
18 NXP Semiconductors

MC34712EP VTT1
0.60V @ 3A
PS_VTT1_EN
from CPLD
3V3 VIN1
UDIMM[1:2] VTT
PS_VTT1_PG
MC34712EP VTT2
0.60V @ 3A
PS_VTT2_EN
from CPLD
3V3 VIN1
UDIMM[3:4] VTT
PS_VTT2_PG
LTC3026EMSE
USB_SVDD_CPU
PS_USVDD_EN
from CPLD
3V3+5V VIN[1:2]
LX2160A USB_SVDD
PS_USVDD_PG
PS_USVDD_SEL
LPF
USB_SVDD
0.80V @ 1.5A
LPF
USB_SDVDD_CPU LX2160A USB_SDVDD
LTC3026EMSE
AVDD_SD1_PLL*
PS_SAVDD_EN
from CPLD
3V3+5V VIN[1:2] LX2160A AVDD_SD1_PLLF
LX2160A AVDD_SD1_PLLS
PS_SAVDD_PG
PS_SAVDD_SEL SD_AVDD
0.90V @ 1.5A
AVDD_SD2_PLL* LX2160A AVDD_SD2_PLLF
LX2160A AVDD_SD2_PLLS
AVDD_SD3_PLL* LX2160A AVDD_SD3_PLLF
LX2160A AVDD_SD3_PLLS
LTC7150
PS_0V85_EN
PS_0V85_PG
from CPLD
12V0 VIN IN112525 VDD
AQR107_1 VDD
AQR107_2 VDD
DIMM[1:4] VDD
0V85
0.85V @ 20A
NX5P2924BUK
3V3 LX2160A USB_HVDD
USB_HVDD_SW
3.30V @ 1.0A
PS_USB_HVDD_EN
from CPLD
LPF
USB_HVDD_CPU
FPF1321UCX
3V3+OVDD LX2160A EVDD
EVDD
1.80V @ 1.0A \
3.30V @ 1.0A
PS_EVDD_EN
from CPLD
PS_EVDD_SEL
LPFx2
LPFx2
LPFx2
Figure 2-2. Power supplies - Part 2
Chapter 2 LX2160ARDB Functional Description
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
NXP Semiconductors 19

MAX8902B
3V3_SB LX2160A TA_BB_VDD
TA_BB_VDD
0.8V @ 0.5A
PS_TA_BB_SEL
from CPLD
PS_TA_BB_PG_B
MC34717EP/R2
PS_LVAUX_EN
PS_LVAUX_PG
1V2
1.20V @ 5A
from CPLD
5V0 VIN[1:2] IN112525 RT1_VDD*
AQR107_1 P0_VA12*
AQR107_2 P0_VA12*
0V9
0.9V @ 5A CS4223 VDD
CS4223 AVDD
MC34717EP/R2
PS_2VX_EN
PS_2VX_PG
2V5
2.50V @ 5A
from CPLD
5V0 VIN[1:2] MAX14591 VDD
MX25V4006 VDD
2V1
2.10V @ 5A AQR107_1 VA21_*
AQR107_2 VA21_*
MC34717EP/R2
3V3_SB
3.30V @ 1.5A
5V0_SB VIN[1:2] EPM2210 IO
PCF2129 VBAT
LTC3882 I2C_IO
MAX8902 TA_BB
1V8_SB
1.80V @ 1.5A EPM2210 IO
EPM2210 VDD
Figure 2-3. Power supplies - Part 3
Note that several power supplies have onboard low-pass filters, to prevent board
switching noise from coupling into sensitive analog supplies. The figure below shows the
filters used.
2.2uF 2.2uF
2.2uF=NFM18PC225B1A3
2.2uF=GRM155R60J225KE95
LPF
LPF
47uF 3nF
4.7uF
0.33OHm
LPF
10uF 1uF
5.1OHm
0.22uF
Figure 2-4. Passive low pass filters
2.1.1 Primary power supply
The primary power supply for the LX2160ARDB is an external 300 W ATX12V/
EPS12V power supply. The following tables show its main features.
Table 2-1. Primary power supply
Power supply Description
External ATX 12 V power
supply
Vin 90 - 264 Vac
Fin frequency 50 - 60 Hz
Table continues on the next page...
Power supplies
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 0, 09/2018
20 NXP Semiconductors