NXP Semiconductors ADC1002S020 User manual

Quick Start ADC1002S020
Demonstration board for ADC1002S020
Rev. 2 — 11 octobre 2010 Quick Start
Document information
Info Content
Keywords DEMO8766G, PCB769-2, Demonstration board, ADC, Converter,
ADC1002S020
Abstract This document describes how to use the demonstration board
DEMO8766G for the analog-to-digital converter ADC1002S020.
Overview

NXP Semiconductors
Quick Start ADC1002S020
QS ADC1002S020
QS_ADC1002S020_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Quick Start Rev. 2 — 11 octobre 2010 2 of 24
Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]
Revision history
Rev Date Description
1 20080612 Initial version.
2 20101011 Update for data acquisition system.

NXP Semiconductors
QS ADC1002S020
Quick Start ADC1002S020
Quick Start
QS_ADC1002S020_2
Rev. 2 — 11 octobre 2010
3 of
24
1. Overview of the ADC1002S020 demo board
1.1 ADC1002S020 demoboard
Figure 1 presents the connections to measure the ADC1002S020 based on DEMO8766G:
Fig 1. ADC1002S020 demoboard set-up
P
OWER SUPPLY
. I = 50 mA
. 12 V
.GND
LOGIC
ANALYZER
Output data:
. D9 (MSB) to D0 (LSB)
C
LOCK SIGNAL
. sinewave
. AC
SYNTHESIZED
SIGNAL
GENERATOR
I
NPUT SIGNAL
. 2 V
pp
sinewave
. AC
SYNTHESIZED
SIGNAL
GENERATOR
F
ILTER
. High-order
. Band pass
P
RESENTED CONFIGURATION
. 2V
pp
input full scale
. Single TTL-CMOS clock signal
. 3.3 V power supply
. ADC active
. Binary ADC output
. VRB = 1.2 V
DC
. VI+OFS = VRM (= 2.25 V
DC
)
. VRT = 3.3 V
DC
Synchronized

NXP Semiconductors
Quick Start ADC1002S020
QS ADC1002S020
QS_ADC1002S020_2
©
NXP B.V.
2010
. All rights reserved.
Quick Start Rev. 2 — 11 octobre 2010 4 of 24
1.2 Power supply
The board is powered with a single 12 V
DC
power supply. A power supply regulator is
used to supply all the circuitry on the board.
Table 1. General power supply
Name Function View
J3 Green connector – Power supply 12 V
DC
/ 50 mA.
DS2 PWR green light – It indicates the good supply plugging
PWR switch – ADC power supply selectionK3
3.3 V 5 V
TP31 VCC test point – ADC power supply
TM1,
TM2 MASSE test point – Analog ground
TM3,
TM4 GND test point – Digital ground
STDBY switch – ADC stand-by activationK2
ADC active ADC OFF
1.3 DC voltage adjustments
The ADC1002S020 allows to adjust the full scale input signal from 1.6 V to 2.4 V.
Table 2. DC voltage adjustments
Name Function View
P1 VRT trimmer – TOP reference adjustment
TP1 VRT test point – TOP reference value (typ 3.3 V)
P2 VRB trimmer – BOT reference adjustment
TP5 VRB test point – BOT reference value (typ 1.2 V)
P3 OFS trimmer – Input signal DC offset adjustment
TP3 VI+OFS test point – Input signal DC offset (typ 2.25 V)
TP7 VRM test point – MIDDLE reference value (typ 2.25 V)

NXP Semiconductors
Quick Start ADC1002S020
QS ADC1002S020
QS_ADC1002S020_2
©
NXP B.V.
2010
. All rights reserved.
Quick Start Rev. 2 — 11 octobre 2010 5 of 24
1.4 Input signals (VI, CLK)
To ensure a good evaluation of the device, the input signal and the input clock must be
synchronized together.
Moreover, the input frequency (Fi, MHz) and the clock frequency (Fclk, Msps) should
follow the formula:
, where M is an odd number of period and N is the number of samples.
Table 3. Input signals
Name Function View
J2 VI connector – Analog input signal ( 50Ω matching)
J3 CLK connector – Clock input signal ( 50Ω matching)
1.5 Output signals (D0 to D9, IR)
Table 4. Output signals
Name Function View
TP10
to
TP30
Array connector – ADC digital output(D0 to D9) and In
range signal (IR)
DS1 IR green light – It indicates that the analog input signal is
in the full scale range
OEN switch – Output enable selection
K1
Active output
High impedance
output

NXP Semiconductors
QS ADC1002S020
Quick Start ADC1002S020
Quick Start
QS_ADC1002S020_2
Rev. 2 — 11 octobre 2010
6 of
24
2. HSDC extension module: acquisition board
The figure 2 shows an overview of the extension module HSDC-EXTMOD01/DB acquisition board:
Fig 2. HSDC extension module: acquisition board
+5V
P
OWER SUPPLY
. I = 3.2 A
R
EFERENCE SIGNAL
. typical 10 MHz
SIGNAL
GENERATOR
USB
SPI
MODULE
P
RESENTED CONFIGURATION
. acquisition board
. external reference signal
. LVDS DDR 16-bit input stream
. CMOS 2 16
-
bit channels input
LVDS
DDR
I/O
CONNECTOR
.
up to 325 MHz 16
-
bit LVDS DDR
CMOS
I/O
CONNECTOR
. 2 channels up to 200 MHz 16-bit
J
UMPER FOR
I/O
SUPPLY
. define either I/O is 1.8 V or 3.3 V

NXP Semiconductors
Quick Start ADC1002S020
QS ADC1002S020
QS_ADC1002S020_2
©
NXP B.V.
2010
. All rights reserved.
Quick Start Rev. 2 — 11 octobre 2010 7 of 24
The HSDC extension module is intended for acquisition/generation and clock generation
purpose. When connected to an ADC demo-board it is intended as an acquisition system
for digital output bits delivered by ADC, either CMOS (HE14 P1 connector) or LVDS DDR
(SAMTEC QTH_060_02 P2 connector).
The board brief specification is shown below:
•8MB memory size for acquisition pattern;
•2 16-bit channels CMOS up to 200 MHz;
•16-bit LVDS DDR input data stream up to 320 MHz;
•On-board or external reference for signal generation.
In this section the specific requirement for the use with ADC1002S020 demo-board will
be shown.
For more details on the HSDC-EXTMOD01/DB, please contact dataconverter-
[e-mail].
2.1 HSDC extension module: hardware initialization
Before using the generation board, make sure that you connect the USB cable prior to
the supply.
2.2 HSDC extension module: software initialization
Before using the generation board, the user needs to install software to control the board.
The steps are described below.
Go to the installation directory “\HSDC-EXTMOD01\Software\USBConfigSetup v1.3
100212 1525” on the CD. Double click on the file “CDM 2.04.16.exe” file.
Run the application “\HSDC-EXTMOD01\Software\USBConfigSetup v1.3 100212
1525\USBConfigSetup.msi”, this will display the following window:
Fig 3. “USBConfigSetup” window: step 1
Click “Next” to proceed with installation process:

NXP Semiconductors
Quick Start ADC1002S020
QS ADC1002S020
QS_ADC1002S020_2
©
NXP B.V.
2010
. All rights reserved.
Quick Start Rev. 2 — 11 octobre 2010 8 of 24
Fig 4. “USBConfigSetup” window: step 2
Click “Next” to continue:
Fig 5. “USBConfigSetup” window: step 3
Click “Next” to finish the installation process.
The system is now ready to use the ADC1412D series board for evaluation purpose.
2.3 HSDC extension module: CMOS connector description
The figure 6 shows a brief description of the hardware connection on the HE14
connector:

NXP Semiconductors
Quick Start ADC1002S020
QS ADC1002S020
QS_ADC1002S020_2
©
NXP B.V.
2010
. All rights reserved.
Quick Start Rev. 2 — 11 octobre 2010 9 of 24
Fig 6. HSDC extension module: HE14 CMOS hardware schematic overview
The HSDC extension module can acquire data in CMOS level using:
•either the on-board clock generated by the internal PLL, refer to as
pDFS_CLK[0]/nDFS_CLK[0] that will be used by the FPGA. In this case, the
reference of the board should be delivered by the clock signal generator;

NXP Semiconductors
Quick Start ADC1002S020
QS ADC1002S020
QS_ADC1002S020_2
©
NXP B.V.
2010
. All rights reserved.
Quick Start Rev. 2 — 11 octobre 2010 10 of 24
•or the clock provided by the ADC refer to as P1_CLK_IN. This is the preferred
situation since the user will not deal with any set-up/hold timing for the acquisition.
Refer to section 3.2 for software configuration.