NXP Semiconductors ADC1412D Series User manual

Quick start ADC1412D,
ADC1212D, ADC1112D series
Demonstration board for ADC1412D, ADC1212D, ADC1112D
series
Rev. 10 — 17 December 2010 Quick start
Document information
Info Content
Keywords PCB2004-1, Demonstration board, ADC, Converter, ADC1412D,
ADC1212D and ADC1112D series.
Abstract This document describes how to use the demonstration board for the
analog-to-digital converter ADC1412D, ADC1212D and ADC1112D
series.
Overview

NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series
Quick start
QS_ADC1412D_10.doc
©
NXP B.V.
2010
. All rights reserved.
Quick start Rev. 10 — 17 December 2010 2 of 27
Revision history
Rev Date Description
1 20081001 Initial version.
2 20090518 Update to PCB2004-1.2.
3 20090610 Add SPI software description.
4 20100518 Update to latest release of SPI software.
Add HSDC extension module acquisition system description.
5 20100601 Correction added.
6 20100730 Update for LVDS acquisition mode.
7 20100806 Update to latest acquisition software tool.
8 20100820 Update for web release.
9 20100924 Update with latest board reference.
10 20101217 Update with latest software tool.

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Quick start ADC1412D, ADC1212D, ADC1112D series
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QS_ADC1412D_10.doc
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1. Overview of the ADC1412D, ADC1212D, ADC1112D demo board
1.1 ADC1412D series
Figure 1 presents the connections to measure the ADC1412D series:
Fig 1. ADC1412D series typical configuration set-up (e.g. demoboard F1/DB)
P
OWER SUPPLY
. I = 370 mA
. 3 V
.GND
P
OWER SUPPLY
. I = 40 mA
.GND
.1.8 V
LOGIC
ANALYZER
Output data ADC A (top to
bottom):
. DA13 (MSB) to DA0 (LSB)
C
LOCK SIGNAL
. sinewave
. AC
SYNTHESIZED
SIGNAL
GENERATOR
USB
SPI
MODULE
I
NPUT
B
SIGNAL
. 2 V
pp
sinewave
. AC
SYNTHESIZE
D
SIGNAL
GENERATOR
I
NPUT
A
SIGNAL
. 2 V
pp
sinewave
. AC
SYNTHESIZED
SIGNAL
GENERATOR
F
ILTER
. High-order
. Band pass
F
ILTER
. High-order
. Band pass
P
RESENTED CONFIGURATION
. 2 V
pp
input full scale
. Single Sine wave clock signal
. Input common mode from IC
. Binary ADC output
. SPI Mode
. DAV for synchronization
Output data ADC B (top to
bottom):
. DB0 (LSB) to DB13 (MSB)

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1.2 ADC1212D series
Figure 2 presents the connections to measure the ADC1212D series:
Fig 2. ADC1212D series typical configuration set-up (e.g. demoboard F1/DB)
P
OWER SUPPLY
. I = 370 mA
. 3 V
.GND
P
OWER SUPPLY
. I = 40 mA
.GND
.1.8 V
LOGIC
ANALYZER
Output data ADC A (top to
bottom):
. DA11 (MSB) to DA0 (LSB)
C
LOCK SIGNAL
. sinewave
. AC
SYNTHESIZED
SIGNAL
GENERATOR
USB
SPI
MODULE
I
NPUT
B
SIGNAL
. 2 V
pp
sinewave
. AC
SYNTHESIZED
SIGNAL
GENERATOR
I
NPUT
A
SIGNAL
. 2 V
pp
sinewave
. AC
SYNTHESIZED
SIGNAL
GENERATOR
F
ILTER
. High-order
. Band pass
F
ILTER
. High-order
. Band pass
P
RESENTED CONFIGURATION
. 2 V
pp
input full scale
. Single Sine wave clock signal
. Input common mode from IC
. Binary ADC output
. SPI Mode
. DAV for synchronization
Output data ADC B (top to
bottom):
. DB0 (LSB) to DB11 (MSB)

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1.3 ADC1112D series
Figure 3 presents the connections to measure the ADC1112D series:
Fig 3. ADC1112D series typical configuration set-up (e.g. demoboard F1/DB)
P
OWER SUPPLY
. I = 370 mA
. 3 V
.GND
P
OWER SUPPLY
. I = 40 mA
.GND
.1.8 V
LOGIC
ANALYZER
Output data ADC A (top to
bottom):
. DA10 (MSB) to DA0 (LSB)
C
LOCK SIGNAL
. sinewave
. AC
SYNTHESIZED
SIGNAL
GENERATOR
USB
SPI
MODULE
I
NPUT
B
SIGNAL
. 2 V
pp
sinewave
. AC
SYNTHESIZED
SIGNAL
GENERATOR
I
NPUT
A
SIGNAL
. 2 V
pp
sinewave
. AC
SYNTHESIZED
SIGNAL
GENERATOR
F
ILTER
. High-order
. Band pass
F
ILTER
. High-order
. Band pass
P
RESENTED CONFIGURATION
. 2 V
pp
input full scale
. Single Sine wave clock signal
. Input common mode from IC
. Binary ADC output
. SPI Mode
. DAV for synchronization
Output data ADC B (top to
bottom):
. DB0 (LSB) to DB10 (MSB)

NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series
Quick start
QS_ADC1412D_10.doc
©
NXP B.V.
2010
. All rights reserved.
Quick start Rev. 10 — 17 December 2010 6 of 27
N
M
F
F
s
in
=
1.4 Power supply
The board is powered with a 3 V
DC
and 1.8/3 V
DC
power supplies. A power supply
regulator is used to supply all the circuitry on the board.
Table 1. General power supply
Name Function View
J8 +3 V green connector – Power supply 3 V
DC
/ 400 mA.
J7 +1.8 V green connector – Power supply 1.8 V
DC
/ 100 mA
TP1 AGND test point – Digital ground
TP2 DGND test point – Analog ground
1.5 Input signals (IN, CLK)
The input clock signal can be either a sinewave or a LVCMOS signal.
To ensure a good evaluation of the device, the input signal and the input clock must be
synchronized together.
Moreover, the input frequency (Fi, MHz) and the clock frequency (Fclk, Msps) should
follow the formula, known as coherency criteria for FFT processing (see section 3.3.6
and appendix A.1):
where M is an odd number of period and N is the number of samples.
Table 2. Input signals
Name Function View
J1 IN A connector – Analog input signal ( 50 Ω matching)
J2 CLKP connector – Single ended clock input signal ( 50 Ω
matching), with a transformer.
J3 CLKN connector – Grounded on that demoboard
J4 IN B connector – Analog input signal ( 50 Ω matching)
J8
J7
TP2
TP1
J1
J2
J3
J4

NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series
Quick start
QS_ADC1412D_10.doc
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2010
. All rights reserved.
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1.6 Output signals (DA0 to DA13, DB0 to DB13, OTRA, DAV)
The digital output signal is available in binary, 2’s complement or gray format.
A Data Valid Output clock (DAV) is provided by the device for the data acquisition.
Table 3. Output signals
Name Function View
J5 Array connector – ADC A digital output(DA0 to DA13),
Out of range signal (OTRA)
J6 Array connector – ADC B digital output(DB0 to DB13) and
Data Valid (DAV)
1.7 SPI Mode
The ADC1412D can be controlled either by a Serial Peripheral Interface (SPI) or by PIN.
Table 4. SPI Interface
Name Function View
J9 Array connector – SPI daughter board interface (for
debug only)
J10 USB connector – SPI daughter board interface
1.8 SPI program
For more details on how to control device with SPI, refer to section 3.3.
J6
J5
J9
J10
J9
J10

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Quick start
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s
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2. HSDC extension module: acquisition board
The figure 4 shows an overview of the extension module HSDC-EXTMOD01/DB acquisition board:
Fig 4. HSDC extension module: acquisition board
+5V
P
OWER SUPPLY
. I = 3.2 A
R
EFERENCE SIGNAL
. typical 10 MHz
SIGNAL
GENERATOR
USB
SPI
MODULE
P
RESENTED CONFIGURATION
. acquisition board
. external reference signal
. LVDS DDR 16-bit input stream
. CMOS 2 16
-
bit channels input
LVDS
DDR
I/O
CONNECTOR
.
up to 325 MHz 16
-
bit LVDS DDR
CMOS
I/O
CONNECTOR
. 2 channels up to 200 MHz 16-bit
J
UMPER FOR
I/O
SUPPLY
. define either I/O is 1.8 V or 3.3 V
RED LED
FOR POWER
SUPPLY CONNEC
TION
RED LED
FOR
+3V3
POWER
RED LED
FOR
USB
CONNECTION
GREEN LED FOR
EMBEDDED
PLL LOCK STATUS
FLASHING RED
FOR
FPGA STATUS

NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series
Quick start
QS_ADC1412D_10.doc
©
NXP B.V.
2010
. All rights reserved.
Quick start Rev. 10 — 17 December 2010 9 of 27
The HSDC extension module is intended for acquisition/generation and clock generation
purpose. When connected to an ADC demo-board it is intended as an acquisition system
for digital output bits delivered by ADC, either CMOS (HE14 P1 connector) or LVDS DDR
(SAMTEC QTH_060_02 P2 connector).
The board brief specification is shown below:
•32 MB memory size for acquisition pattern;
•2 16-bit channels CMOS up to 200 MHz;
•16-bit LVDS DDR input data stream up to 320 MHz;
•On-board or external reference for signal generation.
In this section the specific requirement for the use with ADC1412D demo-board will be
shown.
For more details on the HSDC-EXTMOD01/DB, please contact dataconverter-
[e-mail].
2.1 HSDC extension module: hardware initialization
Before using the generation board, make sure that you connect the USB cable prior to
the supply.
When USB and power cable are connected, the HSDC-EXTMOD will light 3 red LEDs.
The green LED close to the PLL is only when it is locked (see section 3.3).
The red LED close to FPGA reports normal behavior when flashing ¼ on, ¾ off. Any
other flashing behavior reports a failure at initialization (see section 3.3).
2.2 HSDC extension module: CMOS connector description
The figure 5 shows a brief description of the hardware connection on the HE14
connector.
For proper use of the acquisition board, make sure that resistor R86 (0 Ω) is connected
while R84 is removed.

NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series
Quick start
QS_ADC1412D_10.doc
©
NXP B.V.
2010
. All rights reserved.
Quick start Rev. 10 — 17 December 2010 10 of 27
Fig 5. HSDC extension module: HE14 CMOS hardware schematic overview