Oki ML63326 User manual

ML63326
User's Manual
CMOS 4-bit microcontroller
SECOND EDITION
ISSUE DATE: Sep. 1999
PEUL63326-02
¡
Preliminary

NOTICE
1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
9. MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
E2Y0002-29-62

Preface
This manual describes the hardware of Oki's original CMOS 4-bit microcontroller ML63326.
Refer to the "nX-4/250 Core Instruction Manual" for details of the 4-bit CPU core nX-4/250
which is built in the ML63326.
The manuals related to the ML63326 are shown below.
• nX-4/250 Core Instruction Manual:
Describes the base architecture and instruction set of nX-4/250 core.
• SASM63K User's Manual:
Describes the structured assembler operation and assembler language specifica-
tion.
• Dr. 63326 User's Manual:
Describes the hardware of the emulator.
• DT63K Debugger User's Manual:
Describes the debugger commands.
This document is subject to change without notice.

Notation
Classification Notation Description
nNumeric value xxh, xxH Represents a hexadecimal number.
xxb Represents a binary number.
nUnit word, W 1 word = 16 bits
byte, B 1 byte = 2 nibbles = 8 bits
nibble, N 1 nibble = 4 bits
mega-, M 106
kilo-, K 210 = 1024
kilo-, k 103= 1000
milli-, m 10-3
micro-, m10-6
nano-, n 10-9
second, s (lower case) second
KB 1 KB = 1 kilobyte = 1024 bytes
MB 1 MB = 1 megabyte = 220 bytes
= 1,048,576 bytes
nSymbol Note: Gives more information about mistakable items.
nTerminology “H” level Indicates high side voltage signal levels VIH and
VOH as specified by the electrical characteristics.
“L” level Indicates low side voltage signal levels VIL and
VOL as specified by the electrical characteristics.
nRegister description
Invalid bit : When read, a value of “1” is always obtained. Write operations are invalid.
R/W attribute : “R” indicates data can be read and “W” indicates data can be written.
!
Bit name
Invalid bit
Address
R/W attribute
Register name
PBF —PB1MOD PB0MOD
bit 3 bit 2 bit 1 bit 0
PBMOD0 (032H)
(R/W)

- i -
Table of Contents
Chapter 1 Overview
1.1 Overview........................................................................................................ 1-1
1.2 Features......................................................................................................... 1-1
1.3 Function List .................................................................................................. 1-5
1.4 Block Diagram................................................................................................ 1-6
1.5 Pin Configuration ........................................................................................... 1-7
1.6 Pin Descriptions ............................................................................................. 1-11
1.6.1 Descriptions of the Basic Pin Functions ............................................. 1-11
1.6.2 Descriptions of the Secondary Pin Functions..................................... 1-16
1.6.3 Unused Pin Processing ...................................................................... 1-18
1.7 Basic Timing .................................................................................................. 1-19
1.7.1 Basic Timing of CPU Operation.......................................................... 1-19
1.7.2 Port I/O Basic Timing.......................................................................... 1-19
1.7.3 Interrupt Basic Timing......................................................................... 1-21
Chapter 2 CPU and Memory Spaces
2.1 Overview........................................................................................................ 2-1
2.2 Registers........................................................................................................ 2-1
2.2.1 Accumulator (A).................................................................................. 2-1
2.2.2 Flag Register ...................................................................................... 2-1
2.2.2.1 Carry Flag (C)....................................................................... 2-1
2.2.2.2 Zero Flag (Z)......................................................................... 2-2
2.2.2.3 G Flag (G)............................................................................. 2-2
2.2.3 Master Interrupt Enable Flag (MIE) .................................................... 2-2
2.2.4 Current Bank Register (CBR), Extra Bank Register (EBR),
HL Register (HL), XY Register (XY) ................................................... 2-3
2.2.5 Program Counter (PC)........................................................................ 2-4
2.2.6 RA Registers (RA3, RA2, RA1, RA0) ................................................. 2-4
2.2.7 Stack Pointer (SP) and Call Stack...................................................... 2-5
2.2.8 Register Stack Pointer (RSP) and Register Stack.............................. 2-6
2.3 Memory Spaces ............................................................................................. 2-7
2.3.1 Program Memory Space..................................................................... 2-7
2.3.2 Data Memory Space........................................................................... 2-8
2.3.3 Memory Space for Voice Synthesis and Character Data ................... 2-9
2.3.4 External Memory Space ..................................................................... 2-10

- ii -
Chapter 3 CPU Control Functions
3.1 Overview ........................................................................................................ 3-1
3.2 System Reset Mode (RST) ............................................................................ 3-2
3.2.1 Transfer to and State of System Reset Mode .................................... 3-2
3.3 Halt Mode ...................................................................................................... 3-3
3.3.1 Transfer to and State of Halt Mode .................................................... 3-3
3.3.2 Halt Mode Release ............................................................................. 3-4
3.3.2.1 Release of Halt Mode by Interrupt........................................ 3-4
3.3.2.2 Release of Halt Mode by RESET Pin ................................... 3-4
3.3.3 Melody Data Interrupt and Halt Mode Release .................................. 3-5
3.3.4 Note Concerning HALT Instruction..................................................... 3-5
Chapter 4 Interrupt (INT326)
4.1 Overview ........................................................................................................ 4-1
4.2 Interrupt Registers ......................................................................................... 4-3
4.3 Interrupt Sequence ........................................................................................ 4-10
4.3.1 Interrupt Processing ........................................................................... 4-10
4.3.2 Return from an Interrupt Routine........................................................ 4-11
4.3.3 Interrupt Hold Instructions .................................................................. 4-11
Chapter 5 Clock Generator Circuit (OSC)
5.1 Overview ........................................................................................................ 5-1
5.2 Clock Generator Circuit Configuration ........................................................... 5-1
5.3 Low-Speed Clock Generator Circuit .............................................................. 5-2
5.4 High-Speed Clock Generator Circuit ............................................................. 5-4
5.5 System Clock Control .................................................................................... 5-6
5.6 Frequency Control Register (FCON) ............................................................. 5-7
5.7 System Clock Select Timing .......................................................................... 5-8
Chapter 6 Time Base Counter (TBC)
6.1 Overview ........................................................................................................ 6-1
6.2 Time Base Counter Configuration ................................................................. 6-1
6.3 Time Base Counter Registers........................................................................ 6-2
6.4 Time Base Counter Operation ....................................................................... 6-3

- iii -
Chapter 7 Timers (TIMER)
7.1 Overview........................................................................................................ 7-1
7.2 Timer Configuration ....................................................................................... 7-1
7.3 Timer Registers.............................................................................................. 7-3
7.4 Timer Operation ............................................................................................. 7-14
7.4.1 Timer Clock ........................................................................................ 7-14
7.4.2 Timer Data Registers.......................................................................... 7-14
7.4.3 Timer Counter Registers .................................................................... 7-14
7.4.4 Timer Interrupt Requests and Overflow Flags.................................... 7-15
7.4.5 Auto-Reload Mode Operation............................................................. 7-16
7.4.6 Capture Mode Operation .................................................................... 7-18
7.4.7 Frequency Measurement Mode Operation......................................... 7-21
Chapter 8 100 Hz Timer Counter (100HzTC)
8.1 Overview........................................................................................................ 8-1
8.2 100 Hz Timer Counter Configuration ............................................................. 8-1
8.3 100 Hz Timer Counter Registers ................................................................... 8-2
8.4 100 Hz Timer Counter Operation................................................................... 8-3
Chapter 9 Watchdog Timer (WDT)
9.1 Overview........................................................................................................ 9-1
9.2 Watchdog Timer Configuration ...................................................................... 9-1
9.3 Watchdog Timer Control Register (WDTCON) .............................................. 9-2
9.4 Watchdog Timer Operation............................................................................ 9-2

- iv -
Chapter 10 Ports (INPUT, OUTPUT, I/O PORT)
10.1 Overview ........................................................................................................ 10-1
10.2 Ports List ........................................................................................................ 10-1
10.3 Port 0 (P0.0–P0.3) ......................................................................................... 10-2
10.3.1 Port 0 Configuration.......................................................................... 10-2
10.3.2 Port 0 Registers................................................................................ 10-2
10.3.3 Port 0 External Interrupt Functions (External Interrupt 5)................. 10-5
10.4 Ports 4–7 (P4.0–P4.3, P5.0–P5.3, P6.0–P6.3, P7.0–P7.3)........................... 10-7
10.4.1 Port 4–7 Configuration...................................................................... 10-7
10.4.2 Port 4–7 Registers ............................................................................ 10-8
10.5 Port 8, Port 9, Port A (P8.0, P8.1, P9.0–P9.3, PA.0–PA.3) ........................... 10-15
10.5.1 Port 8, Port 9, Port A Configuration .................................................. 10-15
10.5.2 Port 8, Port 9, Port A Registers ........................................................ 10-16
10.6 Port B (PB.0–PB.3) ........................................................................................ 10-24
10.6.1 Port B Configuration ......................................................................... 10-24
10.6.2 Port B Registers ............................................................................... 10-25
10.6.3 Port B External Interrupt Function (External Interrupt 0) .................. 10-29
10.7 Port E (PE.0–PE.3) ........................................................................................ 10-30
10.7.1 Port E Configuration ......................................................................... 10-30
10.7.2 Port E Registers ............................................................................... 10-31
10.7.3 Port E.3 External Interrupt Function (External Interrupt 2) ............... 10-34
10.8 Port F (PF.0–PF.3)......................................................................................... 10-35
10.8.1 Port F Configuration ......................................................................... 10-35
10.8.2 Port F Registers................................................................................ 10-36
10.8.3 Port F External Interrupt Function (External Interrupt 3) .................. 10-40
Chapter 11 External Memory Transfer Function (EXTMEM)
11.1 Overview ........................................................................................................ 11-1
11.2 Connection with the External Memory ........................................................... 11-2
11.3 External Memory Address Space .................................................................. 11-3
11.4 Setting of Secondary Port Functions ............................................................. 11-4
11.5 Distinction between ROM Area inside the Chip and Memory Area External
to the Chip ..................................................................................................... 11-4
11.6 Reading from External Memory ..................................................................... 11-5
11.7 Reading from the Voice ROM inside the Chip ............................................... 11-6
11.8 Writing to External Memory ........................................................................... 11-7
Chapter 12 Melody Driver (MELODY63K)
12.1 Overview ........................................................................................................ 12-1
12.2 Melody Driver Configuration .......................................................................... 12-1
12.3 Melody Driver Registers ................................................................................ 12-2
12.4 Melody Circuit Operation ............................................................................... 12-4
12.4.1 Tempo Data...................................................................................... 12-5
12.4.2 Melody Data ..................................................................................... 12-6
12.4.3 Melody Circuit Application Example ................................................. 12-9
12.5 Buzzer Circuit Operation................................................................................ 12-10
12.6 Melody/Buzzer Output Selector Circuit .......................................................... 12-12
12.7 Differences with Voice Synthesis Section Melody/Buzzer Output ................. 12-13

Chapter 13 Voice Synthesis
13.1 Overview........................................................................................................ 13-1
13.2 Voice Synthesis Section Configuration.......................................................... 13-1
13.3 Registers Related to the Voice Synthesis Section......................................... 13-3
13.4 Voice ROM..................................................................................................... 13-8
13.4.1 Voice ROM Configuration................................................................. 13-8
13.4.2 Creation of Voice ROM Store Data .................................................. 13-9
13.5 Voice Synthesis Section Clock Input Frequency ........................................... 13-10
13.6 Operation of the Voice Synthesis Section...................................................... 13-11
13.6.1 Description of Pins Related to Voice Synthesis................................ 13-11
13.6.2 Phrase Address and Stop Code ....................................................... 13-12
13.7 Voice .............................................................................................................. 13-13
13.7.1 Voice Reproduction Method ............................................................. 13-13
13.7.1.1 4-Bit ADPCM Method ....................................................... 13-13
13.7.1.2 8-Bit Straight PCM Method............................................... 13-13
13.7.1.3 8-Bit Nonlinear PCM......................................................... 13-13
13.7.2 Forcible Stopping of Voice Output.................................................... 13-13
13.7.3 Voice Output Procedure ................................................................... 13-14
13.8 Voice Output Duration.................................................................................... 13-17
13.9 Melody ........................................................................................................... 13-18
13.9.1 Tempo Data...................................................................................... 13-18
13.9.2 Melody Data ..................................................................................... 13-20
13.9.3 Melody Circuit Application Example ................................................. 13-24
13.9.4 Melody Output Procedure................................................................. 13-25
13.10 Buzzer............................................................................................................ 13-27
13.10.1 Buzzer Output Procedure ................................................................. 13-28
13.11 Example of Connections Made for Extending the Voice Data Area .............. 13-29
13.12 Example of Connections Made When Using a Piezoelectric Speaker........... 13-30
Chapter 14 Shift Register (SFT)
14.1 Overview........................................................................................................ 14-1
14.2 Shift Register Configuration........................................................................... 14-1
14.3 Shift Registers................................................................................................ 14-2
14.4 Shift Register Operation ................................................................................ 14-4
14.5 Shift Register Application Example................................................................ 14-6
Chapter 15 LCD Driver (LCD)
15.1 Overview........................................................................................................ 15-1
15.2 LCD Driver Configuration............................................................................... 15-1
15.3 LCD Driver Registers..................................................................................... 15-2
15.4 LCD Driver Operation .................................................................................... 15-5
15.5 Bias Generator (BIAS) ................................................................................... 15-6
15.6 LCD Driver Output Waveform........................................................................ 15-9
- v -

- vi -
Chapter 16 Battery Low Detect Circuit (BLD)
16.1 Overview ........................................................................................................ 16-1
16.2 Battery Low Detect Circuit Configuration ....................................................... 16-1
16.3 Judgment Voltage .......................................................................................... 16-2
16.4 Battery Low Detect Circuit Register ............................................................... 16-2
16.5 Battery Low Detect Circuit Operation ............................................................ 16-3
Chapter 17 Power Supply Circuit (POWER)
17.1 Overview ........................................................................................................ 17-1
17.2 Power Supply Circuit Configuration ............................................................... 17-1
17.3 Power Supply Circuit Operation..................................................................... 17-2
Appendixes
Appendix A List of Special Function Registers ............................................Appendix-1
Appendix B Package Dimensions................................................................Appendix-13
Appendix C Input/Output Circuit Configuration ............................................Appendix-14
Appendix D Peripheral Circuit Examples .....................................................Appendix-16
Appendix E Electrical Characteristics ......................................................... Appendix-21
Appendix F Instruction List ..........................................................................Appendix-35
Appendix G Mask Option .............................................................................Appendix-59

1
Chapter 1 Overview
2
Chapter 2 CPU and Memory Spaces
3
Chapter 3 CPU Control Functions
4
Chapter 4 Interrupt (INT326)
5
Chapter 5 Clock Generator Circuit (OSC)
6
Chapter 6 Time Base Counter (TBC)
7
Chapter 7 Timers (TIMER)
8
Chapter 8 100 Hz Timer Counter (100HzTC)
9
Chapter 9 Watchdog Timer (WDT)
10
Chapter 10 Ports (INPUT, OUTPUT, I/O PORT)
14
Chapter 14 Shift Register (SFT)
15
Chapter 15 LCD Driver (LCD)
17
Chapter 17 Power Supply Circuit (POWER)
Appendixes
11
Chapter 11 External Memory Transfer Function (EXTMEM)
12
Chapter 12 Melody Driver (MELODY63K)
13
Chapter 13 Voice Synthesis
16
Chapter 16 Battery Low Detect Circuit (BLD)

Chapter 1
Overview
1

1-1
ML63326 User's Manual
Chapter 1 Overview
1
Chapter 1 Overview
1.1 Overview
The ML63326 is a 4-bit microcontroller with built-in voice synthesis section and 1024-
segment dot matrix LCD driver.
The ML63326 is ideal for applications such as game machines, toys, and clocks, that have
LCD displays and synthesized voice outputs.
The ML63326 is a mask ROM product belonging to the M633xx series of the OLMS-63K
family with Oki's original nX-4/250 CPU core.
TheML63326contains a24K-wordprogrammemory, a1536-nibbledata memory,one4-bit
input port, four 4-bit output ports, five 4-bit and one 2-bit I/O ports, a shift register, an LCD
driver capable of driving a maximum of 1024 segments, and a voice synthesis section.
The voice synthesis section has a 12-bit D/A converter and a low-pass filter.
1.2 Features
The ML63326 has the following features.
a. Extensive instruction set
• 439 instructions
Transfer, rotate, increment/decrement, arithmetic operations, compare, logic
operations, mask operations, bit operations, ROM table reference, external
memory transfer, stack operations, flag operations, jump, conditional branch,
call/return, control
b. Wide variety of addressing modes
• Indirectaddressingmodefor4typesofdatamemorywithcurrentbankregister,
extra bank register, HL register and XY register
• Data memory bank internal direct addressing mode
c. Processing speed
• 2clocks permachine cycle, withmost instructionsexecuted in1 machinecycle
• Minimum instruction execution time: 61 ms (@ 32.768 kHz system clock)
0.976 ms (@ 2.048 MHz system clock)
d. Clock generation circuit
• Low-speed clock:
CrystaloscillationorRCoscillationselectedwithmaskoption(30kHzto80kHz)
• High-speed clock:
Crystal oscillation (4.096 MHz max.) or RC oscillation (2.048 MHz max.)
selectedwithsoftware(Duringthecrystaloscillationmode,thedeviceoperates
outputting the 1/2 frequency waveform of the source oscillation clock.)
e. Program memory space
• 24K words
• The basic instruction length is 16 bits per word.
f. Data memory space
• 1536 nibbles
g. External data memory space
• 64 Kbytes (expandable by using I/O port)

1-2
ML63326 User's Manual
Chapter 1 Overview
h. Stack level Call stack level Register stack level
16 16
i. Ports
• Input ports:
Selectable as input with pull-up resistor, input with pull-down resistor or high
impedance input.
Output ports:
SelectableasP-channelopendrainoutput/N-channelopendrainoutput/CMOS
output/high-impedance output.
• I/O ports:
Selectable as input with pull-up resistor, input with pull-down resistor or high
impedance input.
Selectable as p-channel open drain output, n-channel open drain output, high
impedance output or CMOS output.
• Can be interfaced to external devices having different power supplies.
• Number of ports:
Input port Output ports I/O ports
1 port ¥4 bits 4 ports ¥4 bits 5 ports ¥4 bits
1 port ¥2 bits
j. Voice synthesis section
• Algorithm: 4-bit ADPCM method/non-linear 8-bit PCM method/
straight 8-bit PCM method
• Voice synthesis data area
Internal ROM: 1-Mbit mask ROM (128 Kbytes)
Stores voice data and character data, etc.
External ROM: 4-Mbit ROM (512 Kbytes max.)
• Sampling frequencies
With a source oscillator of 4.096 MHz: 4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.7
kHz, 12.8 kHz, and 16.0 kHz
• Built-in 12-bit D/A converter
• Built-in low-pass filter
• Built-in melody circuit (MELODY)
• Voice output duration
voice output duration = voice ROM capacity/bit rate
= voice ROM capacity/(sampling frequency ×bit length)
<Example>
When algorithm = 4-bit ADPCM method,
voice ROM capacity = 512 Kbits, and
sampling frequency = 4.0 kHz,
then the voice output duration = approx. 32.8 sec.

1-3
ML63326 User's Manual
Chapter 1 Overview
1
o. Timers, counters
• 8-bit timer: 4 channels
Selectable as auto-reload mode, capture mode,
clock frequency measurement mode
• Watchdog timer: 1 channel
• 100 Hz timer: 1 channel
1/100 sec. measurement possible
• 15-bit TBC: 1 channel
1Hz, 2 Hz, 4 Hz, 8 Hz, 16 Hz, 32 Hz, 64 Hz,128Hz signals
can be read
p. Shift register
• Shift clock: System clock ¥1 or ¥1/2, Timer 1 overflow, external clock
• Data length: 8 bits
q. Interrupt factors External factors Internal factors
413
Judgment voltage (V) RemarksLD0LD1
— Undefined00
2.00 ±0.10 Ta = 25°C10
2.20 ±0.10 Ta = 25°C01
2.40 ±0.10 Ta = 25°C11
k. Melody output (MELODY63K)
• Melody frequency: 529 Hz to 2979 Hz
• Tone length: 63 varieties
• Tempo: 15 varieties
• Melody data: Stored in program memory
• Buzzer driver signal output: 4 kHz
l. LCD driver
• Number of segments: 1024 segments max. (64 seg. ¥16 com.)
• 1/1 to 1/16 duty
• 1/4 or 1/5 bias (internal regulator)
• Selectable as all-ON mode, all-OFF mode, power down mode, and normal
display mode
• Adjustable contrast (16 levels @ VDD = 2.4 V or more)
m. System reset function
• System reset by RESET pin
• System reset by power-on detection
• System reset by detection that low-speed clock has stopped oscillation
n. Battery check
• Function that detects battery low voltage
• Selection of judgment voltage by software (LD1 and LD0 bit settings of
BLDCON)

1-4
ML63326 User's Manual
Chapter 1 Overview
r. Shipping products Package Product
• Chip (159 pads) ML63326-xxx
• 176-pin flat package (176LQFP) ML63326-xxxTC
LQFP176-P-2424-0.50-BK xxx indicates the ROM code number.
s. Operating temperature
• –20 to +70°C
t. Power supply voltage
• 2.0 to 5.5 V (30 kHz to 2.048 MHz operating frequency: internal clock)

1-5
ML63326 User's Manual
Chapter 1 Overview
1
1.3 Function List
Table 1-1 shows a list of the ML63326 functions. The solid black circles within the chart
indicate that the product has the particular function.
Table 1-1 Function List
Function Symbol ML63326 Reference page
ROM (¥ 16 bits) ROM 24576 Æ2-7
RAM (¥ 4 bits) RAM 1536 Æ2-8
STACK RAM STACK 16 levels Æ2-5
16 levels Æ2-6
System reset generation circuit RST lÆ3-2
Interrupt INT326 lÆ4-1
Clock generator circuit OSC lÆ5-1
Time base counter TBC lÆ6-1
Timers TIMER lÆ7-1
100 Hz timer counter 100HzTC lÆ8-1
Watchdog timer WDT lÆ9-1
Input port INPUT PORT 1 port ¥4 bits —
P0 lÆ10-2
I/O port I/O PORT 5 ports ¥4 bits —
P9 lÆ10-15
PA l
PB lÆ10-24
PE lÆ10-30
Melody driver MELODY63K lÆ12-1
Shift register SFT lÆ14-1
LCD driver LCD 16 lines Æ15-1
64 lines
Display register (¥ 4 bits) DSPR 256 Æ15-4
Bias generator BIAS lÆ15-6
Battery low detect circuit BLD lÆ16-1
Power supply circuit POWER lÆ17-1
Call
Register
Port 0
Port 9
Port A
Port B
Port E
COM
SEG
1 port ¥2 bits
P8 lPort 8
Voice synthesis VOICE SYNTHESIS lÆ13-1
External memory transfer EXTMEM lÆ11-1
Output port OUTPUT PORT 4 ports ¥4 bits —
P4 l
Æ10-7
Port 4
P5 lPort 5
P6 lPort 6
P7 lPort 7
PF lÆ10-35Port F