Oki ML63326 User manual

ML63326
User's Manual
CMOS 4-bit microcontroller
SECOND EDITION
ISSUE DATE: Sep. 1999
PEUL63326-02
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Preliminary

NOTICE
1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
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9. MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
E2Y0002-29-62

Preface
This manual describes the hardware of Oki's original CMOS 4-bit microcontroller ML63326.
Refer to the "nX-4/250 Core Instruction Manual" for details of the 4-bit CPU core nX-4/250
which is built in the ML63326.
The manuals related to the ML63326 are shown below.
• nX-4/250 Core Instruction Manual:
Describes the base architecture and instruction set of nX-4/250 core.
• SASM63K User's Manual:
Describes the structured assembler operation and assembler language specifica-
tion.
• Dr. 63326 User's Manual:
Describes the hardware of the emulator.
• DT63K Debugger User's Manual:
Describes the debugger commands.
This document is subject to change without notice.

Notation
Classification Notation Description
nNumeric value xxh, xxH Represents a hexadecimal number.
xxb Represents a binary number.
nUnit word, W 1 word = 16 bits
byte, B 1 byte = 2 nibbles = 8 bits
nibble, N 1 nibble = 4 bits
mega-, M 106
kilo-, K 210 = 1024
kilo-, k 103= 1000
milli-, m 10-3
micro-, m10-6
nano-, n 10-9
second, s (lower case) second
KB 1 KB = 1 kilobyte = 1024 bytes
MB 1 MB = 1 megabyte = 220 bytes
= 1,048,576 bytes
nSymbol Note: Gives more information about mistakable items.
nTerminology “H” level Indicates high side voltage signal levels VIH and
VOH as specified by the electrical characteristics.
“L” level Indicates low side voltage signal levels VIL and
VOL as specified by the electrical characteristics.
nRegister description
Invalid bit : When read, a value of “1” is always obtained. Write operations are invalid.
R/W attribute : “R” indicates data can be read and “W” indicates data can be written.
!
Bit name
Invalid bit
Address
R/W attribute
Register name
PBF —PB1MOD PB0MOD
bit 3 bit 2 bit 1 bit 0
PBMOD0 (032H)
(R/W)

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Table of Contents
Chapter 1 Overview
1.1 Overview........................................................................................................ 1-1
1.2 Features......................................................................................................... 1-1
1.3 Function List .................................................................................................. 1-5
1.4 Block Diagram................................................................................................ 1-6
1.5 Pin Configuration ........................................................................................... 1-7
1.6 Pin Descriptions ............................................................................................. 1-11
1.6.1 Descriptions of the Basic Pin Functions ............................................. 1-11
1.6.2 Descriptions of the Secondary Pin Functions..................................... 1-16
1.6.3 Unused Pin Processing ...................................................................... 1-18
1.7 Basic Timing .................................................................................................. 1-19
1.7.1 Basic Timing of CPU Operation.......................................................... 1-19
1.7.2 Port I/O Basic Timing.......................................................................... 1-19
1.7.3 Interrupt Basic Timing......................................................................... 1-21
Chapter 2 CPU and Memory Spaces
2.1 Overview........................................................................................................ 2-1
2.2 Registers........................................................................................................ 2-1
2.2.1 Accumulator (A).................................................................................. 2-1
2.2.2 Flag Register ...................................................................................... 2-1
2.2.2.1 Carry Flag (C)....................................................................... 2-1
2.2.2.2 Zero Flag (Z)......................................................................... 2-2
2.2.2.3 G Flag (G)............................................................................. 2-2
2.2.3 Master Interrupt Enable Flag (MIE) .................................................... 2-2
2.2.4 Current Bank Register (CBR), Extra Bank Register (EBR),
HL Register (HL), XY Register (XY) ................................................... 2-3
2.2.5 Program Counter (PC)........................................................................ 2-4
2.2.6 RA Registers (RA3, RA2, RA1, RA0) ................................................. 2-4
2.2.7 Stack Pointer (SP) and Call Stack...................................................... 2-5
2.2.8 Register Stack Pointer (RSP) and Register Stack.............................. 2-6
2.3 Memory Spaces ............................................................................................. 2-7
2.3.1 Program Memory Space..................................................................... 2-7
2.3.2 Data Memory Space........................................................................... 2-8
2.3.3 Memory Space for Voice Synthesis and Character Data ................... 2-9
2.3.4 External Memory Space ..................................................................... 2-10

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Chapter 3 CPU Control Functions
3.1 Overview ........................................................................................................ 3-1
3.2 System Reset Mode (RST) ............................................................................ 3-2
3.2.1 Transfer to and State of System Reset Mode .................................... 3-2
3.3 Halt Mode ...................................................................................................... 3-3
3.3.1 Transfer to and State of Halt Mode .................................................... 3-3
3.3.2 Halt Mode Release ............................................................................. 3-4
3.3.2.1 Release of Halt Mode by Interrupt........................................ 3-4
3.3.2.2 Release of Halt Mode by RESET Pin ................................... 3-4
3.3.3 Melody Data Interrupt and Halt Mode Release .................................. 3-5
3.3.4 Note Concerning HALT Instruction..................................................... 3-5
Chapter 4 Interrupt (INT326)
4.1 Overview ........................................................................................................ 4-1
4.2 Interrupt Registers ......................................................................................... 4-3
4.3 Interrupt Sequence ........................................................................................ 4-10
4.3.1 Interrupt Processing ........................................................................... 4-10
4.3.2 Return from an Interrupt Routine........................................................ 4-11
4.3.3 Interrupt Hold Instructions .................................................................. 4-11
Chapter 5 Clock Generator Circuit (OSC)
5.1 Overview ........................................................................................................ 5-1
5.2 Clock Generator Circuit Configuration ........................................................... 5-1
5.3 Low-Speed Clock Generator Circuit .............................................................. 5-2
5.4 High-Speed Clock Generator Circuit ............................................................. 5-4
5.5 System Clock Control .................................................................................... 5-6
5.6 Frequency Control Register (FCON) ............................................................. 5-7
5.7 System Clock Select Timing .......................................................................... 5-8
Chapter 6 Time Base Counter (TBC)
6.1 Overview ........................................................................................................ 6-1
6.2 Time Base Counter Configuration ................................................................. 6-1
6.3 Time Base Counter Registers........................................................................ 6-2
6.4 Time Base Counter Operation ....................................................................... 6-3

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Chapter 7 Timers (TIMER)
7.1 Overview........................................................................................................ 7-1
7.2 Timer Configuration ....................................................................................... 7-1
7.3 Timer Registers.............................................................................................. 7-3
7.4 Timer Operation ............................................................................................. 7-14
7.4.1 Timer Clock ........................................................................................ 7-14
7.4.2 Timer Data Registers.......................................................................... 7-14
7.4.3 Timer Counter Registers .................................................................... 7-14
7.4.4 Timer Interrupt Requests and Overflow Flags.................................... 7-15
7.4.5 Auto-Reload Mode Operation............................................................. 7-16
7.4.6 Capture Mode Operation .................................................................... 7-18
7.4.7 Frequency Measurement Mode Operation......................................... 7-21
Chapter 8 100 Hz Timer Counter (100HzTC)
8.1 Overview........................................................................................................ 8-1
8.2 100 Hz Timer Counter Configuration ............................................................. 8-1
8.3 100 Hz Timer Counter Registers ................................................................... 8-2
8.4 100 Hz Timer Counter Operation................................................................... 8-3
Chapter 9 Watchdog Timer (WDT)
9.1 Overview........................................................................................................ 9-1
9.2 Watchdog Timer Configuration ...................................................................... 9-1
9.3 Watchdog Timer Control Register (WDTCON) .............................................. 9-2
9.4 Watchdog Timer Operation............................................................................ 9-2

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Chapter 10 Ports (INPUT, OUTPUT, I/O PORT)
10.1 Overview ........................................................................................................ 10-1
10.2 Ports List ........................................................................................................ 10-1
10.3 Port 0 (P0.0–P0.3) ......................................................................................... 10-2
10.3.1 Port 0 Configuration.......................................................................... 10-2
10.3.2 Port 0 Registers................................................................................ 10-2
10.3.3 Port 0 External Interrupt Functions (External Interrupt 5)................. 10-5
10.4 Ports 4–7 (P4.0–P4.3, P5.0–P5.3, P6.0–P6.3, P7.0–P7.3)........................... 10-7
10.4.1 Port 4–7 Configuration...................................................................... 10-7
10.4.2 Port 4–7 Registers ............................................................................ 10-8
10.5 Port 8, Port 9, Port A (P8.0, P8.1, P9.0–P9.3, PA.0–PA.3) ........................... 10-15
10.5.1 Port 8, Port 9, Port A Configuration .................................................. 10-15
10.5.2 Port 8, Port 9, Port A Registers ........................................................ 10-16
10.6 Port B (PB.0–PB.3) ........................................................................................ 10-24
10.6.1 Port B Configuration ......................................................................... 10-24
10.6.2 Port B Registers ............................................................................... 10-25
10.6.3 Port B External Interrupt Function (External Interrupt 0) .................. 10-29
10.7 Port E (PE.0–PE.3) ........................................................................................ 10-30
10.7.1 Port E Configuration ......................................................................... 10-30
10.7.2 Port E Registers ............................................................................... 10-31
10.7.3 Port E.3 External Interrupt Function (External Interrupt 2) ............... 10-34
10.8 Port F (PF.0–PF.3)......................................................................................... 10-35
10.8.1 Port F Configuration ......................................................................... 10-35
10.8.2 Port F Registers................................................................................ 10-36
10.8.3 Port F External Interrupt Function (External Interrupt 3) .................. 10-40
Chapter 11 External Memory Transfer Function (EXTMEM)
11.1 Overview ........................................................................................................ 11-1
11.2 Connection with the External Memory ........................................................... 11-2
11.3 External Memory Address Space .................................................................. 11-3
11.4 Setting of Secondary Port Functions ............................................................. 11-4
11.5 Distinction between ROM Area inside the Chip and Memory Area External
to the Chip ..................................................................................................... 11-4
11.6 Reading from External Memory ..................................................................... 11-5
11.7 Reading from the Voice ROM inside the Chip ............................................... 11-6
11.8 Writing to External Memory ........................................................................... 11-7
Chapter 12 Melody Driver (MELODY63K)
12.1 Overview ........................................................................................................ 12-1
12.2 Melody Driver Configuration .......................................................................... 12-1
12.3 Melody Driver Registers ................................................................................ 12-2
12.4 Melody Circuit Operation ............................................................................... 12-4
12.4.1 Tempo Data...................................................................................... 12-5
12.4.2 Melody Data ..................................................................................... 12-6
12.4.3 Melody Circuit Application Example ................................................. 12-9
12.5 Buzzer Circuit Operation................................................................................ 12-10
12.6 Melody/Buzzer Output Selector Circuit .......................................................... 12-12
12.7 Differences with Voice Synthesis Section Melody/Buzzer Output ................. 12-13

Chapter 13 Voice Synthesis
13.1 Overview........................................................................................................ 13-1
13.2 Voice Synthesis Section Configuration.......................................................... 13-1
13.3 Registers Related to the Voice Synthesis Section......................................... 13-3
13.4 Voice ROM..................................................................................................... 13-8
13.4.1 Voice ROM Configuration................................................................. 13-8
13.4.2 Creation of Voice ROM Store Data .................................................. 13-9
13.5 Voice Synthesis Section Clock Input Frequency ........................................... 13-10
13.6 Operation of the Voice Synthesis Section...................................................... 13-11
13.6.1 Description of Pins Related to Voice Synthesis................................ 13-11
13.6.2 Phrase Address and Stop Code ....................................................... 13-12
13.7 Voice .............................................................................................................. 13-13
13.7.1 Voice Reproduction Method ............................................................. 13-13
13.7.1.1 4-Bit ADPCM Method ....................................................... 13-13
13.7.1.2 8-Bit Straight PCM Method............................................... 13-13
13.7.1.3 8-Bit Nonlinear PCM......................................................... 13-13
13.7.2 Forcible Stopping of Voice Output.................................................... 13-13
13.7.3 Voice Output Procedure ................................................................... 13-14
13.8 Voice Output Duration.................................................................................... 13-17
13.9 Melody ........................................................................................................... 13-18
13.9.1 Tempo Data...................................................................................... 13-18
13.9.2 Melody Data ..................................................................................... 13-20
13.9.3 Melody Circuit Application Example ................................................. 13-24
13.9.4 Melody Output Procedure................................................................. 13-25
13.10 Buzzer............................................................................................................ 13-27
13.10.1 Buzzer Output Procedure ................................................................. 13-28
13.11 Example of Connections Made for Extending the Voice Data Area .............. 13-29
13.12 Example of Connections Made When Using a Piezoelectric Speaker........... 13-30
Chapter 14 Shift Register (SFT)
14.1 Overview........................................................................................................ 14-1
14.2 Shift Register Configuration........................................................................... 14-1
14.3 Shift Registers................................................................................................ 14-2
14.4 Shift Register Operation ................................................................................ 14-4
14.5 Shift Register Application Example................................................................ 14-6
Chapter 15 LCD Driver (LCD)
15.1 Overview........................................................................................................ 15-1
15.2 LCD Driver Configuration............................................................................... 15-1
15.3 LCD Driver Registers..................................................................................... 15-2
15.4 LCD Driver Operation .................................................................................... 15-5
15.5 Bias Generator (BIAS) ................................................................................... 15-6
15.6 LCD Driver Output Waveform........................................................................ 15-9
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