Oki MSM66591 User manual

MSM66591/ML66592
User's Manual
CMOS 16-bit microcontroller
FEUL66591-66592-01
Issue Date: Mar. 4, 2002

Preface
This document describes the hardware of the 16-bit microcontrollers MSM66591/ML66592
that employ Oki-original CPU core nX-8/500S. Shown below are the related manuals. Refer
to them as required.
■nX-8/500S Core Instruction Manual
• Description of nX-8/500S core instruction set
• Description of addressing modes
■MAC66K Assembler Package User’s Manual
• Package overview
• Description of RAS66K [relocatable assembler] operation
• Description of RAS66K assembly language
• Description of RL66K [linker] operation
• Description of LIB66K [librarian] operation
• Description of OH66K [object converter] operation
■Macroprocessor (MP) User’s Manual
• Description of MP operation
• Description of macro processing language
This document is subject to change without notice.

Notation
Classification Notation Description
n Numeric value xxH Represents a hexadecimal number
xxb Represents a binary number
n Unit Word, W 1 word 16 bits
byte, B 1 byte 2 nibbles 8 bits
nibble, N 1 nibble 4 bits
mega-, M 106
kilo-, K 210 1024
kilo-, k 103 1000
milli-, m 10-3
micro-, m10-6
nano-, n 10-9
second, s second
n Terminology “H” level The signal level of the high side of the
voltage;
indicates the voltage level of VIH and VOH
described in the electrical characteristics.
“L” level The signal level of the low side of the
voltage; indicates voltage level of VIL and
VOL described in the electrical characteristics.
Opcode trap Operation code trap. Occurs when an empty
area that has not been assigned an
instruction is fetched, or when an instruction
code combination that does not contain an
instruction is addressed.
n Register description
7
—
6
SCNC0
5
SNEX0
4
ADRUN0
3
"0"
2 1
ADSNM02 ADSNM01ADSNM00
0
ADCON0L
Register na e Invalid bit Bit na e Bit nu ber
Fixed bit
Invalid bit : Indicates that the bit does not exist. Writing into this bit is invalid.
Fixed bit : When writing, always write the specified value. If read, the specified
value will be read. Values of fixed bits are specified as “0” or “1”.

Contents-1
Contents
Chapter 1 Overview
1.1 Features.........................................................................................................1-2
1.2 Block Diagram ...............................................................................................1-4
1.3 Pin Configuration ...........................................................................................1-5
1.4 Basic Operation Timing .................................................................................1-6
Chapter 2 Description of Pins
2.1 P0_0–P0_7: Input/Output Pins ......................................................................2-1
2.2 P1_0–P1_7: Input/Output Pins ......................................................................2-1
2.3 P2_0–P2_7: Input/Output Pins ......................................................................2-1
2.4 P3_0–P3_7: Input/Output Pins ......................................................................2-2
2.5 P4_0–P4_7: Input/Output Pins ......................................................................2-3
2.6 P5_0–P5_7: Input/Output Pins ......................................................................2-3
2.7 P6_0–P6_7: Input/Output Pins ......................................................................2-4
2.8 P7_0–P7_7: Input/Output Pins ......................................................................2-5
2.9 P8_0–P8_7: Input/Output Pins ......................................................................2-6
2.10 P9_0–P9_7: Input/Output Pins ......................................................................2-6
2.11 P10_0–P10_7: Input/Output Pins ..................................................................2-7
2.12 P11_0–P11_7: Input/Output Pins ..................................................................2-8
2.13 P12_0, P12_1: Input/Output Pins ..................................................................2-9
2.14 AI0–AI23: Input Pins ......................................................................................2-9
2.15 AVDD: Input Pin..............................................................................................2-9
2.16 VREF: Input Pin ..............................................................................................2-9
2.17 AGND: Input Pin ............................................................................................2-9
2.18 OSC0, OSC1: Input Pin, Output Pin ..............................................................2-9
2.19 OE: Input Pin..................................................................................................2-9
2.20 NMI: Input Pin ................................................................................................2-9
2.21 RES: Input Pin................................................................................................2-9
2.22 EA: Input Pin ................................................................................................2-10
2.23 TEST: Input Pin ...........................................................................................2-10
2.24 VDD: Input Pin ..............................................................................................2-10
2.25 GND: Input Pin.............................................................................................2-10
2.26 Structure of Pins ..........................................................................................2-10
2.27 Handling of Unused Pins .............................................................................2-12

Contents-2
Chapter 3 CPU Architecture
3.1 Memory Space...............................................................................................3-1
3.1.1 Memory Space Expansion..........................................................................3-1
3.1.2 Program Memory Space.............................................................................3-2
[1] Accessing Program Memory Space ...........................................................3-4
[2] Vector Table Area.......................................................................................3-4
[3] VCAL Table Area........................................................................................3-6
[4] ACAL Area..................................................................................................3-7
3.1.3 Data Memory Space ...................................................................................3-8
[1] Special Function Register (SFR) Area........................................................3-9
[2] Expanded Special Function Register (Expanded SFR) Area .....................3-9
[3] Internal RAM Area ......................................................................................3-9
[4] Fixed Page (FIX) Area ..............................................................................3-10
[5] Local Register Setting Area ......................................................................3-11
[6] ROM Window Setting Area.......................................................................3-11
3.1.4 Data Memory Access................................................................................3-12
[1] Byte Operation..........................................................................................3-12
[2] Word Operation ........................................................................................3-12
3.2 Registers......................................................................................................3-13
3.2.1 Arithmetic Register (ACC) ........................................................................3-13
3.2.2 Control Register........................................................................................3-14
[1] Program Status Word (PSW)....................................................................3-14
[2] Program Counter (PC)..............................................................................3-17
[3] Local Register Base (LRB) .......................................................................3-17
[4] System Stack Pointer (SSP).....................................................................3-18
3.2.3 Pointing Register (PR) ..............................................................................3-19
3.2.4 Local Registers (R, ER) ............................................................................3-20
3.2.5 Segment Register .....................................................................................3-21
[1] Code Segment Register (CSR) ................................................................3-21
[2] Table Segment Register (TSR) ................................................................3-22
3.2.6 Special Function Register (SFR) ..............................................................3-23
3.3 Addressing Mode.........................................................................................3-37
3.3.1 RAM Addressing.......................................................................................3-37
[1] Register Addressing .................................................................................3-37
[2] Page Addressing ......................................................................................3-40
[3] Direct Data Addressing.............................................................................3-43
[4] Pointing Register Indirect Addressing.......................................................3-44
[5] Special Bit Area Addressing .....................................................................3-50

Contents-3
3.3.2 ROM Addressing ......................................................................................3-51
[1] Immediate Addressing ..............................................................................3-51
[2] Table Data Addressing .............................................................................3-51
[3] Program Code Addressing .......................................................................3-53
[4] ROM Window Addressing.........................................................................3-55
Chapter 4 CPU Control Functions
4.1 Standby Function...........................................................................................4-1
4.1.1 Standby Control Register (SBYCON).........................................................4-3
4.1.2 Operation in Each Standby Mode...............................................................4-4
[1] HALT Mode.................................................................................................4-4
[2] STOP Mode ................................................................................................4-5
4.2 Reset Function...............................................................................................4-6
Chapter 5 Memory Control Functions
5.1 ROM Window Function..................................................................................5-1
5.2 READY Function............................................................................................5-3
Chapter 6 Port Functions
6.1 Hardware Configuration of Each Port ............................................................6-1
6.1.1 Configuration of Type A (P0_0–P0_7, P1_0–P1_7, P12_0).......................6-4
6.1.2 Configuration of Type B
(P2_0–P2_7, P3_0–P3_3, P7_4–P7_7, P8_0–P8_7, P10_0–P10_4) .......6-5
6.1.3 Configuration of Type C
(P3_4–P3_7, P4_0–P4_7, P5_0–P5_7, P6_0–P6_7, P7_2, P7_3,
P9_0–P9_7, P10_5–P10_7, P11_0–P11_3) ..............................................6-6
6.1.4 Configuration of Type D (P7_0, P7_1, P11_4–P11_7)...............................6-7
6.1.5 Configuration of Type E (P12_1) ................................................................6-7
6.2 Port Control Registers ...................................................................................6-8
6.2.1 Port Data Register (Pn: n = 0–12) .............................................................6-8
6.2.2 Port Mode Register (PnIO: n = 0–12) ........................................................6-8
6.2.3 Port Secondary Function Control Register (PnSF: n = 2–10)....................6-8
6.3 Port 0 (P0) ...................................................................................................6-11
6.4 Port 1 (P1) ...................................................................................................6-12
6.5 Port 2 (P2) ...................................................................................................6-13
6.6 Port 3 (P3) ...................................................................................................6-15
6.7 Port 4 (P4) ...................................................................................................6-17

Contents-4
6.8 Port 5 (P5) ...................................................................................................6-19
6.9 Port 6 (P6) ...................................................................................................6-21
6.10 Port 7 (P7) ...................................................................................................6-23
6.11 Port 8 (P8) ...................................................................................................6-25
6.12 Port 9 (P9) ...................................................................................................6-27
6.13 Port 10 (P10) ...............................................................................................6-29
6.14 Port 11 (P11) ...............................................................................................6-31
6.15 Port 12 (P12) ...............................................................................................6-32
Chapter 7 Output Pin Control Pin (OE)
Chapter 8 Clock Generation Circuit
Chapter 9 Time Base Counter (TBC)
9.1 1/n Counter ....................................................................................................9-2
Chapter 10 Watchdog Timer (WDT)
10.1 WDT Control Register (WDTCON) ..............................................................10-1
10.2 Operation of WDT........................................................................................10-1
10.3 Time until Overflow of WDT.........................................................................10-2
10.4 Program Runaway Detection Timing Diagram ............................................10-2
Chapter 11 Flexible Timer (FTM)
11.1 Configuration of Counter Part ......................................................................11-6
11.2 Counter Selection Part.................................................................................11-8
11.3 Type A1 Register Modules (TMR0–TMR3) ...............................................11-10
11.3.1 Configuration of Type A1 Register Modules (TMR0–TMR3) ................11-10
[1] Timer Registers (TMR0, TMR0L–TMR3, TMR3L)..................................11-10
[2] Capture Control Register (CAPCON) .....................................................11-11
[3] Event Control Registers (EVNTCONL, EVNTCONH).............................11-12
[4] Event Dividing Counters 0–3 (EVDV0–EVDV3) .....................................11-14
[5] EVDV0–EVDV3 Buffer Registers (EVDV0BF–EVDV3BF) .....................11-14
11.3.2 Operation of Type A1 Register Modules (TMR0–TMR3) .....................11-15
11.3.3 Capture Pin Dividing Circuit..................................................................11-16
[1] Configuration of Dividing Circuit .............................................................11-16
[2] Operation of Dividing Circuit ...................................................................11-16
[3] Operation to Switch Dividing Ratio .........................................................11-16

Contents-5
11.4 Type A2 Register Modules (TMR14, TMR15) ...........................................11-17
11.4.1 Configuration of Type A2 Register Modules (TMR14, TMR15) ............11-17
[1] Timer Registers (TMR14, TMR15) .........................................................11-17
[2] Capture Control Register (CAPCON) .....................................................11-18
[3] Event Control Register 2 (EVNTCON2)..................................................11-19
[4] Event Dividing Counters 14, 15 (EVDV14, EVDV15) .............................11-20
[5] EVDV14, EVDV15 Buffer Registers (EVDV14BF, EVDV15BF) .............11-20
11.4.2 Operation of Type A2 Register Modules (TMR14, TMR15) .................11-21
11.4.3 Capture Pin Dividing Circuit..................................................................11-22
[1] Configuration of Dividing Circuit .............................................................11-22
[2] Operation of Dividing Circuit ...................................................................11-22
[3] Operation to Switch Dividing Ratio .........................................................11-22
11.5 Type B Register Modules (TMR4–TMR13) ...............................................11-23
11.5.1 Configuration of Type B Register Modules (TMR4–TMR13) ................11-23
[1] Timer Registers (TMR4–TMR13) ...........................................................11-24
[2] Timer Register Buffer Registers (TMR4BF–TMR13BF) .........................11-24
[3] Real-time Output Control Registers (RTOCON4–RTOCON13) .............11-24
11.5.2 Operation of Type B Register Modules (TMR4–TMR13) .......................11-26
11.6 Type D Register Module (TMR17).............................................................11-27
11.6.1 Configuration of Type D Register Module (TMR17) .............................11-27
[1] Timer Register (TMR17) .........................................................................11-29
[2] Real-time Output Control Registers (RTOCON17, RTO4CON) .............11-29
[3] TMR Mode Register (TMRMODE)..........................................................11-31
[4] Capture Control Register (CAPCON) .....................................................11-32
11.6.2 Operation of Type D Register Module (TMR17) ...................................11-33
[1] Operation in Real-time Output Mode (RTO) ...........................................11-33
[2] Operation in 4-Port Output Real-time Output Mode (4-Port RTO)..........11-34
[3] Operation in CAP Mode..........................................................................11-35
11.7 Type E Register Module (TMR16) .............................................................11-36
11.7.1 Configuration of Type E Register Module (TMR16)..............................11-36
[1] Timer Register (TMR16) .........................................................................11-37
[2] Real-time Output Control Register (RTOCON16)...................................11-37
[3] TMR Mode Register (TMRMODE)..........................................................11-38
[4] Capture Control Register (CAPCON) .....................................................11-39
11.7.2 Operation of Type E Register Module (TMR16) ...................................11-40
[1] Operation in Real-time Output Mode (RTO) ...........................................11-40
[2] Operation in CAP Mode..........................................................................11-40
11.8 RTO Mode Output Timing Changes ..........................................................11-41

Contents-6
Chapter 12 General-Purpose 8-Bit Timer Function
12.1 General-Purpose 8-Bit Timer (GTM) ...........................................................12-2
[1] General-Purpose 8-Bit Timer Counter (GTMC) ........................................12-3
[2] General-Purpose 8-Bit Timer Register (GTMR) .......................................12-3
[3] General-Purpose 8-Bit Timer Control Register (GTMCON) .....................12-3
[4] General-Purpose 8-Bit Timer Interrupt Control Register (GTINTCON) ....12-5
12.2 General-Purpose 8-Bit Event Counter (GEVC) ...........................................12-6
[1] General-Purpose 8-Bit Event Counter (GEVC) ........................................12-6
[2] General-Purpose 8-Bit Timer Control Register (GTMCON) .....................12-6
[3] General-Purpose 8-Bit Timer Interrupt Control Register (GTINTCON) ....12-7
Chapter 13 PWM Functions
13.1 Configuration of PWM..................................................................................13-4
[1] PWM Counters (PWC0–PWC11) .............................................................13-4
[2] PWM Counter Buffer Registers (PWC0BF–PWC11BF) ...........................13-4
[3] PWM Registers (PWR0–PWR11).............................................................13-5
[4] PWM Buffer Registers (PW0BF–PW11BF) ..............................................13-5
[5] Comparison Circuit ...................................................................................13-5
[6] Output F/F.................................................................................................13-5
[7] PWM Control Registers (PWCON0–PWCON5) .......................................13-5
[8] PWMRUN Register (PWRUN)..................................................................13-9
[9] PWM Interrupt Registers (PWINTQ0, PWINTQ1) ..................................13-10
[10] PWM Interrupt Enable Registers (PWINTE0, PWINTE1).......................13-13
13.2 Operation of PWM .....................................................................................13-16
Chapter 14 Baud Rate Generator Functions
14.1 Configuration of SCI0 Timer (S0TM) ...........................................................14-3
[1] SCI0 Timer Counter..................................................................................14-3
[2] SCI0 Timer Register .................................................................................14-3
[3] SCI0 Timer Control Register (S0CON).....................................................14-3
14.2 Operation of SCI0 Timer..............................................................................14-5
14.3 Configuration of SCI1 Timer (S1TM) ...........................................................14-6
[1] SCI1 Timer Counter..................................................................................14-6
[2] SCI1 Timer Register .................................................................................14-6
[3] SCI1 Timer Control Register (S1CON).....................................................14-6
14.4 Operation of SCI1 Timer..............................................................................14-8

Contents-7
14.5 Configuration of SCI2 Timer (S2TM) ...........................................................14-9
[1] SCI2 Timer Counter..................................................................................14-9
[2] SCI2 Timer Register .................................................................................14-9
[3] SCI2 Timer Control Register (S2CON).....................................................14-9
14.6 Operation of SCI2 Timer............................................................................14-11
14.7 Configuration of SCI3 Timer (S3TM) .........................................................14-12
[1] SCI3 Timer Counter................................................................................14-12
[2] SCI3 Timer Register ...............................................................................14-12
[3] SCI3 Timer Control Register (S3CON)...................................................14-12
14.8 Operation of SCI3 Timer............................................................................14-14
14.9 Configuration of SCI4 Timer (S4TM) .........................................................14-15
[1] SCI4 Timer Counter................................................................................14-15
[2] SCI4 Timer Register ...............................................................................14-15
[3] SCI4 Timer Control Register (S4CON)...................................................14-15
14.10 Operation of SCI4 Timer............................................................................14-17
Chapter 15 Serial Port Functions
15.1 Configuration of Serial Ports........................................................................15-2
15.2 Serial Port Control Registers .......................................................................15-5
15.2.1 Control Registers for SCI0......................................................................15-5
[1] SCI0 Transmit Control Register (ST0CON)..............................................15-5
[2] SCI0 Receive Control Register (SR0CON) ..............................................15-7
[3] SCI0 Transmit/Receive Buffer Register (S0BUF0)...................................15-9
[4] SCI0 Receive Buffer Registers (S0BUF1, S0BUF2, S0BUF3).................15-9
[5] SCI0 Transmit and Receive Registers......................................................15-9
[6] SCI0 Status Register 0 (S0STAT0) ........................................................15-10
[7] SCI0 Status Register 1 (S0STAT1) ........................................................15-13
[8] SCI0 Status Register 2 (S0STAT2) ........................................................15-15
[9] SCI0 Interrupt Control Register (SR0INT) ..............................................15-17
15.2.2 Control Registers for SCI1....................................................................15-19
[1] SCI1 Transmit Control Register (ST1CON)............................................15-19
[2] SCI1 Receive Control Register (SR1CON) ............................................15-21
[3] SCI1 Transmit/Receive Buffer Register (S1BUF)...................................15-23
[4] SCI1 Transmit and Receive Registers....................................................15-23
[5] SCI1 Status Register (S1STAT) .............................................................15-23

Contents-8
15.2.3 Control Registers for SCI2....................................................................15-26
[1] SCI2 Transmit Control Register (ST2CON)............................................15-26
[2] SCI2 Receive Control Register (SR2CON) ............................................15-28
[3] SCI2 Transmit/Receive Buffer Register (S2BUF0).................................15-30
[4] SCI2 Receive Buffer Registers (S2BUF1, S2BUF2, S2BUF3)...............15-30
[5] SCI2 Transmit and Receive Registers....................................................15-30
[6] SCI2 Status Register 0 (S2STAT0) ........................................................15-31
[7] SCI2 Status Register 1 (S2STAT1) ........................................................15-34
[8] SCI2 Status Register 2 (S2STAT2) ........................................................15-36
[9] SCI2 Interrupt Control Register (SR2INT) ..............................................15-38
15.2.4 Control Registers for SCI3....................................................................15-40
[1] SCI3 Transmit Control Register (ST3CON)............................................15-40
[2] SCI3 Receive Control Register (SR3CON) ............................................15-42
[3] SCI3 Transmit/Receive Buffer Register (S3BUF0).................................15-44
[4] SCI3 Receive Buffer Registers (S3BUF1, S3BUF2, S3BUF3)...............15-44
[5] SCI3 Transmit and Receive Registers....................................................15-44
[6] SCI3 Status Register 0 (S3STAT0) ........................................................15-45
[7] SCI3 Status Register 1 (S3STAT1) ........................................................15-48
[8] SCI3 Status Register 2 (S3STAT2) ........................................................15-50
[9] SCI3 Interrupt Control Register (SR3INT) ..............................................15-52
15.2.5 Control Registers for SCI4....................................................................15-54
[1] SCI4 Transmit Control Register (ST4CON)............................................15-54
[2] SCI4 Receive Control Register (SR4CON) ............................................15-56
[3] SCI4 Transmit/Receive Buffer Register (S4BUF0).................................15-58
[4] SCI4 Receive Buffer Registers (S4BUF1, S4BUF2, S4BUF3)...............15-58
[5] SCI4 Transmit and Receive Registers....................................................15-58
[6] SCI4 Status Register 0 (S4STAT0) ........................................................15-59
[7] SCI4 Status Register 1 (S4STAT1) ........................................................15-62
[8] SCI4 Status Register 2 (S4STAT2) ........................................................15-64
[9] SCI4 Interrupt Control Register (SR4INT) ..............................................15-66
15.3 Operation of Serial Ports ...........................................................................15-68
15.3.1 Transmit Operation ...............................................................................15-68
15.3.2 Receive Operation ................................................................................15-74
[1] Single Buffer Mode .................................................................................15-74
[2] 4-Stage Buffer Mode...............................................................................15-81

Contents-9
Chapter 16 A/D Converter Functions
16.1 Configuration of A/D Converter....................................................................16-4
[1] Scan Mode................................................................................................16-4
[2] Select Mode..............................................................................................16-4
[3] Hard Select Mode .....................................................................................16-4
16.2 Control Register of A/D Converter ...............................................................16-7
[1] A/D Control Register 0L (ADCON0L) .......................................................16-7
[2] A/D Control Register 1L (ADCON1L) .......................................................16-9
[3] A/D Control Register 0H (ADCON0H) ....................................................16-11
[4] A/D Control Register 1H (ADCON1H) ....................................................16-13
[5] A/D Interrupt Control Register 0 (ADINTCON0) .....................................16-15
[6] A/D Interrupt Control Register 1 (ADINTCON1) .....................................16-17
[7] A/D Hard Select Register 0 (ADHSEL0).................................................16-19
[8] A/D Hard Select Register 1 (ADHSEL1).................................................16-22
[9] A/D Hard Select Software-Control Register (ADHSCON) ......................16-25
[10] A/D Hard Select Enable Register (ADHENCON) ...................................16-26
[11] A/D Result Registers (ADCR0–ADCR23)...............................................16-28
16.3 Generated Timing of the A/D Hard Select Mode .......................................16-29
Chapter 17 Transition Detector Functions
17.1 Transition Detector Control Register (TRNSCON) ......................................17-1
17.2 Transition Detector Register (TRNSIT)........................................................17-3
Chapter 18 Peripheral Functions
18.1 Clockout Function ........................................................................................18-1
18.2 RES Pin Valid Level Detection Function ......................................................18-1
18.3 OE Pin Monitor Function..............................................................................18-1
Chapter 19 External Interrupt Request Function

Contents-10
Chapter 20 Interrupt Request Processing Function
20.1 Non-maskable Interrupt (NMI) .....................................................................20-2
20.2 Maskable Interrupt .......................................................................................20-4
[1] Interrupt Request Flag Disable Register IRQD
(IRQD0L, IRQD0H, IRQD1L, IRQD1H, IRQD2L) ...........................20-6
[2] Interrupt Request Register IRQ (IRQ0L, IRQ0H, IRQ1L, IRQ1H, IRQ2L) ...20-6
[3] Interrupt Enable Register IE (IE0L, IE0H, IE1L, IE1H, IE2L)....................20-6
[4] Master Interrupt Enable Flag (MIE) ..........................................................20-6
[5] Master Interrupt Priority Flag (MIPF) ........................................................20-6
[6] Interrupt Priority Control Register
IPX0 (IP00L, IP00H, IP10L, IP10H, IP20L),
IPX1 (IP01L, IP01H, IP11L, IP11H, IP21L) ....................................20-7
20.3 Operation of Maskable Interrupt ..................................................................20-8
Chapter 21 Bus Port Functions
21.1 Bus Port (P0, P1, P12_0, P12_1) Functions ...............................................21-1
21.1.1 Operation of P0, P1, P12_0 and P12_1 During a Program Memory
Access ....................................................................................................21-1
21.2 External Memory Access .............................................................................21-2
21.2.1 External Program Memory Access .........................................................21-2
21.2.2 External Program Memory Access Timing .............................................21-2
Chapter 22 Expansion Port
22.1 Expansion Port Configuration ......................................................................22-1
22.2 Expansion Port Control Register (EXTPCON).............................................22-2
22.3 Expansion Port Register (EXTPD)...............................................................22-3
22.4 Expansion Port Operation............................................................................22-3
[1] Input Mode................................................................................................22-3
[2] Output Mode .............................................................................................22-4

Contents-11
Chapter 23 Serial Port with FIFO (SCI5)
23.1 SCI5 Configuration ......................................................................................23-1
23.2 SCI5 Control Register 0 (SCI5CON0) .........................................................23-2
23.3 SCI5 Control Register 1 (SCI5CON1) .........................................................23-4
23.4 SCI5 Interrupt Register (SCI5INT)...............................................................23-5
23.5 Serial Address Output Register (SFADR)....................................................23-6
23.6 Serial Data Input Register (SFDIN) .............................................................23-7
23.7 Serial Data Output Register (SFDOUT).......................................................23-7
23.8 SCI5 Operation ............................................................................................23-8
Chapter 24 RAM Monitor Function
24.1 Configuration of RAM Monitor Function.......................................................24-1
24.2 Configuration of Serial Transfer Data ..........................................................24-3
24.3 RAM Monitor Function Operation ................................................................24-5
[1] Setting the addresses ...............................................................................24-5
[2] Detection of address matching .................................................................24-5
[3] Reading data ............................................................................................24-5
Chapter 25 Electrical Characteristics
[MSM66591 Electrical Characteristics] ...............................................................25-1
25.1 Absolute Maximum Ratings .........................................................................25-1
25.2 Operating Range .........................................................................................25-2
25.3 DC Characteristics.......................................................................................25-3
25.4 AC Characteristics .......................................................................................25-5
[1] External Program Memory Control ...........................................................25-5
25.5 A/D Converter Characteristics .....................................................................25-6
[ML66592 Electrical Characteristics] ..................................................................25-8
25.6 Absolute Maximum Ratings .........................................................................25-8
25.7 Operating Range .........................................................................................25-9
25.8 DC Characteristics.....................................................................................25-10
25.9 AC Characteristics (Preliminary)................................................................25-12
[1] External Program Memory Control .........................................................25-12
25.10 A/D Converter Characteristics ...................................................................25-13
Chapter 26 Package Dimensions
Chapter 27 Revision History

Contents-12

1
Chapter 1 Overview
2
Chapter 2 Description of Pins
3
Chapter 3 CPU Architecture
4
Chapter 4 CPU Control Functions
5
Chapter 5 Memory Control Functions
6
Chapter 6 Port Functions
7
Chapter 7 Output Pin Control Pin (OE)
8
Chapter 8 Clock Generation Circuit
9
Chapter 9 Time Base Counter (TBC)
10
Chapter 10 Watchdog Timer (WDT)
11
Chapter 11 Flexible Timer (FTM)
12
Chapter 12 General-Purpose 8-Bit Timer Function
13
Chapter 13 PWM Functions
14
Chapter 14 Baud Rate Generator Functions
15
Chapter 15 Serial Port Functions
16
Chapter 16 A/D Converter Functions
17
Chapter 17 Transition Detector Functions
18
Chapter 18 Peripheral Functions
19
Chapter 19 External Interrupt Request Function
20
Chapter 20 Interrupt Request Processing Function
21
Chapter 21 Bus Port Functions
22
Chapter 22 Expansion Port
23
Chapter 23 Serial Port with FIFO (SCI5)
24
Chapter 24 RAM Monitor Function
25
Chapter 25 Electrical Characteristics
26
Chapter 26 Package Dimensions
27
Chapter 27 Revision History

Overview
Chapter 1
1

1-1
MSM66591/ML66592 User's Manual
Chapter 1 Overview
1
1. Overview
The MSM66591/ML66592 are high performance 16-bit microcontrollers that contain a 16-bit
CPU (nX-8/500S), ROM, RAM, a 10-bit A/D converter, serial ports, flexible timers, and
PWMs.
The ML66592 is the same as the MSM66591 with the exception that the ML66592 has an
increased ROM and RAM capacity and a higher operating speed. Table 1-1 lists the func-
tional differences between the MSM66591 and ML66592.
The MSM66Q591 is a Flash EEPROM version of the MSM66591. The ML66Q592 is a Flash
EEPROM version of the ML66592.
Modifications in
ML66592/ML66Q592 and notes
Operating frequency
(internal)
Increased by MHz (with
increased supply current)
20 to 2 MHz 20 to 28 MHz
Program memory space
Operating temperature – 0 to +115°C – 0 to +95°C Changed from +115°C to +95°C
Increased by 6 K bytes
(internal) (SEG2)
Increased by 128K bytes
(external) (SEG2, 3)
External A17 output (P12_1)
has been added.
(When EA = "L")
192K bytes (internal)
256K bytes (external)
0:0000H to 3:FFFFH
128K bytes
0:0000H to 1:FFFFH
6K bytes
200H to 19FFH
8K bytes
200H to 21FFH
6K bytes
200H to 19FFH
8K bytes
0200H to 21FFH
192K bytes
0:0000H to 2:FFFFH
128K bytes
0:0000H to 1:FFFFH
Increased by 2K bytes
(1A00H to 21FFH)
Increased by 2K bytes
(1A00H to 21FFH)
…Changed from 2000H to 3000H
Increased by 6 K bytes (SEG2)
One valid bit has been added
to each of CSR and TSR.
Access forbidden to the
internal SEG3.
2000H
000H
8000H
1/2 CLK (12 MHz)
1/ CLK (6 MHz)
1/8 CLK (3 MHz)
1/16 CLK (1.5 MHz)
2/3 CLK (16 MHz)
1/3 CLK (8 MHz)
512 CLK (21.3 µs)
38 CLK (16 µs)
256 CLK (10.7 µs)
1/ CLK (6 MHz*)
1/8 CLK (3 MHz)
1/16 CLK (1.5 MHz)
512 CLK (18.3 µs)
38 CLK (13.7µs)
256 CLK (9.1 µs)
Not provided
1/8 CLK (3.5 MHz)
1/16 CLK (1.75 MHz)
1/2 CLK (1 MHz)
1/ CLK (7 MHz)
1/8 CLK (3.5 MHz)
1/16 CLK (1.75 MHz)
2/3 CLK (forbidden)
1/3 CLK (9.3 MHz)
3000H
000H
8000H
…Use of 2/3 CLK is forbidden.
ML66592/66Q592MSM66591/66Q591Item
Data memory space
Internal ROM capacity
Internal RAM capacity
Starting address for the
ROM Window function
CLKOUT function
(Values in parentheses are
output frequencies of the
device operating at the
maximum frequency)
(Values in parentheses are
conversion time when the
device is operating at the
maximum frequency)
Transfer clock during
Flash ROM reprogramming
in the user mode
(MSM66Q591/ML66Q592 only)
…Should be used at 16 ms or more
…1/ CLK has been deleted.
10-bit A/D converter
conversion time
* 6 MHz is outside the guarantee
range.
Note: In the ML66592/66Q592, the AC characteristics during external program memory access apply
only when the internal operating frequency is not more than 24 MHz.
Table 1-1 Di erences between MSM66591/66Q591 and ML66592/66Q592 Speci ications