Oki MSM66591 User manual

MSM66591/ML66592
User's Manual
CMOS 16-bit microcontroller
FEUL66591-66592-01
Issue Date: Mar. 4, 2002

Preface
This document describes the hardware of the 16-bit microcontrollers MSM66591/ML66592
that employ Oki-original CPU core nX-8/500S. Shown below are the related manuals. Refer
to them as required.
■nX-8/500S Core Instruction Manual
• Description of nX-8/500S core instruction set
• Description of addressing modes
■MAC66K Assembler Package User’s Manual
• Package overview
• Description of RAS66K [relocatable assembler] operation
• Description of RAS66K assembly language
• Description of RL66K [linker] operation
• Description of LIB66K [librarian] operation
• Description of OH66K [object converter] operation
■Macroprocessor (MP) User’s Manual
• Description of MP operation
• Description of macro processing language
This document is subject to change without notice.

Notation
Classification Notation Description
n Numeric value xxH Represents a hexadecimal number
xxb Represents a binary number
n Unit Word, W 1 word 16 bits
byte, B 1 byte 2 nibbles 8 bits
nibble, N 1 nibble 4 bits
mega-, M 106
kilo-, K 210 1024
kilo-, k 103 1000
milli-, m 10-3
micro-, m10-6
nano-, n 10-9
second, s second
n Terminology “H” level The signal level of the high side of the
voltage;
indicates the voltage level of VIH and VOH
described in the electrical characteristics.
“L” level The signal level of the low side of the
voltage; indicates voltage level of VIL and
VOL described in the electrical characteristics.
Opcode trap Operation code trap. Occurs when an empty
area that has not been assigned an
instruction is fetched, or when an instruction
code combination that does not contain an
instruction is addressed.
n Register description
7
—
6
SCNC0
5
SNEX0
4
ADRUN0
3
"0"
2 1
ADSNM02 ADSNM01ADSNM00
0
ADCON0L
Register na e Invalid bit Bit na e Bit nu ber
Fixed bit
Invalid bit : Indicates that the bit does not exist. Writing into this bit is invalid.
Fixed bit : When writing, always write the specified value. If read, the specified
value will be read. Values of fixed bits are specified as “0” or “1”.

Contents-1
Contents
Chapter 1 Overview
1.1 Features.........................................................................................................1-2
1.2 Block Diagram ...............................................................................................1-4
1.3 Pin Configuration ...........................................................................................1-5
1.4 Basic Operation Timing .................................................................................1-6
Chapter 2 Description of Pins
2.1 P0_0–P0_7: Input/Output Pins ......................................................................2-1
2.2 P1_0–P1_7: Input/Output Pins ......................................................................2-1
2.3 P2_0–P2_7: Input/Output Pins ......................................................................2-1
2.4 P3_0–P3_7: Input/Output Pins ......................................................................2-2
2.5 P4_0–P4_7: Input/Output Pins ......................................................................2-3
2.6 P5_0–P5_7: Input/Output Pins ......................................................................2-3
2.7 P6_0–P6_7: Input/Output Pins ......................................................................2-4
2.8 P7_0–P7_7: Input/Output Pins ......................................................................2-5
2.9 P8_0–P8_7: Input/Output Pins ......................................................................2-6
2.10 P9_0–P9_7: Input/Output Pins ......................................................................2-6
2.11 P10_0–P10_7: Input/Output Pins ..................................................................2-7
2.12 P11_0–P11_7: Input/Output Pins ..................................................................2-8
2.13 P12_0, P12_1: Input/Output Pins ..................................................................2-9
2.14 AI0–AI23: Input Pins ......................................................................................2-9
2.15 AVDD: Input Pin..............................................................................................2-9
2.16 VREF: Input Pin ..............................................................................................2-9
2.17 AGND: Input Pin ............................................................................................2-9
2.18 OSC0, OSC1: Input Pin, Output Pin ..............................................................2-9
2.19 OE: Input Pin..................................................................................................2-9
2.20 NMI: Input Pin ................................................................................................2-9
2.21 RES: Input Pin................................................................................................2-9
2.22 EA: Input Pin ................................................................................................2-10
2.23 TEST: Input Pin ...........................................................................................2-10
2.24 VDD: Input Pin ..............................................................................................2-10
2.25 GND: Input Pin.............................................................................................2-10
2.26 Structure of Pins ..........................................................................................2-10
2.27 Handling of Unused Pins .............................................................................2-12

Contents-2
Chapter 3 CPU Architecture
3.1 Memory Space...............................................................................................3-1
3.1.1 Memory Space Expansion..........................................................................3-1
3.1.2 Program Memory Space.............................................................................3-2
[1] Accessing Program Memory Space ...........................................................3-4
[2] Vector Table Area.......................................................................................3-4
[3] VCAL Table Area........................................................................................3-6
[4] ACAL Area..................................................................................................3-7
3.1.3 Data Memory Space ...................................................................................3-8
[1] Special Function Register (SFR) Area........................................................3-9
[2] Expanded Special Function Register (Expanded SFR) Area .....................3-9
[3] Internal RAM Area ......................................................................................3-9
[4] Fixed Page (FIX) Area ..............................................................................3-10
[5] Local Register Setting Area ......................................................................3-11
[6] ROM Window Setting Area.......................................................................3-11
3.1.4 Data Memory Access................................................................................3-12
[1] Byte Operation..........................................................................................3-12
[2] Word Operation ........................................................................................3-12
3.2 Registers......................................................................................................3-13
3.2.1 Arithmetic Register (ACC) ........................................................................3-13
3.2.2 Control Register........................................................................................3-14
[1] Program Status Word (PSW)....................................................................3-14
[2] Program Counter (PC)..............................................................................3-17
[3] Local Register Base (LRB) .......................................................................3-17
[4] System Stack Pointer (SSP).....................................................................3-18
3.2.3 Pointing Register (PR) ..............................................................................3-19
3.2.4 Local Registers (R, ER) ............................................................................3-20
3.2.5 Segment Register .....................................................................................3-21
[1] Code Segment Register (CSR) ................................................................3-21
[2] Table Segment Register (TSR) ................................................................3-22
3.2.6 Special Function Register (SFR) ..............................................................3-23
3.3 Addressing Mode.........................................................................................3-37
3.3.1 RAM Addressing.......................................................................................3-37
[1] Register Addressing .................................................................................3-37
[2] Page Addressing ......................................................................................3-40
[3] Direct Data Addressing.............................................................................3-43
[4] Pointing Register Indirect Addressing.......................................................3-44
[5] Special Bit Area Addressing .....................................................................3-50

Contents-3
3.3.2 ROM Addressing ......................................................................................3-51
[1] Immediate Addressing ..............................................................................3-51
[2] Table Data Addressing .............................................................................3-51
[3] Program Code Addressing .......................................................................3-53
[4] ROM Window Addressing.........................................................................3-55
Chapter 4 CPU Control Functions
4.1 Standby Function...........................................................................................4-1
4.1.1 Standby Control Register (SBYCON).........................................................4-3
4.1.2 Operation in Each Standby Mode...............................................................4-4
[1] HALT Mode.................................................................................................4-4
[2] STOP Mode ................................................................................................4-5
4.2 Reset Function...............................................................................................4-6
Chapter 5 Memory Control Functions
5.1 ROM Window Function..................................................................................5-1
5.2 READY Function............................................................................................5-3
Chapter 6 Port Functions
6.1 Hardware Configuration of Each Port ............................................................6-1
6.1.1 Configuration of Type A (P0_0–P0_7, P1_0–P1_7, P12_0).......................6-4
6.1.2 Configuration of Type B
(P2_0–P2_7, P3_0–P3_3, P7_4–P7_7, P8_0–P8_7, P10_0–P10_4) .......6-5
6.1.3 Configuration of Type C
(P3_4–P3_7, P4_0–P4_7, P5_0–P5_7, P6_0–P6_7, P7_2, P7_3,
P9_0–P9_7, P10_5–P10_7, P11_0–P11_3) ..............................................6-6
6.1.4 Configuration of Type D (P7_0, P7_1, P11_4–P11_7)...............................6-7
6.1.5 Configuration of Type E (P12_1) ................................................................6-7
6.2 Port Control Registers ...................................................................................6-8
6.2.1 Port Data Register (Pn: n = 0–12) .............................................................6-8
6.2.2 Port Mode Register (PnIO: n = 0–12) ........................................................6-8
6.2.3 Port Secondary Function Control Register (PnSF: n = 2–10)....................6-8
6.3 Port 0 (P0) ...................................................................................................6-11
6.4 Port 1 (P1) ...................................................................................................6-12
6.5 Port 2 (P2) ...................................................................................................6-13
6.6 Port 3 (P3) ...................................................................................................6-15
6.7 Port 4 (P4) ...................................................................................................6-17

Contents-4
6.8 Port 5 (P5) ...................................................................................................6-19
6.9 Port 6 (P6) ...................................................................................................6-21
6.10 Port 7 (P7) ...................................................................................................6-23
6.11 Port 8 (P8) ...................................................................................................6-25
6.12 Port 9 (P9) ...................................................................................................6-27
6.13 Port 10 (P10) ...............................................................................................6-29
6.14 Port 11 (P11) ...............................................................................................6-31
6.15 Port 12 (P12) ...............................................................................................6-32
Chapter 7 Output Pin Control Pin (OE)
Chapter 8 Clock Generation Circuit
Chapter 9 Time Base Counter (TBC)
9.1 1/n Counter ....................................................................................................9-2
Chapter 10 Watchdog Timer (WDT)
10.1 WDT Control Register (WDTCON) ..............................................................10-1
10.2 Operation of WDT........................................................................................10-1
10.3 Time until Overflow of WDT.........................................................................10-2
10.4 Program Runaway Detection Timing Diagram ............................................10-2
Chapter 11 Flexible Timer (FTM)
11.1 Configuration of Counter Part ......................................................................11-6
11.2 Counter Selection Part.................................................................................11-8
11.3 Type A1 Register Modules (TMR0–TMR3) ...............................................11-10
11.3.1 Configuration of Type A1 Register Modules (TMR0–TMR3) ................11-10
[1] Timer Registers (TMR0, TMR0L–TMR3, TMR3L)..................................11-10
[2] Capture Control Register (CAPCON) .....................................................11-11
[3] Event Control Registers (EVNTCONL, EVNTCONH).............................11-12
[4] Event Dividing Counters 0–3 (EVDV0–EVDV3) .....................................11-14
[5] EVDV0–EVDV3 Buffer Registers (EVDV0BF–EVDV3BF) .....................11-14
11.3.2 Operation of Type A1 Register Modules (TMR0–TMR3) .....................11-15
11.3.3 Capture Pin Dividing Circuit..................................................................11-16
[1] Configuration of Dividing Circuit .............................................................11-16
[2] Operation of Dividing Circuit ...................................................................11-16
[3] Operation to Switch Dividing Ratio .........................................................11-16

Contents-5
11.4 Type A2 Register Modules (TMR14, TMR15) ...........................................11-17
11.4.1 Configuration of Type A2 Register Modules (TMR14, TMR15) ............11-17
[1] Timer Registers (TMR14, TMR15) .........................................................11-17
[2] Capture Control Register (CAPCON) .....................................................11-18
[3] Event Control Register 2 (EVNTCON2)..................................................11-19
[4] Event Dividing Counters 14, 15 (EVDV14, EVDV15) .............................11-20
[5] EVDV14, EVDV15 Buffer Registers (EVDV14BF, EVDV15BF) .............11-20
11.4.2 Operation of Type A2 Register Modules (TMR14, TMR15) .................11-21
11.4.3 Capture Pin Dividing Circuit..................................................................11-22
[1] Configuration of Dividing Circuit .............................................................11-22
[2] Operation of Dividing Circuit ...................................................................11-22
[3] Operation to Switch Dividing Ratio .........................................................11-22
11.5 Type B Register Modules (TMR4–TMR13) ...............................................11-23
11.5.1 Configuration of Type B Register Modules (TMR4–TMR13) ................11-23
[1] Timer Registers (TMR4–TMR13) ...........................................................11-24
[2] Timer Register Buffer Registers (TMR4BF–TMR13BF) .........................11-24
[3] Real-time Output Control Registers (RTOCON4–RTOCON13) .............11-24
11.5.2 Operation of Type B Register Modules (TMR4–TMR13) .......................11-26
11.6 Type D Register Module (TMR17).............................................................11-27
11.6.1 Configuration of Type D Register Module (TMR17) .............................11-27
[1] Timer Register (TMR17) .........................................................................11-29
[2] Real-time Output Control Registers (RTOCON17, RTO4CON) .............11-29
[3] TMR Mode Register (TMRMODE)..........................................................11-31
[4] Capture Control Register (CAPCON) .....................................................11-32
11.6.2 Operation of Type D Register Module (TMR17) ...................................11-33
[1] Operation in Real-time Output Mode (RTO) ...........................................11-33
[2] Operation in 4-Port Output Real-time Output Mode (4-Port RTO)..........11-34
[3] Operation in CAP Mode..........................................................................11-35
11.7 Type E Register Module (TMR16) .............................................................11-36
11.7.1 Configuration of Type E Register Module (TMR16)..............................11-36
[1] Timer Register (TMR16) .........................................................................11-37
[2] Real-time Output Control Register (RTOCON16)...................................11-37
[3] TMR Mode Register (TMRMODE)..........................................................11-38
[4] Capture Control Register (CAPCON) .....................................................11-39
11.7.2 Operation of Type E Register Module (TMR16) ...................................11-40
[1] Operation in Real-time Output Mode (RTO) ...........................................11-40
[2] Operation in CAP Mode..........................................................................11-40
11.8 RTO Mode Output Timing Changes ..........................................................11-41

Contents-6
Chapter 12 General-Purpose 8-Bit Timer Function
12.1 General-Purpose 8-Bit Timer (GTM) ...........................................................12-2
[1] General-Purpose 8-Bit Timer Counter (GTMC) ........................................12-3
[2] General-Purpose 8-Bit Timer Register (GTMR) .......................................12-3
[3] General-Purpose 8-Bit Timer Control Register (GTMCON) .....................12-3
[4] General-Purpose 8-Bit Timer Interrupt Control Register (GTINTCON) ....12-5
12.2 General-Purpose 8-Bit Event Counter (GEVC) ...........................................12-6
[1] General-Purpose 8-Bit Event Counter (GEVC) ........................................12-6
[2] General-Purpose 8-Bit Timer Control Register (GTMCON) .....................12-6
[3] General-Purpose 8-Bit Timer Interrupt Control Register (GTINTCON) ....12-7
Chapter 13 PWM Functions
13.1 Configuration of PWM..................................................................................13-4
[1] PWM Counters (PWC0–PWC11) .............................................................13-4
[2] PWM Counter Buffer Registers (PWC0BF–PWC11BF) ...........................13-4
[3] PWM Registers (PWR0–PWR11).............................................................13-5
[4] PWM Buffer Registers (PW0BF–PW11BF) ..............................................13-5
[5] Comparison Circuit ...................................................................................13-5
[6] Output F/F.................................................................................................13-5
[7] PWM Control Registers (PWCON0–PWCON5) .......................................13-5
[8] PWMRUN Register (PWRUN)..................................................................13-9
[9] PWM Interrupt Registers (PWINTQ0, PWINTQ1) ..................................13-10
[10] PWM Interrupt Enable Registers (PWINTE0, PWINTE1).......................13-13
13.2 Operation of PWM .....................................................................................13-16
Chapter 14 Baud Rate Generator Functions
14.1 Configuration of SCI0 Timer (S0TM) ...........................................................14-3
[1] SCI0 Timer Counter..................................................................................14-3
[2] SCI0 Timer Register .................................................................................14-3
[3] SCI0 Timer Control Register (S0CON).....................................................14-3
14.2 Operation of SCI0 Timer..............................................................................14-5
14.3 Configuration of SCI1 Timer (S1TM) ...........................................................14-6
[1] SCI1 Timer Counter..................................................................................14-6
[2] SCI1 Timer Register .................................................................................14-6
[3] SCI1 Timer Control Register (S1CON).....................................................14-6
14.4 Operation of SCI1 Timer..............................................................................14-8

Contents-7
14.5 Configuration of SCI2 Timer (S2TM) ...........................................................14-9
[1] SCI2 Timer Counter..................................................................................14-9
[2] SCI2 Timer Register .................................................................................14-9
[3] SCI2 Timer Control Register (S2CON).....................................................14-9
14.6 Operation of SCI2 Timer............................................................................14-11
14.7 Configuration of SCI3 Timer (S3TM) .........................................................14-12
[1] SCI3 Timer Counter................................................................................14-12
[2] SCI3 Timer Register ...............................................................................14-12
[3] SCI3 Timer Control Register (S3CON)...................................................14-12
14.8 Operation of SCI3 Timer............................................................................14-14
14.9 Configuration of SCI4 Timer (S4TM) .........................................................14-15
[1] SCI4 Timer Counter................................................................................14-15
[2] SCI4 Timer Register ...............................................................................14-15
[3] SCI4 Timer Control Register (S4CON)...................................................14-15
14.10 Operation of SCI4 Timer............................................................................14-17
Chapter 15 Serial Port Functions
15.1 Configuration of Serial Ports........................................................................15-2
15.2 Serial Port Control Registers .......................................................................15-5
15.2.1 Control Registers for SCI0......................................................................15-5
[1] SCI0 Transmit Control Register (ST0CON)..............................................15-5
[2] SCI0 Receive Control Register (SR0CON) ..............................................15-7
[3] SCI0 Transmit/Receive Buffer Register (S0BUF0)...................................15-9
[4] SCI0 Receive Buffer Registers (S0BUF1, S0BUF2, S0BUF3).................15-9
[5] SCI0 Transmit and Receive Registers......................................................15-9
[6] SCI0 Status Register 0 (S0STAT0) ........................................................15-10
[7] SCI0 Status Register 1 (S0STAT1) ........................................................15-13
[8] SCI0 Status Register 2 (S0STAT2) ........................................................15-15
[9] SCI0 Interrupt Control Register (SR0INT) ..............................................15-17
15.2.2 Control Registers for SCI1....................................................................15-19
[1] SCI1 Transmit Control Register (ST1CON)............................................15-19
[2] SCI1 Receive Control Register (SR1CON) ............................................15-21
[3] SCI1 Transmit/Receive Buffer Register (S1BUF)...................................15-23
[4] SCI1 Transmit and Receive Registers....................................................15-23
[5] SCI1 Status Register (S1STAT) .............................................................15-23