Oki MSM7586-01 User manual

¡ Semiconductor MSM7586-01/03
1/42
¡ Semiconductor
MSM7586-01/03
p/4 Shift QPSK MODEM/ADPCM CODEC
GENERAL DESCRIPTION
The MSM7586 is a CMOS IC developed for use with digital cordless telephones. The device
provides a p/4 shift QPSK modem function and a CODEC function which performs transcoding
between the voice band analog signal and 32 kbps ADPCM data.
The MSM7586 performs DTMF tone and several types of tone generation, transmit/receive data,
mute and gain control, side-tone pass and its gain control, and VOX function.
FEATURES
(p/4 Shift QPSK Modem Unit)
• 384 kbps transmission speed
• Built-in root Nyquist digital filter for the baseband band limiter
• Built-in D/A converters for the analog outputs of the quadrature signal component I and Q
• The DC offset and gain can be adjusted with respect to the differential I and Q analog outputs
• Completely digitized p/4 shift QPSK demodulator system
(ADPCM CODEC Unit)
• ADPCM system: built-in ITU-T Recommendations G.726 (32kbps, 24 kbps, 16 kbps)
• Transmit/receive full-duplex capability
• PCM interface code format: selectable between m-law and A-law
• Serial ADPCM and PCM transmission rate: 64 kbps to 2,048 kbps
• Transmit/receive mute function; transmit/receive programmable gain setting
• Side tone generator (8-step level adjustment)
• Built-in DTMF tone, ringing tone, and various ringing tone generators
• Built-in VOX function
(Common Unit)
• Operate with a single 3 V power supply (VDD: 2.7 V to 3.6 V)
• Low power consumption
When entire system is operating: 20 mA Typ.
When powered down: 0.02 mA Typ.
• Package:
100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM7586-01TS-K)
(Product name: MSM7586-03TS-K)
E2U0034-28-82
This version: Aug. 1998
Previous version: Nov. 1996

¡ Semiconductor MSM7586-01/03
2/42
BLOCK DIAGRAM
Phase
detector
Delay
detector AFC
SL2 SL1
To each block
+1
–1
+1
–1
Root Nyquist LPF
PLL
3.84M
To D/A
S/P
MAPPING
1/10 384k
–
+
–
+
–1
–
+
4
<MODEM Unit>
<CODEC Unit>
TOUT3
PDN0
PDN1
PDN2
IFIN
IFCK
X2
X1
I+
I–
Q+
Q–
SGCR
AIN1–
AIN1+
GSX1
AIN2–
GSX2
AOUT+
AOUT–
PWI
VFRO
RXD
RXC
SLS
RPR
RCW
AFC
TXD
TXW
TXCI
TXCO
RSYNC
IR
PCMRO
PCMSO
BCLK
PCMSI
XSYNC
IS
VOXO
VDAM AGM VDDM DGM RXSC
MCK
MODEM
MCU
interface
EXCKM
DOUTM
DENM
DINM
R7, R6
R5, R4
To each block
BSTO
SGM
SGCT
IO2
IO1 SW1
SW2
VDAC
SAO
–
+
GSX3
AIN3
–
+
GSX4
AIN4
CODEC
MCU
interface
To each
block
VOXI
TOUT2 TOUT1
RESET
PDN3
AGC
DGC
VDAC
VDDC
IO7 IO6
SW5
IO5
SW4
IO4 IO3
SW3
EXCKC
DENC
DINC
DOUTC
VREF
DPLLDEC SL2
SL1
LPF
LPF
DC Adjust
DC Adjust
D/A
D/A
ATT
ATT
CRM1-B7 to B4
CRM1-B3 to B0
Receiver
Transmitter
CRC5-B7
CRC5-B6
R
R
T
CRC5-B5 CRC5-B4
VOICE
DETECT
COMPA
NDER
ADPCM
CODER
P
/
S
S
/
P
P
/
S
S
/
P
P
/
S
S
/
P
DTMF
/Tone
Generator
BPF
RC
Filter
A/D
Convertor
LPF
RC
Filter
D/A
Convertor
Noise
generator Power detect
+EXPAN
DER
ATT
ATT
CRC3-B7 to B5
CRC2-B2 to B0
CRC3-B3 to B0
Sign bit
ATT
CRC4-B6 CRC2-B6 to B4
PCMRI
ADPCM
DE-
CODER
CRC4-B5
T
R
T
CRM0-B6
Decision
To each block
+

¡ Semiconductor MSM7586-01/03
3/42
PIN CONFIGURATION (TOP VIEW)
100 VDDM
RXSC SLS IFIN NC X1 NC NC X2 IFCK MCK PDN0 PDN1 PDN2 NC RCW AFC RPR RXC RXD
NC DENM EXCKM DOUTM DINM
SAO
AIN3
GSX3
VDAC
VDDC
NC
AIN4
GSX4
NC
IO3 IO4
NC
TOUT1 TOUT2 TOUT3
PDN3
RESET
NC
DINC
DOUTC
EXCKC
DENC
NC
VOXI
VOXO
VDAM
Q–
Q+
I–
I+
NC
SGM
AGM
AGC
SGCR
SGCT
AIN1+
AIN1–
GSX1
IO5
IO6
IO7
AIN2
GSX2
IO1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
IO2
VFRO
PWI
AOUT–
AOUT+
21
22
23
24
25
NC
TXW
TXD
TXCO
TXCI
NC
BSTO
DGM
DGC
R7
R6
R5
R4
NC
BCLK
XSYNC
RSYNC
NC
PCMSO
PCMSI
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
IS
NC
IR
PCMRO
PCMRI
55
54
53
52
51
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC : No connect pin
100-Pin Plastic TQFP

¡ Semiconductor MSM7586-01/03
4/42
PIN AND FUNCTIONAL DESCRIPTIONS
(Modem Unit)
TXD
Transmit data input for 384 kbps.
TXCI
Transmit clock input.
When the control register CRM0 - B6 is "0", a 384 kHz clock pulse synchronous with TXD should
be input to this pin. This clock pulse should be continuous because this device use APLL to
generate an internal clock pulse.
When CRM0 - B6 is "1", a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz
clock pulse is applied to TXCL, TXCO outputs a 384 kHz clock pulse, which is generated by
dividing the TXCL input by 10. The transmit data, synchronous to the 384 kHz clock pulse,
shouldbeinputtotheTXD.InthiscasethedevicesdonotuseAPLL,andthe3.84MHzclockpulse
need not be continuous. (Refer to Fig. 1.)
TXCO
Transmit clock output.
When CRM0 - B6 is "0", TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring
purposes. When CRM0 - B6 is "1", this pin outputs a 384 kHz clock pulse generated by dividing
the TXCI input by 10. (Refer to Fig. 1.)
TXW
Transmit data window signal input.
The transmit timing signal for the burst data is input to this pin. If TXW is "1", the modulation
data is output. (Refer to Fig. 1)

¡ Semiconductor MSM7586-01/03
5/42
Figure 1 Transmit Timing Diagram
(1) CRM0 – B6 = "0"
Ramp rise-up
2 symbols
Ramp
Fall-down
2 symbols
(2) CRM0 – B6 = "1"
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D
n
-1 D
n

,
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D
n
-1 D
n

,
Ramp rise-up
2 symbols
Ramp
Fall-down
2 symbols
Delay of 6.25 symbols Delay of 6.25 symbols
Delay of 6.25 symbols Delay of 6.25 symbols
TXD
TXCI
(384 kHz)
TXW
TXCO
(384 kHz)
I, Q
TXD
TXCI
(3.84 MHz)
TXW
TXCO
(3.84 kHz)
I, Q

¡ Semiconductor MSM7586-01/03
6/42
BSTO
BSTO is the modulator side burst window output.
The burst position of the I and Q baseband modulator output is output.
I+, I–
Quadrature modulation signal I Component differential analog output.
Their output levels are 500 mVpp (when TXD = "0": 360 mVpp typ.) with 1.6 Vdc as the center
value. The output pin load conditions are: R ≥10 kW, C £ 20 pF. The gain of these pins can be
adjusted using the control register CRM1 - B7 to B4, and the offset voltage at the I– pin can be
adjusted using CRM3 - B7 to B3.
Q+, Q–
Quadrature modulation signal Q component differential analog outputs.
Their output levels are 500 mVpp (when TXD = "0": 360 mVpp typ.) with 1.6 Vdc as the center
value. The output pin load conditions are: R ≥10 kW, C £ 20 pF. The gain of these pins can be
adjusted using the control register CRM1 - B3 to B0, and the offset voltage at the Q– pin can be
adjusted by using CRM4 - B7 to B3.
SGM
Internal reference voltage output.
The output voltage value is approximately 2.0 V. Insert a bypass capacitor between this pin and
the AGM pin. During power down, this output is at 0 V.
The external SG voltage if necessary should be used via a buffer.

¡ Semiconductor MSM7586-01/03
7/42
PDN0, PDN1, PDN2
Various power down control.
PDN0 controls the standby mode/communication mode; PDN1 controls the modulator unit;
and PDN2 controls the demodulator unit. Refer to Table 1 for details.
The control register reset input width should be 200ns or more.
Modulator unit is powered off. (VREF and PLL are powered on.)
I and Q outputs are in a high impedance state.
Only the demodulator clock regenerator unit is powered on.
PDN0 PDN2 PDN1
Mode Name Operation State
0 0/1 1 Mode A
1 0 0 Mode D
1 1 1 Mode G
Standby
Mode
Entire system is powered down. The control register is reset.
0 0 0 Mode BEntire system is powered down. The control register is not reset.
1 1 0 Mode FModulator unit is powered off. (VREF and PLL are powered off.)
I and Q outputs are in a high impedance state.
Demodulator unit is powered on.
1 0 1 Mode EModulator unit is powered on.
Only the demodulator clock regenerator unit is powered on.
Modulator unit is powered on.
Demodulator unit is powered on.
Commu-
nication
Mode
0 1 0 Mode CModulator unit is powered off. (VREF and PLL also powered off.)
Demodulator unit is powered on.
Table 1: Description of Modem Power Down Control

¡ Semiconductor MSM7586-01/03
8/42
VDDM, VDAM
+3 V power supply for the modem unit.
Supplied to the digital circuits through the VDDM pin and to the analog circuits through the
VDAM pin. VDDM and VDAM, and VDDC and VDAC should be connected as close as possible
on the PC board.
DGM, AGM
Ground pins for the modem unit.
DGM is the ground pin of the digital system, and AGM is the ground pin of the analog system.
Since DGM and AGM are isolated inside the IC, connect them as close as possible on the circuit
board.
MCK
Master clock input.
The clock frequency is 19.2 MHz.
IFIN
Modulated signal input for the demodulator block.
Select the IF frequency can be selected from 1.2 MHz, 10.7 MHz, 10.75 MHz, and 10.8 MHz, based
on CRM0 - B4 and B3.
IFCK
Clock frequency 19.0222 MHz input for demodulator block IF frequencies of 10.7 MHz.
If the IF frequency is 1.2 MHz or 10.8 MHz, set this pin to "0" or "1". (Refer to Fig. 2.)
X1, X2
Crystal oscillator connection pins.
When supplying a 19.0222 MHz clock to IFCK, use these pins. (Refer to Fig. 2.)
Figure 2 How to Use IFCK, X1, and X2
When IFIN = 10.7 MHz
MSM7586
X1 X2 IFCK
19.0222 MHz
When IFIN = 1.2 MHz or 10.8 MHz
MSM7586
X1 X2 IFCK

¡ Semiconductor MSM7586-01/03
9/42
RXD, RXC, RXSC
Receive data and receive clock outputs.
When the modem unit is powered on, RXD, RXC and RXSC are selected based on SLS as shown
in Figure 3. These outputs are used by the clock regenerator circuit.
Figure 3 Timing Diagram of RXD, RXC, and RXSC
SLS
Receive side operation slot selection signal.
This device has two clock regenerator circuits and two AFC data memory registers. If SLS is "0",
slot 1 is selected, if SLS is "1", slot 2 is selected.
RPR
High-speed phase clock control signal input for the clock recovery circuit.
If this pin is at "0", the circuit is always in the low-speed phase clock mode. If this pin is at "1",
the clock recovery circuit enters the high-speed phase clock mode. When the phase difference
is less than a defined value, the circuit shifts to the low-speed phase clock mode automatically.
RXD
RXC
RXSC
SLS 1 Symbol The regenerated data and clock are
selected asynchronously by the SLS signal.

¡ Semiconductor MSM7586-01/03
10/42
AFC
AFC operation range specification signal input.
As shown in Fig. 4, the AFC information is reset when both AFC and RPR are set to "1". AFC
operation starts after a fixed number of clock cycles and the AFC information is reset. If RPR is
set to "1", an average number of times that AFC turns on is low. If RPR is "0", AFC is high. If AFC
is "0", frequency error is not calculated, but the frequency is corrected using an error that is held.
RCW
Clock recovery circuit operation ON/OFF control signal input.
If RCW this pin is "0", DPLL does not make any phase corrections.
AFC
AFC information
is reset.
RPR
Average
number of times
AFC is low.
AFC information
is maintained.
AFC
RPR
AFC information
is maintained.
The clock recovery circuit
starts with the previous
AFC information.
"0"
(CASE1)
(CASE2)
Average number of times
AFC is high.
Average number of times
AFC is high.
Figure 4 AFC Control Timing Diagram
DENM , EXCKM, DINM, DOUTM
Serial control ports for the microprocessor interface.
The device contains a 6-byte control register (CRM0 - 5). An external CPU uses these pins to read
data from and write data to the control register. DENM is the "Enable" signal input pin. EXCKM
is a data shift clock pulse input pin. DINM is an address and data input pin. DOUTM is a data
output pin. Figure 5 shows input/output timing diagram.

¡ Semiconductor MSM7586-01/03
11/42

High Impedance
High Impedance
(a) Write Data Timing Diagram
(b) Read Data Timing Diagram
DENM
W
EXCKM
DINM A2
DOUTM
A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
R A2A1A0
B7 B6 B5 B4 B3 B2 B1 B0
DENM
EXCKM
DINM
DOUTM



,


,


Figure 5 Modem Unit MCU Interface I/O Timing
The register map is shown below.
Table 2: Modem Unit Control Register (CRM0 to 5) Map
R/W: Read/Write enable R: Read-only register
R7, R6, R5, R4
These are the control register data output pins.
These output the data CRM2 - B7, B6, B5, and B4, respectively.
Register
Name
Address
A2 A1 A0
Data Description R/W
B7 B6 B5 B4 B3 B2 B1 B0
CRM0 000 R/W
—TXC
SEL
MOD
OFF IFSEL1 IFSEL0 — TEST1 TEST0
CRM1 001 R/W
Ich
GAIN3
Ich
GAIN2
Ich
GAIN1
Ich
GAIN0
Qch
GAIN3
Qch
GAIN2
Qch
GAIN1
Qch
GAIN0
CRM2 010 R/W
R7 R6 R5 R4 — — — —
CRM3 011 R/W
Ich
Offset4
Ich
Offset3
Ich
Offset2
Ich
Offset1
Ich
Offset0 ———
CRM4 100 R/W
Qch
Offset3
Qch
Offset2
Qch
Offset1
Qch
Offset0 ———
CRM5 101 R/W
ICT5 ICT4 ICT3 ICT2 LOCAL
INV1
LOCAL
INV0 ICT1 ICT0
Qch
Offset4

¡ Semiconductor MSM7586-01/03
12/42
(CODEC Unit)
AIN1+, AIN1-, AIN2, GSX1, GSX2
The transmit analog input and the output for transmit gain adjustment.
The pin AIN1–(AIN2) connects to the inverting input of the internal transmit amplifier, and the
pin AIN1+ connects to the non-inverting input of the internal transmit amplifier. The pin GSX1
(GSX2) connects to output of the internal transmit amplifier. See Fig. 6 for gain adjustment.
VFRO, AOUT+, AOUT-, PWI
Used for the receive analog output and the output for receive gain adjustment.
VFRO is an output of the receive filter. AOUT+ and AOUT– are differential analog signal outputs
which can directly drive ZL= 350 W+120 nF or the 1.2 kWload. See Fig. 6 for gain adjustment.
However, these outputs are in high impedance state during power down.
SAO, AIN3, AIN4, GSX3, GSX4
Input pins for the internal operational amp.
Refer to Fig.␣ 6 for connection information. However, these output pins are in the high impedance
state during power down.

¡ Semiconductor MSM7586-01/03
13/42
Transmit gain : (VGSX2/Vi)
= (R2/R1) ¥(R4/R3)
AIN1–
GSX1
R2
C1
to ENCODER
R1
Analog output signal
Vo
Receive gain : (VO/VVFRO)
= 2 ¥(R6/R5)
ZL= 120 nF
+ 350 W
AIN2
GSX2
R4
C2 R3
AOUT+
R6 AOUT–
AIN1+
–1
–
+
–
+
–
+
C1 R1 R2
Reference
voltage
generator
SGCT
from
DECODER
+
–
Vi Differential analog input signal
R5
+1
VFRO
+1
SAO
–
+
R7
R8
AIN3
GSX3
Sounder output gain : (VGSX3)
= VSAO ¥(R8/R7)
Sounder output signal
Figure 6 CODEC Unit Analog Interface

¡ Semiconductor MSM7586-01/03
14/42
IO1 to IO7
I/O pins of the internal analog switch.
Refer to the control register description table (CRC5) and the block diagram for connection
information and control methods.
TOUT1 to TOUT3
Sign bit output pins of the tone generator.
Output control of each pin is performed by the control register. Refer to the control register
descriptiontable(CRC5)andtheblockdiagramforconnectioninformationandcontrolmethods.
SGCT, SGCR
Output pins of the CODEC unit analog signal ground voltage.
SGCT outputs the analog signal ground voltage of the transmit system, and SGCR outputs the
same for the receive system. The output voltage value is approximately 1.4 V. Connect 10 mF and
0.1 mF bypass capacitors (ceramic type) between these pins and the AGC pin. During power
down, the output changes to 0 V. The external SG voltage if necessary should be used via a buffer.
VDDC, VDAC
CODEC unit +3 V power supply.
VDDC is supplied to the digital system power supply, and VDAC is supplied to the analog
system power supply. VDDC and VDAC, and VDDM and VDAM must be connected as possible
on the PC board.
DGC, AGC
CODEC unit ground.
DGC is the digital system ground pin, and AGC is the analog system ground pin. Since DGC and
AGC are unconnected in the device, place them as close together as possible on the circuit board.
PDN3
CODEC unit power-down control input.
The CODEC unit changes to the power - down state when set to a digital "0." Since the power-
down control is handled by an OR with control register CRC0 - B5, set CRC0 - B5 to digital "0"
when using this pin.
RESET
Reset control input pin of the CODEC unit control register.
When set to digital "0," each bit of the control register is reset. During normal operation, set this
pin to digital "1." A more than 200ns reset signal should be input.

¡ Semiconductor MSM7586-01/03
15/42
PCMSO
Transmit PCM data output.
This PCM output signal is output from MSB synchronous with the rising edge of BCLK and
XSYNC.
PCMSI
Transmit PCM data input.
This signal is converted to the ADPCM data. The PCM signal is shifted on the falling edge of
BCLK. Normally, this pin is connected to PCMSO.
PCMRO
Receive PCM data output.
The PCM signal is the output signal after ADPCM decoder processing. This signal is serially
output from the MSB synchronous with the rising edge of BCLK and RSYNC.
PCMRI
Receive PCM data input.
The PCM input signal is shifted on the falling edge of BCLK and input from MSB. Normally, this
pin is connected to PCMRO.
IS
Transmit ADPCM signal output.
This signal is the output signal after ADPCM encoding, and is serially output from MSB
synchronous with the rising edge of BCLK and XSYNC. This pin is an open drain output which
remains in a high impedence state during power-down, and requires a pull-up resistor.
IR
Receive ADPCM signal input.
Input data is shifted serially from MSB on the falling edge of BCLK synchronous with RSYNC.
BCLK
Shift clock input for the PCM data (PCMSO, PCMSI, PCMRO, PCMRI) and the ADPCM data(IS,
IR) .
The frequency ranges from 64 kHz to 2048 kHz.
XSYNC
Transmit PCM and ADPCM data 8 kHz synchronous signal input.
This signal should be synchronous with BCLK. XSYNC is used for indicating MSB of the transmit
serial PCM and ADPCM data stream.
RSYNC
Receive PCM and ADPCM data 8 kHz synchronous signal input.
This signal should be synchronous with BCLK signal. RSYNC is used for indicating MSB of the
receive serial PCM and ADPCM data stream.

¡ Semiconductor MSM7586-01/03
16/42
VOXO
Transmit VOX function signal output.
VOX function is used to recognize the presence or absence of the transmit voice signal by
detecting the signal energy. "H" and "L" levels on this pin correspond to the presence and the
absence, respectively. This result also appears at the register data CRC7 - B7. The signal energy
detect threshold is set by the control register data CRC6 - B6, B5.
VOXI
Signal input for receive VOX function.
The "H" level on VOXI indicates the presence of voice signal, the decoder block processes normal
receive signal, and the voice signal appears at analog output pins . The "L" level indicates the
absence of voice signal, the background noise generated in this device is transferred to the analog
output pins. The background noise amplitude is set by the control register CRC6. Because this
signal is ORed with the register data CRC6 - B3, the control register data CRC6 - B3 should be set
to digital "0".
Input voice signal
GSX2 pin
Regenerated voice
VFRO pin
VOXO pin
VOXI pin
Voice Silience Voice
Voice Silience Voice
Voice detection time
Tvxon Silence detection time
(Hangover time) Tvxoff
(a) Transmission Side VOX Function Timing Diagram
(b) Receive Side VOX Function Timing Diagram
Regenerated voice signal
generation time Internal background noise generation time
Note: The VOXO and VOXI pin function are enabled when CRC6 - B7 is set to "1".
Figure 7 VOX Function

¡ Semiconductor MSM7586-01/03
17/42
DENC, EXCKC, DINC, DOUTC
Serial control ports for MCU interface.
Reading and writing data are performed by an external MCU through these pins. The 8-byte
control registers (CRC0 - 7) are provided for the CODEC unit in this device. DENC is the "Enable"
control signal input, EXCKC is the data shift clock input, DINC is the address and data input, and
DOUTC is the data output. Figure 8 shows input/output timing diagram.
Table 3: CODEC Unit Control Register (CRC0 to 7) Map
R/W: Read/Write enable R: Read-only register

High Impedance
High Impedance
(a) Write Data Timing Diagram
(b) Read Data Timing Diagram
DENC
W
EXCKC
DINC A2
DOUTC
A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
R A2A1A0
B7 B6 B5 B4 B3 B2 B1 B0
DENC
EXCKC
DINC
DOUTC



,


,


Figure 8 CODEC Unit MCU Interface I/O Timing
The register map is shown below.
Register
Name
Address
A2 A1 A0
Data Description R/W
B7 B6 B5 B4 B3 B2 B1 B0
CRC0 000 R/W
A/m
SEL —PDN ALL ————
PDN
SAO/AOUT
CRC1 001 R/W
MODE1 MODE0 TX
RESET
RX
RESET
TX
MUTE
RX
MUTE —RX
PAD
CRC2 010 R/W
TX
ON/OFF
TX
GAIN2
TX
GAIN1
TX
GAIN0
RX
ON/OFF
RX
GAIN2
RX
GAIN1
RX
GAIN0
CRC3 011 R/W
Side Tone
GAIN2
Side Tone
GAIN1
Side Tone
GAIN0
TONE
ON/OFF
TONE
GAIN3
TONE
GAIN2
TONE
GAIN1
TONE
GAIN0
CRC4 100 R/W
DTMF/
OTHERS
SEL
TONE
SEND
SAO/
VFRO TONE4 TONE3 TONE2 TONE1 TONE0
CRC5 101 R/W
SW1
CONT
SW2
CONT
SW3
CONT
SW4/5
CONT —TOUT3 CONT
TOUT2
CONT
TOUT1
CONT
CRC6 110 R/W
VOX
ON/OFF
ON
LVL1
ON
LVL0
OFF
TIME
VOX
IN
RX NOISE
LEVEL SEL
RX NOISE
LVL1
RX NOISE
LVL0
CRC7 111 R
VOX
OUT
TX NOISE
LVL1
TX NOISE
LVL0 —————

¡ Semiconductor MSM7586-01/03
18/42
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
VDD
VAIN
VDIN
TSTG
Condition
—
—
—
—
Rating
–0.3 to +5
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–55 to +150
Unit
V
V
V
°C
RECOMMENDED OPERATING CONDITIONS
Modem Unit
(V
DD
= 2.7 V to 3.6 V, Ta = –25°C to +70°C)
CODEC Unit
Parameter
Power Supply Voltage
Operating Temperature
Input High Voltage
Input Low Voltage
Digital Input Rise Time
Digital Input Fall Time
Digital Output Load
Bypass Capacitor for SG
Master Clock Frequency
Master Clock Duty Ratio
Modulator Side Input
Frequency
Demodulator Side
Input Frequency
Clock Duty Ratio
IF Input Duty Ratio
Transmit Sync Pulse
Setting Time
Bit Clock Frequency
Synchronous Signal Frequency
Clock Duty Ratio
Transmit Sync Pulse Setting Time
Receive Sync Pulse Setting Time
Synchronous Signal Width
PCM, ADPCM Set-up Time
PCM, ADPCM Hold Time
Symbol
V
DD
Ta
V
IH
V
IL
t
Ir
t
If
R
DL
C
DL
C
SG
F
MCK
D
MCK
F
TXC1
F
TXC2
F
IFCK1
F
IFCK2
D
CKM
D
CIF
t
XSM ,
t
SXM
t
SDM ,
t
DHM
F
BCK
F
SYNC
D
CKC
t
XSC,
t
SXC
t
RSC,
t
SRC
t
WSC
t
DSC
t
DHC
Conditon
Voltage must be fixed
—
Input pins fully digital
Input pins fully digital
Input pins fully digital
Input pins fully digital
IS (Pull-up resistance)
Input pins fully digital
Between SGM and AGM,
and between SGCT/R and AGC
MCK
MCK
TXCI (When CRM0 - B6 = "0")
TXCI (When CRM0 - B6 = "1")
IFCK (When IFIN = 10.7 MHz)
IFCK
(When IFIN = 10.75 MHz)
IFCK, TXCI, EXCKM
IFIN
TXCI´TXW
TXCI´TXD
BCLK
XSYNC, RSYNC
BCLK, EXCKC
BCLK´XSYNC
BCLK´RSYNC
XSYNC, RSYNC
—
—
Fig.9
Fig.12
Min. Typ. Max. Unit
2.7 — 3.6 V
–25 +25 +70 °C
0.45 ¥
V
DD
V
DD
V
00.16 ¥
V
DD
V
—50ns
—50ns
500 — W
— 100 pF
10 + 0.1 — mF
–0.01% +0.01% MHz
40 60 %
— — kHz
— — MHz
— — MHz
— — MHz
40 60 %
45 55 %
200 — ns
—
—
—
—
—
—
—
19.2
50
384
3.84
19.0222
19.1111
50
50
—
200 — ns—
64 2048 kHz—
— — kHz8.0
40 60 %50
100 — ns—
100 — ns—
1 BCLK 100 ms—
100 — ns—
100 — ns—

¡ Semiconductor MSM7586-01/03
19/42
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
Output High Voltage
Output Low Voltage
Output Leakage Current
Input Capacitance
Symbol
VOH
VOL
IO
Condition
IOH
= 0.4 mA
IOL = –1.2 mA
(IS pin is 500 Wpull-up)
IS pin
Min.
0.5 ¥VDD
0
—
Typ.
—
0.2
—
Max.
VDD
0.4
10
Unit
V
V
mA
CIN — —5—pF
(VDD
= 2.7 V to 3.6 V, Ta = –25°C to +70°C)
0.8 ¥VDD
IDD1
Mode A, Mode B (When V
DD
= 3.0 V)
— 0.02 0.1 mA
IDD2 Mode C (When VDD = 3.0 V) — 5.5 11.0 mA
IDD3 Mode D (When VDD = 3.0 V) — 5.5 11.0 mA
IDD4 Mode E (When VDD = 3.0 V) — 11.5 23.0 mA
IDD5 Mode F (When VDD = 3.0 V) — 9.5 19.0 mA
IDD6 Mode G (When VDD = 3.0 V) — 14.0 28.0 mA
Power Supply Current
(Modem Unit)
* When CODEC Unit is in a
Power Down State
Input Leakage Current IIH
IIL
VI = VDD
VI = 0 V
—
—
—
—
2.0
0.5
mA
mA
Power Supply Current (CODEC Unit)
* When Modem Unit is in a Power
Down State
IDD7
IDD9
When operating *
(When no signal, and VDD = 3.0 V)
When powered down
(When VDD = 3.0 V)
—
—
12.0
0.02
19.0
0.1
mA
mA
IDD8
IOH = 1 mA—V
DD V
— 8.0 16.0 mA
*I
DD7 applies when CRC0 - B0 = "0" and CRC4 - B5 = "0"; IDD8 applies when operating at other
times.

¡ Semiconductor MSM7586-01/03
20/42
Parameter
Output Resistance Load
Symbol
R
LIQ
Condition
I+, I–, Q+, Q–
Min.
10
Typ.
—
Max.
—
Unit
kW
(V
DD
= 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Output Capacitance Load C
LIQ
I+, I–, Q+, Q– — — 20 pF
Output DC Voltage Level V
DCM
I+, I–, Q+, Q– (TXW = 0) 1.55 1.6 1.65 V
Output AC Voltage Level V
ACM
I+, I–, Q+, Q– 340 360 380 mV
PP
(For TXD = 0 continuous input)
Output DC Voltage Adjustment Level Range D
CVL
— ±45 — mV
Output AC Voltage Adjustment Level Range A
CVL
—±4—%
Out-of-band Spectrum P600 600 kHz detuning (continuous) 60 — — dB
P900 900 kHz detuning (continuous) 65 — — dB
Modulation Accuracy E
VM
— 1.0 3.0 %
rms
Demodulator Side IF Input Level I
FV
IFIN input level 0.4 — V
DD
V
PP
IFIN Input Impedance R
IF
—20—kW
SGM Output Voltage V
SGM
— 2.0 — V
SGM Output Impedance R
SGM
— 1.5 — kW
—
—
—
DC impedance
Master Clock External Input Level
I
X11
1.5 — V
DD
V
PP
X1 input level
(When CRM5 – B1 = "0")
I
X12
0.7 — V
DD
V
PP
X1 input level
(When CRM5 – B1 = "1")
—
—
X1 Input Impedande RX1 — 2.0 — MW
X1 Input Capacitance CX1 — 10 — pF
—
—
Offset Voltage Difference V
OFF
–20 — +20 mV
Difference among
I+, I–, Q+ and Q–
Modulator D/A
Conversion Sampling Frequency F
SDA
— 1.92 — MHz—
Modulator D/A
Conversion Offset Frequency F
CDA
— 380 — kHz—
Analog Interface Characteristics (Modem Unit)