Philips TDA8950 Operational manual

1. General description
The TDA8950 is a high-efficiency Class D audio power amplifier. The typical output power
is 2 ×150 W with a speaker load impedance of 4 Ω.
The TDA8950 is available in both HSOP24 and DBS23P power packages. The amplifier
operates over a wide supply voltage range from ±12.5 V to ±40 V and features low
quiescent current consumption.
2. Features
nPin compatible with TDA8920B for both HSOP24 and DBS23P packages
nSymmetrical operating supply voltage range from ±12.5 V to ±40 V
nStereo full differential inputs, can be used as stereo Single-Ended (SE) or mono
Bridge-Tied Load (BTL) amplifier
nHigh output power in typical applications:
uSE 2 ×150 W, RL=4Ω(VP= ±37 V)
uSE 2 ×170 W, RL=4Ω(VP= ±39 V)
uSE 2 ×100 W, RL=6Ω(VP= ±37 V)
uBTL 1 ×300 W, RL=8Ω(VP= ±37 V)
nLow noise
nSmooth pop noise-free start-up and switch off
nZero dead time switching
nFixed frequency
nInternal or external clock
nHigh efficiency
nLow quiescent current
nAdvanced protection strategy: voltage protection and output current limiting
nThermal FoldBack (TFB)
nFixed gain of 30 dB in SE and 36 dB in BTL applications
nFully short-circuit proof across load
nBD modulation in BTL configuration
3. Applications
nDVD
nMini and micro receiver
nHome Theater In A Box (HTIAB) system
nHigh-power speaker system
TDA8950
2×150 W class-D power amplifier
Rev. 02 — 11 June 2009 Product data sheet

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 2 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
4. Quick reference data
[1] VPis the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] The circuit is DC adjusted at VP=±12.5 V to ±32.5 V.
[3] Output power is measured indirectly; based on RDSon measurement; see Section 13.3.
5. Ordering information
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
General, VP[1] = ±30 V
VPsupply voltage Operating mode [2] ±12.5 ±35 ±40 V
VP(ovp) overvoltage protection supply voltage Standby, Mute modes; VDD −VSS 85 - 90 V
Iq(tot) total quiescent current Operating mode; no load; no filter; no
RC-snubber network connected -5075mA
Stereo SE configuration
Pooutput power Tj=85°C; LLC =22µH; CLC = 680 nF
(see Figure 10)[3]
THD + N = 10 %; RL=4Ω; VP=±39 V 170 W
THD + N = 0.5 %; RL= 4 Ω; VP=±37 V - 100 - W
THD + N = 10 %; RL= 4 Ω; VP=±37 V - 150 - W
THD + N = 10 %; RL= 6 Ω; VP= ±37 V - 100 - W
Mono BTL configuration
Pooutput power Tj=85°C; LLC =22µH; CLC = 680 nF
(see Figure 10); RL=8Ω;
THD + N = 10 %; VP=±37 V
[3] - 300 - W
Table 2. Ordering information
Type number Package
Name Description Version
TDA8950J DBS23P plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1
TDA8950TH HSOP24 plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 3 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
6. Block diagram
Pin numbers in brackets refer to type number TDA8950J.
Fig 1. Block diagram
001aah653
OUT1
VSSP1
VDDP2
DRIVER
HIGH
OUT2
BOOT2
TDA8950TH
(TDA8950J)
BOOT1
DRIVER
LOW
SWITCH1 CONTROL
AND
HANDSHAKE
PWM
MODULATOR
MANAGER
OSCILLATOR TEMPERATURE SENSOR
CURRENT PROTECTION
VOLTAGE PROTECTION
STABI
MODE
INPUT
STAGE
mute
9 (3)
8 (2)
IN1M
IN1P
22 (15)
21 (14)
20 (13)
17 (11)
16 (10)
15 (9)
VSSP2VSSP1
DRIVER
HIGH
DRIVER
LOW
SWITCH2 CONTROL
AND
HANDSHAKE
PWM
MODULATOR
11 (5)
n.c.
7 (1)
OSC
2 (19)
SGND
6 (23)
MODE
INPUT
STAGE
mute
5 (22)
4 (21)
IN2M
IN2P
19 (-)24 (17)
VSSD n.c.
1 (18)
VSSA
12 (6)
n.c.
3 (20)
VDDA
10 (4)
n.c.
23 (16)13 (7)18 (12) 14 (8)
VDDP2
PROTSTABI VDDP1

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 4 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
7. Pinning information
7.1 Pinning
Fig 2. Pin configuration TDA8950TH Fig 3. Pin configuration TDA8950J
TDA8950TH
VSSD VSSA
VDDP2 SGND
BOOT2 VDDA
OUT2 IN2M
VSSP2 IN2P
n.c. MODE
STABI OSC
VSSP1 IN1P
OUT1 IN1M
BOOT1 n.c.
VDDP1 n.c.
PROT n.c.
001aah654
24
23
22
21
20
19
18
17
16
15
14
13
11
12
9
10
7
8
5
6
3
4
1
2TDA8950J
OSC
IN1P
IN1M
n.c.
n.c.
n.c.
PROT
VDDP1
BOOT1
OUT1
VSSP1
STABI
VSSP2
OUT2
BOOT2
VDDP2
VSSD
VSSA
SGND
VDDA
IN2M
IN2P
MODE
001aah655
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 5 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
7.2 Pin description
8. Functional description
8.1 General
The TDA8950 is a two-channel audio power amplifier that uses Class D technology.
For each channel, the audio input signal is converted into a digital PWM signal using an
analog input stage and a PWM modulator; see Figure 1. To drive the output power
transistors, the digital PWM signal is fed to a control and handshake block and to high-
and low-side driver circuits. This level-shifts the low-power digital PWM signal from a logic
level to a high-power PWM signal switching between the main supply lines.
A 2nd-order low-pass filter converts the PWM signal to an analog audio signal that can be
used to drive a loudspeaker.
Table 3. Pin description
Symbol Pin Description
TDA8950TH TDA8950J
VSSA 1 18 negative analog supply voltage
SGND 2 19 signal ground
VDDA 3 20 positive analog supply voltage
IN2M 4 21 channel 2 negative audio input
IN2P 5 22 channel 2 positive audio input
MODE 6 23 mode selection input: Standby, Mute or Operating
mode
OSC 7 1 oscillator frequency adjustment or tracking input
IN1P 8 2 channel 1 positive audio input
IN1M 9 3 channel 1 negative audio input
n.c. 10 4 not connected
n.c. 11 5 not connected
n.c. 12 6 not connected
PROT 13 7 decoupling capacitor for protection (OCP)
VDDP1 14 8 channel 1 positive power supply voltage
BOOT1 15 9 channel 1 bootstrap capacitor
OUT1 16 10 channel 1 PWM output
VSSP1 17 11 channel 1 negative power supply voltage
STABI 18 12 decoupling of internal stabilizer for logic supply
n.c. 19 - not connected
VSSP2 20 13 channel 2 negative power supply voltage
OUT2 21 14 channel 2 PWM output
BOOT2 22 15 channel 2 bootstrap capacitor
VDDP2 23 16 channel 2 positive power supply voltage
VSSD 24 17 negative digital supply voltage

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 6 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
The TDA8950 single-chip Class D amplifier contains high-power switches, drivers, timing
and handshaking between the power switches, along with some control logic. To ensure
maximum system robustness, an advanced protection strategy has been implemented to
provide overvoltage, overtemperature and overcurrent protection.
Each of the two audio channels contains a PWM modulator, an analog feedback loop and
a differential input stage. The TDA8950 also contains circuits common to both channels
such as the oscillator, all reference sources, the mode interface and a digital timing
manager.
The two independent amplifier channels feature high output power, high efficiency, low
distortion and low quiescent currents, and can be connected in the following
configurations:
•Stereo Single-Ended (SE)
•Mono Bridge-Tied Load (BTL)
The amplifier system can be switched to one of three operating modes using pin MODE:
•Standby mode: featuring very low quiescent current
•Mute mode: the amplifier is operational but the audio signal at the output is
suppressed by disabling the voltage-to-current (VI converter) input stages
•Operating mode: the amplifier is fully operational, de-muted and can deliver an output
signal
A slowly rising voltage should be applied (e.g. via an RC network) to pin MODE to ensure
pop noise-free start-up. The bias-current setting of the (VI converter) input stages is
related to the voltage on the MODE pin.
In Mute mode, the bias-current setting of the VI converters is zero (VI converters are
disabled). In Operating mode, the bias current is at a maximum. The time constant
required to apply the DC output offset voltage gradually between Mute and Operating
mode levels can be generated using an RC network connected to pin MODE. An example
of a switching circuit for driving pin MODE is illustrated in Figure 4. If the capacitor was
omitted, the very short switching time constant could result in audible pop noises being
generated at start-up (depending on the DC output offset voltage and loudspeaker used).
Fig 4. Example of mode selection circuit
010aaa552
SGND
mode control
mute/
operating
10 µF
5.6 kΩ
+5 V
470 Ω
standby/
operating S2S1
5.6 kΩ

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 7 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
To ensure the coupling capacitors at the inputs (CIN in Figure 10) are fully charged before
the outputs start switching, a delay is inserted during the transition from Mute to Operating
mode. An overview of the start-up timing is provided in Figure 5. For proper switch-off, the
MODE pin should be forced LOW at leaxt 100 ms before the supply lines (VDDA and VSSA)
drop below 12.5 V.
(1) First 1⁄4pulse down.
Upper diagram: When switching from Standby to Mute, there is a delay of approximately 100 ms
before the output starts switching. The audio signal will become available once VMODE reaches the
Operating mode level (see Table 8), but not earlier than 150 ms after switching to Mute. To start-up
pop noise-free, it is recommended that the time constant applied to pin MODE be at least 350 ms
for the transition between Mute and Operating modes.
Lower diagram: When switching directly from Standby to Operating mode, there is a delay of
100 ms before the outputs start switching. The audio signal becomes available after a second
delay of 50 ms. To start-up pop noise-free, it is recommended that the time-constant applied to pin
MODE be at least 500 ms for the transition between Standby and Operating modes.
Fig 5. Timing on mode selection input pin MODE
2.2 V < VMODE < 3 V
audio output
operating
standby
mute
50 %
duty cycle
> 4.2 V
0 V (SGND) time
001aah657
VMODE
100 ms 50 ms
modulated PWM
>350 ms
2.2 V < VMODE < 3 V
audio output
operating
standby
mute
50 %
duty cycle
> 4.2 V
0 V (SGND) time
VMODE
100 ms 50 ms
modulated PWM
>350 ms
(1)
(1)

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 8 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
8.2 Pulse-width modulation frequency
The amplifier output signal is a PWM signal with a typical carrier frequency of between
250 kHz and 450 kHz. A 2nd-order LC demodulation filter on the output is used to convert
the PWM signal into an analog audio signal. The carrier frequency is determined by an
external resistor, ROSC, connected between pins OSC and VSSA. The optimal carrier
frequency setting is between 250 kHz and 450 kHz.
The carrier frequency is set to 345 kHz by connecting an external 30 kΩresistor between
pins OSC and VSSA. See Table 9 for more details.
If two or more Class D amplifiers are used in the same audio application, it is
recommended that an external clock circuit be used with all devices (see Section 13.4).
This will ensure that they operate at the same switching frequency, thus avoiding beat
tones (if the switching frequencies are different, audible interference known as ‘beat tones’
can be generated)
8.3 Protection
The following protection circuits are incorporated into the TDA8950:
•Thermal protection:
–Thermal FoldBack (TFB)
–OverTemperature Protection (OTP)
•OverCurrent Protection (OCP)
•Window Protection (WP)
•Supply voltage protection:
–UnderVoltage Protection (UVP)
–OverVoltage Protection (OVP)
–UnBalance Protection (UBP)
How the device reacts to a fault conditions depends on which protection circuit has been
activated.
8.3.1 Thermal protection
The TDA8950 employes an advanced thermal protection strategy. A TFB function
gradually reduces the output power within a defined temperature range. If the temperature
continues to rise, OTP is activated to shut down the device completely.
8.3.1.1 Thermal FoldBack (TFB)
If the junction temperature (Tj) exceeds the thermal foldback activation threshold, the gain
is gradually reduced. This reduces the output signal amplitude and the power dissipation,
eventually stabilizing the temperature.
TFB is specified at the thermal foldback activation temperature Tact(th_fold) where the
closed-loop voltage gain is reduced by 6 dB. The TFB range is:
Tact(th_fold) −5°C < Tact(th_fold) < Tact(th_prot)
The value of Tact(th_fold) for the TDA8950 is approximately 153 °C; see Table 8 for more
details.

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 9 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
8.3.1.2 OverTemperature Protection (OTP)
If TFB fails to stabilize the temperature and the junction temperature continues to rise, the
amplifier will shut down as soon as the temperature reaches the thermal protection
activation threshold, Tact(th_prot). The amplifier will resume switching approximately 100 ms
after the temperature drops below Tact(th_prot).
The thermal behavior is illustrated in Figure 6.
8.3.2 OverCurrent Protection (OCP)
In order to guarantee the robustness of the TDA8950, the maximum output current that
can be delivered at the output stages is limited. OCP is built in for each output power
switch.
OCP is activated when the current in one of the power transistors exceeds the OCP
threshold (IORM = 9.2 A) due, for example, to a short-circuit to a supply line or across the
load.
The TDA8950 amplifier distinguishes between low-ohmic short-circuit conditions and
other overcurrent conditions such as a dynamic impedance drop at the loudspeaker. The
impedance threshold (Zth) depends on the supply voltage.
How the amplifier reacts to a short circuit depends on the short-circuit impedance:
•Short-circuit impedance > Zth: the amplifier limits the maximum output current to IORM
but the amplifier does not shut down the PWM outputs. Effectively, this results in a
clipped output signal across the load (behavior very similar to voltage clipping).
•Short-circuit impedance < Zth: the amplifier limits the maximum output current to IORM
and at the same time discharges the capacitor on pin PROT. When CPROT is fully
discharged, the amplifier shuts down completely and an internal timer is started.
The value of the protection capacitor (CPROT) connected to pin PROT can be between
10 pF and 220 pF (typically 47 pF). While OCP is activated, an internal current source is
enabled that will discharge CPROT.
(1) Duty cycle of PWM output modulated according to the audio input signal.
(2) Duty cycle of PWM output reduced due to TFB.
(3) Amplifier is switched off due to OTP.
Fig 6. Behavior of TFB and OTP
001aah656
(Tact(th_fold) − 5°C) Tact(th_fold) Tj (°C)Tact(th_prot)
Gain
(dB)
30 dB
24 dB
0 dB
12 3

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 10 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
When OCP is activated, the power transistors are turned off. They are turned on again
during the next switching cycle. If the output current is still greater than the OCP threshold,
they will be immediately switched off again. This switching will continue until CPROT is fully
discharged. The amplifier will then be switched off completely and a restart sequence
initiated.
After a fixed period of 100 ms, the amplifier will attempt to switch on again, but will fail if
the output current still exceeds the OCP threshold. The amplifier will continue trying to
switch on every 100 ms. The average power dissipation will be low in this situation
because the duty cycle is low.
Switching the amplifier on and off in this way will generate unwanted ‘audio holes’. This
can be avoided by increasing the value of CPROT (up to 220 pF) to delay amplifier
switch-off. CPROT will also prevent the amplifier switching off due to transient
frequency-dependent impedance drops at the speakers.
The amplifier will switch on, and remain in Operating mode, once the overcurrent
condition has been removed. OCP ensures the TDA8950 amplifier is fully protected
against short-circuit conditions while avoiding audio holes.
[1] VPis the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] OVP can be triggered by supply pumping; see Section 13.6.
8.3.3 Window Protection (WP)
Window Protection (WP) checks the conditions at the output terminals of the power stage
and is activated:
•During the start-up sequence, when the TDA8950 is switching from Standby to Mute.
Start-up will be interrupted If a short-circuit is detected between one of the output
terminals and pin VDDP1/VDDP2 or VSSP1/VSSP2. The TDA8950 will wait until the
short-circuit to the supply lines has been removed before resuming start-up. The short
circuit will not generate large currents because the short-circuit check is carried out
before the power stages are enabled.
•When the amplifier is shut down completely because the OCP circuit has detected a
short circuit to one of the supply lines.
WP will be activated when the amplifier attempts to restart after 100 ms (see
Section 8.3.2). The amplifier will not start-up again until the short circuit to the supply
lines has been removed.
Table 4. Current limiting behavior during low output impedance conditions at different
values of CPROT
Type VP[1] (V) VI(mV, p-p) f (Hz) CPROT
(pF) PWM output stops
Short
(Zth =0Ω)Short (Zth = 0.5 Ω)Short (Zth =1Ω)
TDA8950 29.5 500 20 10 yes yes OVP[2]
1000 10 yes yes no
20 15 yes yes OVP[2]
1000 15 yes no no
1000 220 no no no