Philips TDA8950 Operational manual

1. General description
The TDA8950 is a high-efficiency Class D audio power amplifier. The typical output power
is 2 ×150 W with a speaker load impedance of 4 Ω.
The TDA8950 is available in both HSOP24 and DBS23P power packages. The amplifier
operates over a wide supply voltage range from ±12.5 V to ±40 V and features low
quiescent current consumption.
2. Features
nPin compatible with TDA8920B for both HSOP24 and DBS23P packages
nSymmetrical operating supply voltage range from ±12.5 V to ±40 V
nStereo full differential inputs, can be used as stereo Single-Ended (SE) or mono
Bridge-Tied Load (BTL) amplifier
nHigh output power in typical applications:
uSE 2 ×150 W, RL=4Ω(VP= ±37 V)
uSE 2 ×170 W, RL=4Ω(VP= ±39 V)
uSE 2 ×100 W, RL=6Ω(VP= ±37 V)
uBTL 1 ×300 W, RL=8Ω(VP= ±37 V)
nLow noise
nSmooth pop noise-free start-up and switch off
nZero dead time switching
nFixed frequency
nInternal or external clock
nHigh efficiency
nLow quiescent current
nAdvanced protection strategy: voltage protection and output current limiting
nThermal FoldBack (TFB)
nFixed gain of 30 dB in SE and 36 dB in BTL applications
nFully short-circuit proof across load
nBD modulation in BTL configuration
3. Applications
nDVD
nMini and micro receiver
nHome Theater In A Box (HTIAB) system
nHigh-power speaker system
TDA8950
2×150 W class-D power amplifier
Rev. 02 — 11 June 2009 Product data sheet

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 2 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
4. Quick reference data
[1] VPis the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] The circuit is DC adjusted at VP=±12.5 V to ±32.5 V.
[3] Output power is measured indirectly; based on RDSon measurement; see Section 13.3.
5. Ordering information
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
General, VP[1] = ±30 V
VPsupply voltage Operating mode [2] ±12.5 ±35 ±40 V
VP(ovp) overvoltage protection supply voltage Standby, Mute modes; VDD −VSS 85 - 90 V
Iq(tot) total quiescent current Operating mode; no load; no filter; no
RC-snubber network connected -5075mA
Stereo SE configuration
Pooutput power Tj=85°C; LLC =22µH; CLC = 680 nF
(see Figure 10)[3]
THD + N = 10 %; RL=4Ω; VP=±39 V 170 W
THD + N = 0.5 %; RL= 4 Ω; VP=±37 V - 100 - W
THD + N = 10 %; RL= 4 Ω; VP=±37 V - 150 - W
THD + N = 10 %; RL= 6 Ω; VP= ±37 V - 100 - W
Mono BTL configuration
Pooutput power Tj=85°C; LLC =22µH; CLC = 680 nF
(see Figure 10); RL=8Ω;
THD + N = 10 %; VP=±37 V
[3] - 300 - W
Table 2. Ordering information
Type number Package
Name Description Version
TDA8950J DBS23P plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm) SOT411-1
TDA8950TH HSOP24 plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 3 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
6. Block diagram
Pin numbers in brackets refer to type number TDA8950J.
Fig 1. Block diagram
001aah653
OUT1
VSSP1
VDDP2
DRIVER
HIGH
OUT2
BOOT2
TDA8950TH
(TDA8950J)
BOOT1
DRIVER
LOW
SWITCH1 CONTROL
AND
HANDSHAKE
PWM
MODULATOR
MANAGER
OSCILLATOR TEMPERATURE SENSOR
CURRENT PROTECTION
VOLTAGE PROTECTION
STABI
MODE
INPUT
STAGE
mute
9 (3)
8 (2)
IN1M
IN1P
22 (15)
21 (14)
20 (13)
17 (11)
16 (10)
15 (9)
VSSP2VSSP1
DRIVER
HIGH
DRIVER
LOW
SWITCH2 CONTROL
AND
HANDSHAKE
PWM
MODULATOR
11 (5)
n.c.
7 (1)
OSC
2 (19)
SGND
6 (23)
MODE
INPUT
STAGE
mute
5 (22)
4 (21)
IN2M
IN2P
19 (-)24 (17)
VSSD n.c.
1 (18)
VSSA
12 (6)
n.c.
3 (20)
VDDA
10 (4)
n.c.
23 (16)13 (7)18 (12) 14 (8)
VDDP2
PROTSTABI VDDP1

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 4 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
7. Pinning information
7.1 Pinning
Fig 2. Pin configuration TDA8950TH Fig 3. Pin configuration TDA8950J
TDA8950TH
VSSD VSSA
VDDP2 SGND
BOOT2 VDDA
OUT2 IN2M
VSSP2 IN2P
n.c. MODE
STABI OSC
VSSP1 IN1P
OUT1 IN1M
BOOT1 n.c.
VDDP1 n.c.
PROT n.c.
001aah654
24
23
22
21
20
19
18
17
16
15
14
13
11
12
9
10
7
8
5
6
3
4
1
2TDA8950J
OSC
IN1P
IN1M
n.c.
n.c.
n.c.
PROT
VDDP1
BOOT1
OUT1
VSSP1
STABI
VSSP2
OUT2
BOOT2
VDDP2
VSSD
VSSA
SGND
VDDA
IN2M
IN2P
MODE
001aah655
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 5 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
7.2 Pin description
8. Functional description
8.1 General
The TDA8950 is a two-channel audio power amplifier that uses Class D technology.
For each channel, the audio input signal is converted into a digital PWM signal using an
analog input stage and a PWM modulator; see Figure 1. To drive the output power
transistors, the digital PWM signal is fed to a control and handshake block and to high-
and low-side driver circuits. This level-shifts the low-power digital PWM signal from a logic
level to a high-power PWM signal switching between the main supply lines.
A 2nd-order low-pass filter converts the PWM signal to an analog audio signal that can be
used to drive a loudspeaker.
Table 3. Pin description
Symbol Pin Description
TDA8950TH TDA8950J
VSSA 1 18 negative analog supply voltage
SGND 2 19 signal ground
VDDA 3 20 positive analog supply voltage
IN2M 4 21 channel 2 negative audio input
IN2P 5 22 channel 2 positive audio input
MODE 6 23 mode selection input: Standby, Mute or Operating
mode
OSC 7 1 oscillator frequency adjustment or tracking input
IN1P 8 2 channel 1 positive audio input
IN1M 9 3 channel 1 negative audio input
n.c. 10 4 not connected
n.c. 11 5 not connected
n.c. 12 6 not connected
PROT 13 7 decoupling capacitor for protection (OCP)
VDDP1 14 8 channel 1 positive power supply voltage
BOOT1 15 9 channel 1 bootstrap capacitor
OUT1 16 10 channel 1 PWM output
VSSP1 17 11 channel 1 negative power supply voltage
STABI 18 12 decoupling of internal stabilizer for logic supply
n.c. 19 - not connected
VSSP2 20 13 channel 2 negative power supply voltage
OUT2 21 14 channel 2 PWM output
BOOT2 22 15 channel 2 bootstrap capacitor
VDDP2 23 16 channel 2 positive power supply voltage
VSSD 24 17 negative digital supply voltage

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 6 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
The TDA8950 single-chip Class D amplifier contains high-power switches, drivers, timing
and handshaking between the power switches, along with some control logic. To ensure
maximum system robustness, an advanced protection strategy has been implemented to
provide overvoltage, overtemperature and overcurrent protection.
Each of the two audio channels contains a PWM modulator, an analog feedback loop and
a differential input stage. The TDA8950 also contains circuits common to both channels
such as the oscillator, all reference sources, the mode interface and a digital timing
manager.
The two independent amplifier channels feature high output power, high efficiency, low
distortion and low quiescent currents, and can be connected in the following
configurations:
•Stereo Single-Ended (SE)
•Mono Bridge-Tied Load (BTL)
The amplifier system can be switched to one of three operating modes using pin MODE:
•Standby mode: featuring very low quiescent current
•Mute mode: the amplifier is operational but the audio signal at the output is
suppressed by disabling the voltage-to-current (VI converter) input stages
•Operating mode: the amplifier is fully operational, de-muted and can deliver an output
signal
A slowly rising voltage should be applied (e.g. via an RC network) to pin MODE to ensure
pop noise-free start-up. The bias-current setting of the (VI converter) input stages is
related to the voltage on the MODE pin.
In Mute mode, the bias-current setting of the VI converters is zero (VI converters are
disabled). In Operating mode, the bias current is at a maximum. The time constant
required to apply the DC output offset voltage gradually between Mute and Operating
mode levels can be generated using an RC network connected to pin MODE. An example
of a switching circuit for driving pin MODE is illustrated in Figure 4. If the capacitor was
omitted, the very short switching time constant could result in audible pop noises being
generated at start-up (depending on the DC output offset voltage and loudspeaker used).
Fig 4. Example of mode selection circuit
010aaa552
SGND
mode control
mute/
operating
10 µF
5.6 kΩ
+5 V
470 Ω
standby/
operating S2S1
5.6 kΩ

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 7 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
To ensure the coupling capacitors at the inputs (CIN in Figure 10) are fully charged before
the outputs start switching, a delay is inserted during the transition from Mute to Operating
mode. An overview of the start-up timing is provided in Figure 5. For proper switch-off, the
MODE pin should be forced LOW at leaxt 100 ms before the supply lines (VDDA and VSSA)
drop below 12.5 V.
(1) First 1⁄4pulse down.
Upper diagram: When switching from Standby to Mute, there is a delay of approximately 100 ms
before the output starts switching. The audio signal will become available once VMODE reaches the
Operating mode level (see Table 8), but not earlier than 150 ms after switching to Mute. To start-up
pop noise-free, it is recommended that the time constant applied to pin MODE be at least 350 ms
for the transition between Mute and Operating modes.
Lower diagram: When switching directly from Standby to Operating mode, there is a delay of
100 ms before the outputs start switching. The audio signal becomes available after a second
delay of 50 ms. To start-up pop noise-free, it is recommended that the time-constant applied to pin
MODE be at least 500 ms for the transition between Standby and Operating modes.
Fig 5. Timing on mode selection input pin MODE
2.2 V < VMODE < 3 V
audio output
operating
standby
mute
50 %
duty cycle
> 4.2 V
0 V (SGND) time
001aah657
VMODE
100 ms 50 ms
modulated PWM
>350 ms
2.2 V < VMODE < 3 V
audio output
operating
standby
mute
50 %
duty cycle
> 4.2 V
0 V (SGND) time
VMODE
100 ms 50 ms
modulated PWM
>350 ms
(1)
(1)

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 8 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
8.2 Pulse-width modulation frequency
The amplifier output signal is a PWM signal with a typical carrier frequency of between
250 kHz and 450 kHz. A 2nd-order LC demodulation filter on the output is used to convert
the PWM signal into an analog audio signal. The carrier frequency is determined by an
external resistor, ROSC, connected between pins OSC and VSSA. The optimal carrier
frequency setting is between 250 kHz and 450 kHz.
The carrier frequency is set to 345 kHz by connecting an external 30 kΩresistor between
pins OSC and VSSA. See Table 9 for more details.
If two or more Class D amplifiers are used in the same audio application, it is
recommended that an external clock circuit be used with all devices (see Section 13.4).
This will ensure that they operate at the same switching frequency, thus avoiding beat
tones (if the switching frequencies are different, audible interference known as ‘beat tones’
can be generated)
8.3 Protection
The following protection circuits are incorporated into the TDA8950:
•Thermal protection:
–Thermal FoldBack (TFB)
–OverTemperature Protection (OTP)
•OverCurrent Protection (OCP)
•Window Protection (WP)
•Supply voltage protection:
–UnderVoltage Protection (UVP)
–OverVoltage Protection (OVP)
–UnBalance Protection (UBP)
How the device reacts to a fault conditions depends on which protection circuit has been
activated.
8.3.1 Thermal protection
The TDA8950 employes an advanced thermal protection strategy. A TFB function
gradually reduces the output power within a defined temperature range. If the temperature
continues to rise, OTP is activated to shut down the device completely.
8.3.1.1 Thermal FoldBack (TFB)
If the junction temperature (Tj) exceeds the thermal foldback activation threshold, the gain
is gradually reduced. This reduces the output signal amplitude and the power dissipation,
eventually stabilizing the temperature.
TFB is specified at the thermal foldback activation temperature Tact(th_fold) where the
closed-loop voltage gain is reduced by 6 dB. The TFB range is:
Tact(th_fold) −5°C < Tact(th_fold) < Tact(th_prot)
The value of Tact(th_fold) for the TDA8950 is approximately 153 °C; see Table 8 for more
details.

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 9 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
8.3.1.2 OverTemperature Protection (OTP)
If TFB fails to stabilize the temperature and the junction temperature continues to rise, the
amplifier will shut down as soon as the temperature reaches the thermal protection
activation threshold, Tact(th_prot). The amplifier will resume switching approximately 100 ms
after the temperature drops below Tact(th_prot).
The thermal behavior is illustrated in Figure 6.
8.3.2 OverCurrent Protection (OCP)
In order to guarantee the robustness of the TDA8950, the maximum output current that
can be delivered at the output stages is limited. OCP is built in for each output power
switch.
OCP is activated when the current in one of the power transistors exceeds the OCP
threshold (IORM = 9.2 A) due, for example, to a short-circuit to a supply line or across the
load.
The TDA8950 amplifier distinguishes between low-ohmic short-circuit conditions and
other overcurrent conditions such as a dynamic impedance drop at the loudspeaker. The
impedance threshold (Zth) depends on the supply voltage.
How the amplifier reacts to a short circuit depends on the short-circuit impedance:
•Short-circuit impedance > Zth: the amplifier limits the maximum output current to IORM
but the amplifier does not shut down the PWM outputs. Effectively, this results in a
clipped output signal across the load (behavior very similar to voltage clipping).
•Short-circuit impedance < Zth: the amplifier limits the maximum output current to IORM
and at the same time discharges the capacitor on pin PROT. When CPROT is fully
discharged, the amplifier shuts down completely and an internal timer is started.
The value of the protection capacitor (CPROT) connected to pin PROT can be between
10 pF and 220 pF (typically 47 pF). While OCP is activated, an internal current source is
enabled that will discharge CPROT.
(1) Duty cycle of PWM output modulated according to the audio input signal.
(2) Duty cycle of PWM output reduced due to TFB.
(3) Amplifier is switched off due to OTP.
Fig 6. Behavior of TFB and OTP
001aah656
(Tact(th_fold) − 5°C) Tact(th_fold) Tj (°C)Tact(th_prot)
Gain
(dB)
30 dB
24 dB
0 dB
12 3

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 10 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
When OCP is activated, the power transistors are turned off. They are turned on again
during the next switching cycle. If the output current is still greater than the OCP threshold,
they will be immediately switched off again. This switching will continue until CPROT is fully
discharged. The amplifier will then be switched off completely and a restart sequence
initiated.
After a fixed period of 100 ms, the amplifier will attempt to switch on again, but will fail if
the output current still exceeds the OCP threshold. The amplifier will continue trying to
switch on every 100 ms. The average power dissipation will be low in this situation
because the duty cycle is low.
Switching the amplifier on and off in this way will generate unwanted ‘audio holes’. This
can be avoided by increasing the value of CPROT (up to 220 pF) to delay amplifier
switch-off. CPROT will also prevent the amplifier switching off due to transient
frequency-dependent impedance drops at the speakers.
The amplifier will switch on, and remain in Operating mode, once the overcurrent
condition has been removed. OCP ensures the TDA8950 amplifier is fully protected
against short-circuit conditions while avoiding audio holes.
[1] VPis the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] OVP can be triggered by supply pumping; see Section 13.6.
8.3.3 Window Protection (WP)
Window Protection (WP) checks the conditions at the output terminals of the power stage
and is activated:
•During the start-up sequence, when the TDA8950 is switching from Standby to Mute.
Start-up will be interrupted If a short-circuit is detected between one of the output
terminals and pin VDDP1/VDDP2 or VSSP1/VSSP2. The TDA8950 will wait until the
short-circuit to the supply lines has been removed before resuming start-up. The short
circuit will not generate large currents because the short-circuit check is carried out
before the power stages are enabled.
•When the amplifier is shut down completely because the OCP circuit has detected a
short circuit to one of the supply lines.
WP will be activated when the amplifier attempts to restart after 100 ms (see
Section 8.3.2). The amplifier will not start-up again until the short circuit to the supply
lines has been removed.
Table 4. Current limiting behavior during low output impedance conditions at different
values of CPROT
Type VP[1] (V) VI(mV, p-p) f (Hz) CPROT
(pF) PWM output stops
Short
(Zth =0Ω)Short (Zth = 0.5 Ω)Short (Zth =1Ω)
TDA8950 29.5 500 20 10 yes yes OVP[2]
1000 10 yes yes no
20 15 yes yes OVP[2]
1000 15 yes no no
1000 220 no no no

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 11 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
8.3.4 Supply voltage protection
If the supply voltage drops below the minimum supply voltage threshold, VP(uvp), the UVP
circuit will be activated and the system will shut down. Once the supply voltage rises
above VP(uvp) again, the system will restart after a delay of 100 ms.
If the supply voltage exceeds the maximum supply voltage threshold, VP(ovp), the OVP
circuit will be activated and the power stages will be shut down. When the supply voltage
drops below VP(ovp) again, the system will restart after a delay of 100 ms.
An additional UnBalance Protection (UBP) circuit compares the positive analog supply
voltage (on pin VDDA) with the negative analog supply voltage (on pin VSSA) and is
triggered if the voltage difference exceeds a factor of two (VDDA > 2 ×|VSSA|OR |VSSA|>
2×VDDA). When the supply voltage difference drops below the unbalance threshold,
VP(ubp), the system restarts after 100 ms.
An overview of all protection circuits and their respective effects on the output signal is
provided in Table 5.
[1] Amplifier gain depends on the junction temperature and heatsink size.
[2] The amplifier shuts down completely only if the short-circuit impedance is below the impedance threshold
(Zth; see Section 8.3.2). In all other cases, current limiting results in a clipped output signal.
[3] Fault condition detected during any Standby-to-Mute transition or during a restart after OCP has been
activated (short-circuit to one of the supply lines).
8.4 Differential audio inputs
The audio inputs are fully differential ensuring a high common mode rejection ratio and
maximum flexibility in the application.
•Stereo operation: to avoid acoustical phase differences, the inputs should be in
antiphase and the speakers should be connected in antiphase. This configuration:
–minimizes power supply peak current
–minimizes supply pumping effects, especially at low audio frequencies
•Mono BTL operation: the inputs must be connected in anti-parallel. The output of one
channel is inverted and the speaker load is connected between the two outputs of the
TDA8950. In practice (because of the OCP threshold) the output power can be
boosted to twice the output power that can be achieved with the single-ended
configuration.
The input configuration for a mono BTL application is illustrated in Figure 7.
Table 5. Overview of TDA8950 protection circuits
Protection name Complete
shutdown Restart directly Restart after 100 ms Pin PROT detection
TFB[1] NNNN
OTP Y N Y N
OCP Y[2] N[2] Y[2] Y
WP N[3] YNN
UVPYNYN
OVP Y N Y N
UBPYNYN

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 12 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
9. Limiting values
[1] VPis the supply voltage on pins VDDP1, VDDP2 and VDDA.
10. Thermal characteristics
Fig 7. Input configuration for mono BTL application
Vin
IN1P OUT1
power stage
mbl466
OUT2
SGND
IN1M
IN2P
IN2M
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VP[1] supply voltage Standby, Mute modes; VDD −VSS -90 V
IORM repetitive peak output current maximum output current limiting 9.2 - A
Tstg storage temperature −55 +150 °C
Tamb ambient temperature −40 +85 °C
Tjjunction temperature - 150 °C
VMODE voltage on pin MODE referenced to SGND 0 6 V
VOSC voltage on pin OSC 0 SGND + 6 V
VIinput voltage referenced to SGND; pin IN1P; IN1M;
IN2P and IN2M −5+5 V
VPROT voltage on pin PROT referenced to voltage on pin VSSD 0 12 V
VESD electrostatic discharge voltage Human Body Model (HBM) −2000 +2000 V
Charged Device Model (CDM) −500 +500 V
Iq(tot) total quiescent current Operating mode; no load; no filter; no
RC-snubber network connected -75 mA
VPWM(p-p) peak-to-peak PWM voltage on pins OUT1 and OUT2 - 120 V
Table 7. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient in free air 40 K/W
Rth(j-c) thermal resistance from junction to case 1.1 K/W

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 13 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
11. Static characteristics
[1] VPis the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] The circuit is DC adjusted at VP=±12.5 V to ±42.5 V.
[3] Unbalance protection activated when VDDA > 2 ×|VSSA|OR |VSSA|> 2 ×VDDA.
[4] With respect to SGND (0 V).
[5] The transition between Standby and Mute modes has hysteresis, while the slope of the transition between Mute and Operating modes is
determined by the time-constant of the RC network on pin MODE; see Figure 8.
[6] DC output offset voltage is gradually applied to the output during the transition between Mute and Operating modes. The slope caused
by any DC output offset is determined by the time-constant of the RC network on pin MODE.
[7] At a junction temperature of approximately Tact(th_fold) −5°C, gain reduction commences and at a junction temperature of approximately
Tact(th_prot), the amplifier switches off.
Table 8. Static characteristics
V
P
= ± 35 V; f
osc
= 345 kHz; T
amb
= 25 ° C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supply
VP[1] supply voltage Operating mode [2] ±12.5 ±30 ±40 V
VP(ovp) overvoltage protection supply voltage Standby, Mute modes;
VDD −VSS
85 - 90 V
VP(uvp) undervoltage protection supply voltage VDD −VSS 20 - 25 V
VP(ubp) unbalance protection supply voltage [3] -33-%
Iq(tot) total quiescent current Operating mode; no load; no
filter;noRC-snubbernetwork
connected
- 5075mA
Istb standby current measured at 30 V - 480 650 µA
Mode select input; pin MODE
VMODE voltage on pin MODE referenced to SGND [4] 0- 6V
Standby mode [4][5] 0 - 0.8 V
Mute mode [4][5] 2.2 - 3.0 V
Operating mode [4][5] 4.2 - 6 V
IIinput current VI= 5.5 V - 110 150 µA
Audio inputs; pins IN1M, IN1P, IN2P and IN2M
VIinput voltage DC input [4] -0-V
Amplifier outputs; pins OUT1 and OUT2
VO(offset) output offset voltage SE; Mute mode - - ±25 mV
SE; Operating mode [6] --±150 mV
BTL; Mute mode - - ±30 mV
BTL; Operating mode [6] --±210 mV
Stabilizer output; pin STABI
VO(STABI) output voltage on pin STABI Mute and Operating modes;
with respect to VSSD 9.3 9.8 10.3 V
Temperature protection
Tact(th_prot) thermal protection activation
temperature - 154 - °C
Tact(th_fold) thermal foldback activation
temperature closed loop SE voltage gain reduced with 6 dB [7] - 153 - °C

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 14 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
12. Dynamic characteristics
12.1 Switching characteristics
[1] VPis the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] When using an external oscillator, the frequency ftrack (500 kHz minimum, 900 kHz maximum) will result in a PWM frequency fosc
(250 kHz minimum, 450 kHz maximum) due to the internal clock divider; see Section 8.2.
[3] When tr(i) > 100 ns, the output noise floor will increase.
Fig 8. Behavior of mode selection pin MODE
Standby Mute On
5.5
coa021
VMODE (V)
4.23.02.20.80
VO(V)
VO(offset)(mute)
VO(offset)(on)
slope is directly related to the time-constant
of the RC network on the MODE pin
Table 9. Dynamic characteristics
V
P[1]
= ± 35 V; T
amb
= 25 ° C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Internal oscillator
fosc(typ) typical oscillator frequency ROSC = 30.0 kΩ290 345 365 kHz
fosc oscillator frequency 250 - 450 kHz
External oscillator input or frequency tracking; pin OSC
VOSC voltage on pin OSC HIGH-level SGND + 4.5 SGND + 5 SGND + 6 V
Vtrip trip voltage - SGND + 2.5 - V
ftrack tracking frequency [2] 500 - 900 kHz
Ziinput impedance 1 - - MΩ
Ciinput capacitance - - 15 pF
tr(i) input rise time from SGND + 0 V
SGND + 5 V [3] - - 100 ns

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 15 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
12.2 Stereo SE configuration characteristics
[1] VPis the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] RsL is the series resistance of the low-pass LC filter inductor used in the application.
[3] Output power is measured indirectly; based on RDSon measurement; see Section 13.3.
[4] THD measured between 22 Hz and 20 kHz, using AES17 20 kHz brick wall filter; max. limit is guaranteed but may not be 100 % tested.
[5] Vripple = Vripple(max) = 2 V (p-p); measured independently between VDDPn and SGND and between VSSPn and SGND.
[6] 22 Hz to 20 kHz, using AES17 20 kHz brick wall filter.
[7] 22 Hz to 20 kHz, using AES17 20 kHz brick wall filter.
Table 10. Dynamic characteristics
V
P[1]
= ± 35 V; R
L
= 4 Ω ; f
i
= 1 kHz; f
osc
= 345 kHz; R
sL[2]
< 0.1 Ω ; T
amb
= 25 ° C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Pooutput power Tj=85°C; LLC =22µH; CLC = 680 nF (see
Figure 10)[3]
THD + N = 10 %; RL=4Ω; VP=±39 V 170 W
THD + N = 0.5 %; RL= 4 Ω; VP=±37 V - 100 - W
THD + N = 10 %; RL= 4 Ω; VP=±37 V - 150 - W
THD + N = 10 %; RL= 6 Ω; VP= ±37 V - 100 - W
THD total harmonic distortion Po= 1 W; fi= 1 kHz [4] - 0.05 - %
Po= 1 W; fi= 6 kHz [4] - 0.05 - %
Gv(cl) closed-loop voltage gain 29 30 31 dB
SVRR supply voltage ripple rejection between pins VDDPn and SGND
Operating mode; fi= 100 Hz [5] -90-dB
Operating mode; fi= 1 kHz [5] -70-dB
Mute mode; fi= 100 Hz [5] -75-dB
Standby mode; fi= 100 Hz [5] - 120 - dB
between pins VSSPn and SGND
Operating mode; fi= 100 Hz [5] -80-dB
Operating mode; fi= 1 kHz [5] -60-dB
Mute mode; fi= 100 Hz [5] -80-dB
Standby mode; fi= 100 Hz [5] - 115 - dB
Ziinput impedance between one of the input pins and SGND 45 63 - kΩ
Vn(o) output noise voltage Operating mode; Rs=0Ω[6] - 160 - µV
Mute mode [7] -85-µV
αcs channel separation [8] -70-dB
|∆Gv|voltage gain difference - - 1 dB
αmute mute attenuation fi= 1 kHz; Vi= 2 V (RMS) [9] -75-dB
CMRR common mode rejection ratio Vi(CM) = 1 V (RMS) - 75 - dB
ηpo output power efficiency SE, RL= 4 Ω-88-%
SE, RL= 6 Ω-90-%
BTL, RL= 8 Ω-88-%
RDSon(hs) high-side drain-source on-state
resistance [10] - 200 - mΩ
RDSon(ls) low-side drain-source on-state
resistance [10] - 190 - mΩ

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 16 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
[8] Po= 1 W; fi= 1 kHz.
[9] Vi= Vi(max) = 1 V (RMS); fi= 1 kHz.
[10] Leads and bond wires included.
12.3 Mono BTL application characteristics
[1] VPis the supply voltage on pins VDDP1, VDDP2 and VDDA.
[2] RsL is the series resistance of the low-pass LC filter inductor used in the application.
[3] Output power is measured indirectly; based on RDSon measurement; see Section 13.3.
[4] THD measured between 22 Hz and 20 kHz, using AES17 20 kHz brick wall filter; max. limit is guaranteed but may not be 100 % tested.
[5] Vripple = Vripple(max) = 2 V (p-p).
[6] 22 Hz to 20 kHz, using an AES17 20 kHz brick wall filter; low noise due to BD modulation.
[7] 22 Hz to 20 kHz, using an AES17 20 kHz brick wall filter.
[8] Vi= Vi(max) = 1 V (RMS); fi= 1 kHz.
Table 11. Dynamic characteristics
V
P[1]
= ± 35 V; R
L
= 8 Ω ; f
i
= 1 kHz; f
osc
= 345 kHz; R
sL[2]
< 0.1 Ω ; T
amb
= 25 ° C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Pooutput power Tj=85°C; LLC =22µH; CLC = 680 nF (see
Figure 10)[3]
THD + N = 10 %; RL= 8 Ω; VP=±39 V - 340 - W
THD + N = 0.5 %; RL= 8 Ω; VP=±37 V - 200 - W
THD + N = 10 %; RL= 8 Ω; VP=±37 V - 300 - W
THD total harmonic distortion Po= 1 W; fi= 1 kHz [4] - 0.05 - %
Po= 1 W; fi= 6 kHz [4] - 0.05 - %
Gv(cl) closed-loop voltage gain - 36 - dB
SVRR supply voltage ripple rejection between pin VDDPn and SGND
Operating mode; fi= 100 Hz [5] -80-dB
Operating mode; fi= 1 kHz [5] -80-dB
Mute mode; fi= 100 Hz [5] -95-dB
Standby mode; fi= 100 Hz [5] - 120 - dB
between pin VSSPn and SGND
Operating mode; fi= 100 Hz [5] -75-dB
Operating mode; fi= 1 kHz [5] -75-dB
Mute mode; fi= 100 Hz [5] -90-dB
Standby mode; fi= 100 Hz [5] - 130 - dB
Ziinput impedance measured between one of the input pins and
SGND 45 63 - kΩ
Vn(o) output noise voltage Operating mode; Rs=0Ω[6] - 190 - µV
Mute mode [7] -45-µV
αmute mute attenuation fi= 1 kHz; Vi= 2 V (RMS) [8] -75-dB
CMRR common mode rejection ratio Vi(CM) = 1 V (RMS) - 75 - dB

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 17 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
13. Application information
13.1 Mono BTL application
When using the power amplifier in a mono BTL application, the inputs of the two channels
must be connected in parallel and the phase of one of the inputs must be inverted; see
Figure 7. In principle, the loudspeaker can be connected between the outputs of the two
single-ended demodulation filters.
13.2 Pin MODE
To ensure a pop noise-free start-up, an RC time-constant must be applied to pin MODE.
The bias-current setting of the VI converter input is directly related to the voltage on pin
MODE. In turn the bias-current setting of the VI converters is directly related to the DC
output offset voltage. A slow dV/dt on pin MODE results in a slow dV/dt for the DC output
offset voltage, ensuring a pop noise-free transition between Mute and Operating modes. A
time-constant of 500 ms is sufficient to guarantee pop noise-free start-up; see Figure 4,
Figure 5 and Figure 8 for more information.
13.3 Estimating the output power
13.3.1 Single-Ended (SE)
Maximum output power:
(1)
Maximum output current is internally limited to 9.2 A:
(2)
Where:
•Po(0.5 %): output power at the onset of clipping
•RL: load impedance
•RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent)
•RsL: series impedance of the filter coil
•VP: single-sided supply voltage or 0.5 ×(VDD + |VSS|)
•tw(min): minimum pulse width (typical 150 ns, temperature dependent)
•fosc: oscillator frequency
Remark: Note that Io(peak) should be less than 9.2 A (Section 8.3.2). Io(peak) is the sum of
the current through the load and the ripple current. The value of the ripple current is
dependent on the coil inductance and the voltage drop across the coil.
Po 0.5%()
RL
RLRDSon hs() RsL ++
-----------------------------------------------------VP1t
w min()
0.5×fosc –()×× 2
2RL
-----------------------------------------------------------------------------------------------------------------------------------------
=
Iopeak()
VP1t
w min()
0.5 f osc ×–()×
RLRDSon hs() RsL ++
---------------------------------------------------------------------
=

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 18 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
13.3.2 Bridge-Tied Load (BTL)
Maximum output power:
(3)
Maximum output current internally limited to 9.2 A:
(4)
Where:
•Po(0.5 %): output power at the onset of clipping
•RL: load impedance
•RDSon(hs): high-side RDSon of power stage output DMOS (temperature dependent)
•RDSon(ls): low-side RDSson of power stage output DMOS (temperature dependent)
•RsL: series impedance of the filter coil
•VP: single-sided supply voltage or 0.5 ×(VDD + |VSS|)
•tw(min): minimum pulse width (typical 150 ns, temperature dependent)
•fosc: oscillator frequency
Remark: Note that Io(peak) should be less than 9.2 A; see Section 8.3.2.I
o(peak) is the sum
of the current through the load and the ripple current. The value of the ripple current is
dependent on the coil inductance and the voltage drop across the coil.
13.4 External clock
To ensure duty cycle-independent operation, the external clock frequency is divided by
two internally. The external clock frequency is therefore twice the internal clock frequency
(typically 2 ×350 kHz = 700 kHz).
If several Class D amplifiers are used in a single application, it is recommended that all
the devices run at the same switching frequency. This can be achieved by connecting the
OSC pins together and feeding them from an external oscillator. When using an external
oscillator, it is necessary to force pin OSC to a DC level above SGND. This disables the
internal oscillator and causes the PWM to switch at half the external clock frequency.
The internal oscillator requires an external resistor ROSC, connected between pin OSC
and pin VSSA. ROSC must be removed when using an external oscillator.
The noise generated by the internal oscillator is supply voltage dependent. An external
low-noise oscillator is recommended for low-noise applications running at high supply
voltages.
Po 0.5%()
RL
RLRDSon hs() RDSon ls() ++
------------------------------------------------------------------- 2VP1t
wmin()
0.5 f osc ×–()×× 2
2RL
-----------------------------------------------------------------------------------------------------------------------------------------------------------
=
Iopeak() 2VP1t
w min()
0.5 f osc ×–()×
RLRDSon hs() RDSon ls() +()2RsL ++
-------------------------------------------------------------------------------------------
=

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 19 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
13.5 Heatsink requirements
An external heatsink must be connected to the TDA8950.
Equation 5 defines the relationship between maximum power dissipation before activation
of TFB and total thermal resistance from junction to ambient.
(5)
Power dissipation (P) is determined by the efficiency of the TDA8950. Efficiency
measured as a function of output power is given in Figure 20. Power dissipation can be
derived as a function of output power as shown in Figure 19.
(1) Rth(j-a) = 5 K/W.
(2) Rth(j-a) = 10 K/W.
(3) Rth(j-a) = 15 K/W.
(4) Rth(j-a) = 20 K/W.
(5) Rth(j-a) = 35 K/W.
Fig 9. Derating curves for power dissipation as a function of maximum ambient
temperature
Rth ja–() TjTamb
–
P
------------------------
=
P
(W)
30
20
10
0
Tamb (°C)
(1)
(2)
(3)
(4)
(5)
0 20 10040 60 80
mbl469

TDA8950_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 11 June 2009 20 of 39
NXP Semiconductors TDA8950
2×150 W class-D power amplifier
In the following example, a heatsink calculation is made for an 8 ΩBTL application with a
±30 V supply:
The audio signal has a crest factor of 10 (the ratio between peak power and average
power (20 dB)); this means that the average output power is 1⁄10 of the peak power.
Thus, the peak RMS output power level is the 0.5 % THD level, i.e. 170 W.
The average power is then 1⁄10 ×170W=17W.
The dissipated power at an output power of 17 W is approximately 7 W.
When the maximum expected ambient temperature is 50 °C, the total Rth(j-a) becomes
Rth(j-a) = Rth(j-c) + Rth(c-h) + Rth(h-a)
Rth(j-c) (thermal resistance from junction to case) = 1.1 K/W
Rth(c-h) (thermal resistance from case to heatsink) = 0.5 K/W to 1 K/W (dependent on
mounting)
So the thermal resistance between heatsink and ambient temperature is:
Rth(h-a) (thermal resistance from heatsink to ambient) = 14 −(1.1 + 1) = 11.9 K/W
The derating curves for power dissipation (for several Rth(j-a) values) are illustrated in
Figure 9. A maximum junction temperature Tj= 150 °C is taken into account. The
maximum allowable power dissipation for a given heatsink size can be derived, or the
required heatsink size can be determined, at a required power dissipation level; see
Figure 9.
13.6 Pumping effects
In a typical stereo single-ended configuration, the TDA8950 is supplied by a symmetrical
supply voltage (e.g. VDD = 30 V and VSS =−30 V). When the amplifier is used in an SE
configuration, a ‘pumping effect’ can occur. During one switching interval, energy is taken
from one supply (e.g. VDD), while a part of that energy is returned to the other supply line
(e.g. VSS) and vice versa. When the voltage supply source cannot sink energy, the voltage
across the output capacitors of that voltage supply source increases and the supply
voltage is pumped to higher levels. The voltage increase caused by the pumping effect
depends on:
•Speaker impedance
•Supply voltage
•Audio signal frequency
•Value of supply line decoupling capacitors
•Source and sink currents of other channels
Pumping effects should be minimized to prevent the malfunctioning of the audio amplifier
and/or the voltage supply source. Amplifier malfunction due to the pumping effect can
trigger UVP, OVP or UBP.
148 50–()
7
------------------------- 14 K/W=