Philips Triple high-speed Analog-to-Digital Converter 110 Msps... User manual

TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Rev. 03 — 21 July 2000 Product specification
c
c
1. General description
The TDA8752B is a triple 8-bit ADC with controllable amplifiers and clamps for the
digitizing of large bandwidth RGB signals.
The clamp level, the gain and all other settings are controlled via a serial interface
(either I2C-bus or 3-wire serial bus, selected via a logic input).
The IC also includes a PLL that can be locked to the horizontal line frequency and
generates the ADC clock. The PLL jitter is minimized for high resolution PC graphics
applications. An external clock can also be input to the ADC.
It is possible to set the TDA8752B serial bus address to four different values, when
several TDA8752B ICs are used in a system, by means of the I2C-bus interface (for
example, two ICs used in an odd/even configuration).
2. Features
■Triple 8-bit ADC
■Sampling rate up to 110 Msps
■IC controllable via a serial interface, which can be either I2C-bus or 3-wire serial
bus, selected via a TTL input pin
■IC analog voltage input from 0.4 to 1.2 V (p-p) to produce a full-scale ADC input of
1 V (p-p)
■Three clamps for programming a clamping code between −63.5 and +64 in steps
of 1⁄2LSB for RGB signals, and from +120 to +136 in steps of 1⁄2LSB for YUV
signals
■Three controllable amplifiers: gain controlled via the serial interface to produce a
full-scale resolution of 1⁄2LSB peak-to-peak
■Amplifier bandwidth of 250 MHz
■Low gain variation with temperature
■PLL controllable via the serial interface to generate the ADC clock which can be
locked to a line frequency of 15 to 280 kHz
■Integrated PLL divider
■Programmable phase clock adjustment cells
■Internal voltage regulators
■TTL compatible digital inputs and outputs
■Chip enable high-impedance ADC output

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 2 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
■Power-down mode
■Possibility to use up to four ICs in the same system when using the I2C-bus
interface, or more when using the 3-wire serial bus interface
■1.1 W power dissipation.
3. Applications
■RGB high-speed digitizing
■LCD panels drive
■LCD projection systems
■VGA and higher resolutions
■Using two ICs in parallel, a higher display resolution can be obtained: 200 MHz
pixel frequency.
4. Quick reference data
Table 1: Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VCCA analog supply voltage for R, G and B channels 4.75 5.0 5.25 V
VDDD logic supply voltage for I2C-bus and 3-wire
serial bus 4.75 5.0 5.25 V
VCCD digital supply voltage 4.75 5.0 5.25 V
VCCO output stages supply voltage for R, G and B channels 4.75 5.0 5.25 V
VCCA(PLL) analog PLL supply voltage 4.75 5.0 5.25 V
VCCO(PLL) output PLL supply voltage 4.75 5.0 5.25 V
ICCA analog supply current −120 −mA
IDDD logic supply current for I2C-bus and 3-wire −1.0 −mA
ICCD digital supply current −40 −mA
ICCO output stages supply current fclk = 110 MHz; ramp input −26 −mA
ICCA(PLL) analog PLL supply current −28 −mA
ICCO(PLL) output PLL supply current −5−mA
fclk clock frequency −−110 MHz
fref(PLL) PLL reference clock
frequency 15 −280 kHz
fVCO VCO output clock frequency 12 −110 MHz
INL DC integral non-linearity from analog input to digital
output; full-scale; ramp
input; fclk = 110 MHz
−±0.5 ±1.5 LSB
DNL DC differential non-linearity from analog input to digital
output; full-scale; ramp
input; fclk = 110 MHz
−±0.5 ±1.0 LSB
∆Gamp/∆T amplifier gain stability as a
function of temperature Vref = 2.5 V with 100 ppm/°C maximum −−200 ppm/°C
B amplifier bandwidth −3 dB; Tamb =25°C 250 −−MHz
tset settling time of the ADC block
plus AGC input signal settling time <1 ns; Tamb =25°C−−6ns

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 3 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
5. Ordering information
DRPLL PLL divider ratio 100 −4095
Ptot total power dissipation fclk = 110 MHz; ramp input −1.1 −W
jPLL(rms) maximum PLL phase jitter
(RMS value) fref = 66.67 kHz; fclk = 110 MHz −112 −ps
Table 1: Quick reference data
…continued
Symbol Parameter Conditions Min Typ Max Unit
Table 2: Ordering information
Type number Package Sampling
frequency (MHz)
Name Description Version
TDA8752BH/8 QFP100 plastic quad flat package; 100 leads (lead length
1.95 mm); body 14 ×20 ×2.8 mm SOT317-2 110

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 4 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
6. Block diagram
Fig 1. Block diagram.
FCE467
SERIAL
INTERFACE
I
2
C-BUS
OR
3-WIRE
I
2
C/3W
I
2
C-bus; 1-bit
(Hlevel)
REGULATOR
PLL
PWDWN CP CZ
CKREF
COAST
INV
CKEXT
CKREFO
CKAO
CKBO
CKADCO
B0 to B7
BOR
R0 to R7
OE
G0 to G7
BBOT
BCLP
RBOT
RCLP
GBOT
GCLP
DEC2DEC1HSYNCn.c.
HSYNCI
ADD2
BIN
BGAINC
BAGC
GAGC
Vref
RDEC
RIN
RGAINC
RAGC
GDEC
GIN
GGAINC
BDEC
ADD1
SEN
SCL
SDA
DIS
BLUE CHANNEL
GREEN CHANNEL
TDA8752B
RED CHANNEL
ADC
GOR
ROR
MUX
CLAMP
OUTPUTS
6
VCCA(R)
11
VCCA(G)
19
VCCA(B)
27
VDDD
40
AGNDG
21
VCCO(G)
69
VCCO(B)
59
VCCO(R)
79
VCCD
95
VCCA(PLL)
99
VCCO(PLL)
85
CLP
89
AGNDR
13
VSSD
41
AGNDB
29
OGNDG
60
OGNDR
70
AGNDPLL
96
OGNDB
48
DGND
86
OGNDPLL
82
12
10
3
22
24
28
26
20
18
14
16
33
34
38
TDO
TCK 35
36
42
39
37
90
1, 5, 30, 31, 43 , 44
50, 51, 100 4 2 88 97 98
32
8
9
7
71 to 78
45
17
15
61 to 68
87
46
25
23
49, 52 to 58
47
93
94
92
80
91
84
83
81

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 5 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
Fig 2. Red channel diagram.
150
kΩ
RIN
VP
VCCAR
RCLP
CLP RAGC
CLKADC
Vref
3 kΩ
45 kΩDAC
5
DAC
ROR
R0 to R7
OE
RBOT
RGAINC
HSYNCI
ADC
D
R
D ≥ R
REGISTER
I2C-BUS
FCE468
OUTPUTS
MUX AGC
CLAMP
CONTROL
REGISTER
FINE GAIN ADJUST
I2C-bus:5 bits (Fr) I2C-bus: 7 bits (Cr)
I2C-bus:8 bits (Or)
REGISTER
COARSE GAIN ADJUST
1
8
8
7
8
1
8

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 6 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
Fig 3. PLL diagram.
FCE465
PHASE
FREQUENCY
DETECTOR
I
2
C-bus; 5 bits
(Ip, Up, Do)
I
2
C-bus; 1 bit
(Vlevel)
I
2
C-bus;12 bits (Di) I
2
C-bus;
1 bit (Ckb)
phase selector A
I
2
C-bus;
5 bits (Pa) I
2
C-bus;
1 bit (Cka)
I
2
C-bus;
1 bit (Ckab)
edge selector
I
2
C-bus;
1 bit
(Edge) CLKADC
I
2
C-bus;
2 bits (Vco)
CZ
loop filter
I
2
C-bus;
3 bits (Z)
12 to
100 MHz
DIV N (100 to 4095)
0°/180°
MUX
SYNCHRO
MUX
MUX
NCKBO
CP
CZ CP
COAST CKEXT INV
VCO CKADCO
CKAO
CKREFO
CKREF
phase selector B
I
2
C-bus;5 bits (Pb)
CKBO

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 7 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
7. Pinning information
7.1 Pinning
Fig 4. Pin configuration.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
5130
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
n.c.
AGNDB
BIN
VCCA(B)
BDEC
BCLP
BGAINC
BBOT
BAGC
AGNDG
GIN
VCCA(G)
GDEC
GCLP
GGAINC
GBOT
GAGC
AGNDR
RIN
VCCA(R)
RDEC
RCLP
RGAINC
RBOT
RAGC
n.c.
DEC1
Vref
DEC2
n.c.
n.c.
B1
B2
B3
B4
B5
B6
B7
VCCO(B)
OGNDG
G0
G1
G2
G3
G4
G5
G6
G7
VCCO(G)
OGNDR
R0
R1
R2
R3
R4
R5
R6
R7
VCCO(R)
CKREFO
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
n.c. VCCA(PLL) CZ CP AGNDPLL VCCD CKREF COAST CKEXT INV HSYNC CLP PWDWN OE DGND VCCO(PLL) CKADCO CKBO OGNDPLL CKAO
n.c.
I2C/3W
ADD1 ADD2
TCK
TDO
DIS
SEN SDA
VDDD
VSSD
SCL
n.c. n.c.
ROR
GOR
BOR
OGNDB
B0
n.c.
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
FCE469
TDA8752BH

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 8 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
7.2 Pin description
Table 3: Pin description
Symbol Pin Description
n.c. 1 not connected
DEC2 2 main regulator decoupling input 2
Vref 3 gain stabilizer voltage reference input
DEC1 4 main regulator decoupling input 1
n.c. 5 not connected
RAGC 6 red channel AGC output
RBOT 7 red channel ladder decoupling input (BOT)
RGAINC 8 red channel gain capacitor input
RCLP 9 red channel gain clamp capacitor input
RDEC 10 red channel gain regulator decoupling input
VCCA(R) 11 red channel gain analog power supply
RIN 12 red channel gain analog input
AGNDR13 red channel gain analog ground
GAGC 14 green channel AGC output
GBOT 15 green channel ladder decoupling input (BOT)
GGAINC 16 green channel gain capacitor input
GCLP 17 green channel gain clamp capacitor input
GDEC 18 green channel gain regulator decoupling input
VCCA(G) 19 green channel gain analog power supply
GIN 20 green channel gain analog input
AGNDG21 green channel gain analog ground
BAGC 22 blue channel AGC output
BBOT 23 blue channel ladder decoupling input (BOT)
BGAINC 24 blue channel gain capacitor input
BCLP 25 blue channel gain clamp capacitor input
BDEC 26 blue channel gain regulator decoupling input
VCCA(B) 27 blue channel gain analog power supply
BIN 28 blue channel gain analog input
AGNDB29 blue channel gain analog ground
n.c. 30 not connected
n.c. 31 not connected
I2C/3W 32 selection input between I2C-bus (active HIGH) and 3-wire
serial bus (active LOW)
ADD1 33 I2C-bus address control input 1
ADD2 34 I2C-bus address control input 2
TCK 35 scan test mode input (active HIGH)
TDO 36 scan test output
DIS 37 I2C-bus and 3-wire serial bus disable control input (disable at
HIGH level)
SEN 38 select enable for 3-wire serial bus input (see Figure 10)

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 9 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
SDA 39 I2C-bus/3-wire serial bus data input
VDDD 40 logic I2C-bus/3-wire serial bus digital power supply
VSSD 41 logic I2C-bus/3-wire serial bus digital ground
SCL 42 I2C-bus/3-wire serial bus clock input
n.c. 43 not connected
n.c. 44 not connected
ROR 45 red channel ADC output bit out of range
GOR 46 green channel ADC output bit out of range
BOR 47 blue channel ADC output bit out of range
OGNDB48 blue channel ADC output ground
B0 49 blue channel ADC output bit 0 (LSB)
n.c. 50 not connected
n.c. 51 not connected
B1 52 blue channel ADC output bit 1
B2 53 blue channel ADC output bit 2
B3 54 blue channel ADC output bit 3
B4 55 blue channel ADC output bit 4
B5 56 blue channel ADC output bit 5
B6 57 blue channel ADC output bit 6
B7 58 blue channel ADC output bit 7 (MSB)
VCCO(B) 59 blue channel ADC output power supply
OGNDG60 green channel ADC output ground
G0 61 green channel ADC output bit 0 (LSB)
G1 62 green channel ADC output bit 1
G2 63 green channel ADC output bit 2
G3 64 green channel ADC output bit 3
G4 65 green channel ADC output bit 4
G5 66 green channel ADC output bit 5
G6 67 green channel ADC output bit 6
G7 68 green channel ADC output bit 7 (MSB)
VCCO(G) 69 green channel ADC output power supply
OGNDR70 red channel ADC output ground
R0 71 red channel ADC output bit 0 (LSB)
R1 72 red channel ADC output bit 1
R2 73 red channel ADC output bit 2
R3 74 red channel ADC output bit 3
R4 75 red channel ADC output bit 4
R5 76 red channel ADC output bit 5
R6 77 red channel ADC output bit 6
R7 78 red channel ADC output bit 7 (MSB)
VCCO(R) 79 red channel ADC output power supply
Table 3: Pin description …continued
Symbol Pin Description

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 10 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
CKREFO 80 reference output clock re-synchronized horizontal pulse
CKAO 81 PLL clock output 3 (in phase with reference output clock
CKAO or CKBO)
OGNDPLL 82 PLL digital ground
CKBO 83 PLL clock output 2
CKADCO 84 PLL clock output 1 (in phase with internal ADC clock)
VCCO(PLL) 85 PLL output power supply
DGND 86 digital ground
OE 87 output enable; active LOW (when OE is HIGH, the outputs are
in high-impedance)
PWDWN 88 power-down control input (device is in Power-down mode
when this pin is HIGH)
CLP 89 clamp pulse input (clamp active HIGH)
HSYNC 90 horizontal synchronization input pulse
INV 91 PLL clock output inverter command input (invert when HIGH)
CKEXT 92 external clock input
COAST 93 PLL coast command input
CKREF 94 PLL reference clock input
VCCD 95 digital power supply
AGNDPLL 96 PLL analog ground
CP 97 PLL filter input
CZ 98 PLL filter input
VCCA(PLL) 99 PLL analog power supply
n.c. 100 not connected
Table 3: Pin description
…continued
Symbol Pin Description

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 11 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
8. Functional description
This triple high-speed 8-bit ADC is designed to convert RGB signals, coming from an
analog source, into digital data used by a LCD driver (pixel clock up to 200 MHz when
using 2 ICs).
8.1 IC analog video inputs
The video inputs are internally DC polarized. These inputs are AC coupled externally.
8.2 Clamps
Three independent parallel clamping circuits are used to clamp the video input
signals on the black level and to control the brightness level. The clamping code is
programmable between code −63.5 and +64 and from +120 to +136 in steps of
1⁄2LSB. The programming of the clamp value is achieved via an 8-bit DAC. Each
clamp must be able to correct an offset from ±0.1 V to ±10 mV within 300 ns, and
correct the total offset in 10 lines.
The clamps are controlled by an external TTL positive going pulse (pin CLP). The
drop of the video signal is <1 LSB.
Normally, the circuit operates with a 0 code clamp, corresponding to the 0 ADC code.
This clamp code can be changed from −63.5 to +64 as represented in Figure 5, in
steps of 1⁄2LSB. The digitized video signal is always between code 0 and code 255 of
the ADC. It is also possible to clamp from code 120 to code 136 corresponding to
120 ADC code to 136 ADC code. Then clamping on code 128 of the ADC is possible.
8.3 Variable gain amplifiers
Three independent variable gain amplifiers are used to provide, to each channel, a
full-scale input range signal to the 8-bit ADC. The gain adjustment range is designed
so that for an input range varying from 0.4 to 1.2 V (p-p), the output signal
corresponds to the ADC full-scale input of 1 V (p-p).
To ensure that the gain does not vary over the whole operating temperature range, an
external supplied reference voltage Vref = 2.5 V (DC), with a maximum variation of
100 ppm/°C, is used to calibrate the gain at the beginning of each video line before
the clamp pulse.
Fig 5. Clamp definition.
digitized
video
signal
video signal
CLP
clamp
programming
code 64
code 0
255
= 120 to 136
code−63.5
FCE471

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 12 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
The calibration of the gains is done using the following principle.
From the reference voltage Vref a reference signal of 0.156 V (p-p) (1⁄16Vref) is
generated internally. During the synchronization part of the video line, the multiplexer,
controlled by the TTL synchronization signal (HSYNCI, coming from HSYNC;
see Figure 1) with a width equal to one of the video synchronization signals (e.g. the
signal coming from a synchronization separator), is switched between the two
amplifiers.
The output of the multiplexer is either the normal video signal or the 0.156 V
reference signal (during HSYNC).
The corresponding ADC outputs are then compared to a preset value loaded in a
register. Depending on the result of the comparison, the gain of the variable gain
amplifiers is adjusted (coarse gain control; see Figure 2 and 6). The three 7-bit
registers receive data via a serial interface to enable the gain to be programmed.
The preset value loaded in the 7-bit register is chosen between approximately
67 codes to ensure the full-scale input range (see Figure 6). A contrast control can be
achieved using these registers. In this case care should be taken to stay within the
allowed code range (32 to 99).
A fine correction using three 5-bit DACs, also controlled via the serial interface, is
used to fine tune the gain of the three channels (fine gain control; see Figure 2 and 7)
and to compensate the channel-to-channel gain mismatch.
With a full-scale ADC input, the resolution of the fine register corresponds to 1⁄2LSB
peak-to-peak variation.
To use these gain controls correctly, it is recommended to fix the coarse gain (to have
a full-scale ADC input signal) to within 4 LSB and then adjust it with the fine gain. The
gain is adjusted during HSYNC. During this time the output signal is not related to the
amplified input signal. The outputs, when the coarse gain system is stable, are
related to the programmed coarse code (see Figure 6).
Fig 6. Coarse gain control.
FCE472
128
160
227
255
0
32
99
127 G(max) G(min)
ADC output
code
NCOARSE
code
coarse
register
value
(67 codes)
0.2 0.6 Vi (p-p)
2
0.156 = Vref
16

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 13 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
8.4 ADCs
The ADCs are 8-bit with a maximum clock frequency of 110 Msps. The ADCs input
range is 1 V (p-p) full-scale. One out of range bit exists per channel (ROR, GOR and
BOR). It will be at logic 1 when the signal is out of range of the full-scale of the ADCs.
Pipeline delay in the ADCs is 1 clock cycle from sampling to data output.
The ADCs reference ladders regulators are integrated.
8.5 ADC outputs
ADC outputs are straight binary. An output enable pin (OE; active LOW) enables the
output status between active and high-impedance (OE = HIGH) to be switched; it is
recommended to load the outputs with a 10 pF capacitive load. The timing must be
checked very carefully if the capacitive load is more than 10 pF.
8.6 Phase-locked loop
The ADCs are clocked either by an internal PLL locked to the CKREF clock (all of the
PLL is on-chip except the loop filter capacitance) or by an external clock applied to
pin CKEXT. Selection is performed via the serial interface bus.
The reference clock (CKREF) range is between 15 and 280 kHz. Consequently, the
VCO minimum frequency is 12 MHz and the maximum frequency is 110 MHz. The
gain of the VCO part can be controlled via the serial interface, depending on the
frequency range to which the PLL is locked.
To increase the bandwidth of the PLL, the charge pump current, controlled by the
serial interface, must also be increased. The relationship between the frequency and
the current is given by the following equation:
(1)
Fig 7. Fine gain correction for a coarse gain GNCOARSE.
FCE473
128
160
227
255 G(max)
GNCOARSE
NCOARSE
G(min)
ADC
output code
coarse
register
value
(67 codes)
NFINE = 31
NFINE = 0 Vref
fn1
2π
------ KOIP
⋅
CZCP +()DR⋅
--------------------------------------⋅=

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 14 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
Where:
fn= the natural PLL frequency
KO= the VCO gain
DR = PLL divider ratio
CZand CP= capacitors of the PLL filter.
The other PLL equation is as follows:
(2)
Where:
fz= loop filter zero frequency
R = the chosen resistance for the filter
ξ= the damping factor
FO= 0 dB loop gain frequency.
Different resistances for the filter can be programmed via the serial interface. To
improve the performances, the PLL parameters should be chosen so that:
(3)
(4)
The values of R and IPmust be chosen so that the product is the closest to Lim. In
the event that there are several choices, the couple for which the ξvalue is the closest
to 1 must be chosen.
A software program called “PLL calculator’” is available on Philips Semiconductor
Internet site to calculate the best PLL parameters.
It is possible to control (independently) the phase of the ADC clock and the phase of
an additional clock output (which could be used to drive a second TDA8752B). For
this, two serial interface-controlled digital phase-shift controllers are included
(controlled by 5-bit registers, phase-shift controller steps are 11.25 deg each on the
whole PLL frequency range).
CKREF is re-synchronized, by the synchro block, on the CKAO clock. The output is
CKREFO (LOW during 8 clock periods). CKAO is the clock at the output of the phase
selector A. This clock can be used as the clocks for CKBO and CKADCO. The timing
is given in Figure 8.
Pin COAST is used to disconnect the PLL phase frequency detector during the frame
flyback or the unavailability of the CKREF signal. This signal can normally be derived
from the VSYNC signal.
The clock output is able to drive an external 10 pF load (for the on-chip ADCs).
fz1
2πR×CZ ×
------------------------------and ξ1
2
---fn
fz
-----
×=


=
F
O2ξfn
⋅RI
P
⋅⇒ 2πDR×FO
×
KO
-----------------------------------
==
FO
fref
----------0.15 R IP0.3πDR×fref
×
KO
------------------------------------------
≤⋅⇒≤ Lim=

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 15 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
The PLL can be used in three different methods:
•The IC can be used as stand-alone with a sampling frequency of up to 110 MHz.
•When an RGB signal is at a pixel frequency exceeding 100 to 200 MHz, it is
possible to follow one of the two possibilities given below:
–Using one TDA8752B: the sampling rate can be reduced by a factor of two, by
sampling the even pixels in the even frame and the odd pixels in the odd frame.
Pin INV is used to toggle between the frames.
–Using two TDA8752Bs: the PLL of the master TDA8752B is used to drive both
ADC clocks. The PLL of the slave TDA8752B is disconnected and the CKBO of
the master TDA8752B is connected to pin CKEXT of the TDA8752B master and
CKAO to the slave TDA8752B. In this case, on pin CKAO CKBO will be the
output (with bit CKAB of the master at logic 1).
The master TDA8752B is used to sample the even pixels and the slave
TDA8752B for odd pixels, using a 180 deg phase shift between the clocks (both
pins CKADCO). The master chip and the slave chip have their pin INV LOW,
which guarantees the 180 deg shift ADC clock drive. It is then necessary to
adjust phase B of the master chip. Special care should be taken with the quality
of the input signal (input settling time).
If CKREFO output signal at the master chip is needed, it is possible to use one
of the two phase A values in order to avoid set-up and hold problems in the
SYNCHRO function; e.g. PHASEA = 100000 and PHASEA = 111111.
•When INV is LOW, CKADCO is equal to CKEXT inverted.
tCKAO =t
CLK(buffer) +t phase selector [tCLK(buffer) = 10 ns and tphase selector =].
tCKREFO = either tCKAO −if PHASEA ≥01000 or tCKAO + if PHASEA < 01000.
Fig 8. Timing diagram.
tCKAO
tCKREFO
FCE470
CKAO
CKREFO
CKREF
tphase selector
2π
---------------------------TCLK(pixel)
×
TCLK(pixel)
2
------------------------ TCLK(pixel)
2
------------------------

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 16 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
8.7 I2C-bus and 3-wire serial bus interface
The I2C-bus and 3-wire serial buses control the status of the different control DACs
and registers. Control pin DIS enables or disables the full serial interface function
(disable at HIGH level). Four ICs can be used in the same system and programmed
by the same bus. Therefore, two pins (ADD1 and ADD2) are available to set each
address respectively, for use with the I2C-bus interface. All programming is described
in Section 9 “I2C-bus and 3-wire serial bus interfaces”.
Slave at 180 deg phase shift with respect to pin CKADCO of the master TDA8752B.
Fig 9. Dual TDA8752B solution for pixel clock rate with a single phase adjustment (100 to 200 MHz).
FCE466
I
2
C-bus;
1 bit (Ckb)
(Ckb = 1)
phase selector A
I
2
C-bus;
5 bits (Pa) I
2
C-bus;
1 bit (Cka)
(Cka = 1)
CLKADC
12 to
100 MHz
PLL
Master TDA8752B
(even pixels)
0 /180
MUX
SYNCHRO
COAST CKEXT INV
CKADCO
CKAO
CKREFO
CKREF phase selector B
I
2
C-bus;5 bits (Pb)
CKBO
I
2
C-bus;
1 bit (Ckb)
(Ckb = 0)
phase selector A
I
2
C-bus;
5 bits (Pa) I
2
C-bus;
1 bit (Cka)
(Cka = 1)
CLKADC
12 to
100 MHz
PLL
Slave TDA8752B
(odd pixels)
0 /180
MUX
SYNCHRO
COAST CKEXT INV
CKADCO
CKAO
CKREFO
phase selector B
I
2
C-bus;5 bits (Pb)
CKBO
CKREF
I
2
C-bus;
1 bit (Ckab)
(Ckab = 1)
MUX
MUX
NCKBO
NCKBO
I
2
C-bus;
1 bit (Ckab)
(Ckab = 0)
MUX
MUX

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 17 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
9. I2C-bus and 3-wire serial bus interfaces
9.1 Register definitions
The configuration of the different registers is shown in Table 4.
All the registers are defined by a subaddress of 8 bits; bit A4 refers to the mode which
is used with the I2C-bus interface; bits Sa3 to Sa0 are the subaddresses of each
register.
Bit Mode, used only with the I2C-bus, enables two modes to be programmed:
Mode 0 if bit Mode = 0, each register is programmed independently by giving its
subaddress and its content
Mode 1 if bit Mode = 1, all the registers are programmed one after the other by
giving this initial condition (XXX1 1111) as the subaddress state; thus,
the registers are charged following the predefined sequence of 16 bytes
(from subaddress 0000 to 1101).
9.1.1 Offset register
This register controls the clamp level for the RGB channels. The relationship between
the programming code and the level of the clamp code is given in Table 5.
Table 4: I2C-bus and 3-wire serial bus registers
Function
name Subaddress Bit definition Default value
A7 A6 A5 A4 A3 A2 A1 A0 MSB LSB
SUBADDR −−−−−−−−X X X Mode Sa3 Sa2 Sa1 Sa0 XXX1 0000
OFFSETR XXXX0000Or7 Or6 Or5 Or4 Or3Or2Or1Or00111 1111
COARSER XXXX0001Or8 Cr6 Cr5 Cr4 Cr3Cr2Cr1Cr00010 0000
FINER XXXX0010X X X Fr4 Fr3 Fr2 Fr1 Fr0 XXX0 0000
OFFSETG XXXX0011Og7 Og6 Og5 Og4 Og3Og2Og1Og00111 1111
COARSEG XXXX0100Og8 Cg6 Cg5 Cg4 Cg3Cg2Cg1Cg00010 0000
FINEG XXXX0101X X X Fg4 Fg3Fg2Fg1Fg0XXX0 0000
OFFSETB XXXX0110Ob7 Ob6 Ob5 Ob4 Ob3Ob2Ob1Ob00111 1111
COARSEB XXXX0111Ob8 Cb6 Cb5 Cb4 Cb3Cb2Cb1Cb00010 0000
FINEB XXXX1000X X X Fb4 Fb3Fb2Fb1Fb0XXX0 0000
CONTROL XXXX1001VlevelHlevelEdge Up Do Ip2 Ip1 Ip0 0000 0100
VCO XXXX1010Z2 Z1 Z0 Vco1 Vco0 Di11 Di10 Di9 0110 0001
DIVIDER
(LSB) XXXX1011Di8 Di7 Di6 Di5 Di4 Di3Di2Di11001 0000
PHASEA XXXX1100X Di0 Cka Pa4 Pa3Pa2Pa1Pa0X000 0000
PHASEB XXXX1101X Ckab Ckb Pb4 Pb3 Pb2 Pb1 Pb0 X000 0000

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 18 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
The default programmed value is:
•Programmed code = 127
•Clamp code = 0
•ADC output = 0.
9.1.2 Coarse and fine registers
These two registers enable the gain control, the AGC gain with the coarse register
and the reference voltage with the fine register. The coarse register programming
equation is as follows:
(5)
Where: Vref = 2.5 V.
The gain correspondence is given in Table 6. The gain is linear with reference to the
programming code (NFINE = 0).
The default programmed value is as follows:
•NCOARSE =32
•Gain = 0.825
•Vito be full-scale = 1.212 V.
To modulate this gain, the fine register is programmed using the above equation. With
a full-scale ADC input, the fine register resolution is a 1⁄2LSB peak-to-peak
(see Table 7 for NCOARSE = 32).
Table 5: Coding
Programmed code Clamp code ADC output
0−63.5 underflow
1−63
2−62.5
... ...
127 0 0
... ... ...
254 63.5 63 or 64
255 64 64
256 120 120
... ... ...
287 136 136
Table 6: Gain correspondence (COARSE)
NCOARSE Gain Vito be full-scale (V)
32 0.825 1.212
99 2.5 0.4
GAIN NCOARSE 1+
Vref 1NFINE
32 16×
------------------
–


⋅
------------------------------------------------1
16
------
×NCOARSE 1+
Vref 512 NFINE –()⋅
-------------------------------------------------- 32×==

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 19 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
The default programmed value is: NFINE =0.
9.1.3 Control register
COAST and HSYNC signals can be inverted by setting the I2C-bus control bits
‘Vlevel’ and ‘Hlevel’ respectively. When ‘Vlevel’ and ‘Hlevel’ are set to zero
respectively, COAST and HSYNC are active HIGH.
The bit ‘Edge’ defines the rising or falling edge of CKREF to synchronize the PLL. It
will be on the rising edge if the bit is at logic 0 and on the falling edge if the bit is at
logic 1.
The bits ‘Up’ and ‘Do’ are used for the test, to force the charge pump current. These
bits have to be logic 0 during normal use.
The bits ‘Ip0’, ‘Ip1’ and ‘Ip2’ control the charge pump current, to increase the
bandwidth of the PLL, as shown in Table 8.
The default programmed value is as follows:
•Charge pump current = 100 µA
•Test bits: no test mode; bits ‘Up’ and ‘Do’ at logic 0
•Rising edge of CKREF: bit ‘Edge’ at logic 0
•COAST and HSYNC inputs are active HIGH: bits ‘Vlevel’ and ‘Hlevel’ at logic 0.
9.1.4 VCO register
The bits ‘Z2’, ‘Z1’ and ‘Z0’ enable the internal resistance for the VCO filter to be
selected.
Table 7: Gain correspondence (FINE)
NFINE Gain Vito be full-scale (V)
0 0.825 1.212
31 0.878 1.139
Table 8: Charge pump current control
Ip2 Ip1 Ip0 Current (µA)
0 0 0 6.25
0 0 1 12.5
01025
01150
100100
101200
110400
111700

Philips Semiconductors TDA8752B
Triple high-speed Analog-to-Digital Converter 110 Msps
Product specification Rev. 03 — 21 July 2000 20 of 38
9397 750 07338 © Philips Electronics N.V. 2000. All rights reserved.
The bits Vco1 and Vco0 control the VCO gain.
The default programmed value is as follows:
•Internal resistance = 16 kΩ
•VCO gain = 15 MHz/V.
Table 9: VCO register bits
Z2 Z1 Z0 Resistance (kΩ)
0 0 0 high impedance
001128
01032
01116
1008
1014
1102
1111
Table 10: VCO gain control
Vco1 Vco0 VCO gain (MHz/V) Pixel clock
frequency range
(MHz)
0 0 15 10to20
0 1 20 20to40
1 0 35 40to70
115070to110