Philips TDA9964 User manual

TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD
cameras
Rev. 03 — 16 January 2001 Objective specification
c
c
1. Description
The TDA9964 is a 12-bit analog-to-digital interface for CCD cameras. The device
includes a correlated double sampling circuit, PGA, clamp loops and a low-power
12-bit ADC together with its reference voltage regulator.
The PGA gain and the ADC input clamp level are controlled via the serial interface.
An additional DAC is provided for additional system controls; its output voltage range
is 1.0 V p-p, which is available at pin OFDOUT.
2. Features
■Correlated Double Sampling (CDS), Programmable Gain Amplifier (PGA), 12-bit
Analog-to-Digital Converter (ADC) and reference regulator included
■Fully programmable via a 3-wire serial interface
■Sampling frequency up to 30 MHz
■PGA gain range of 24 dB (in steps of 0.1 dB)
■Low power consumption of only 175 mW at 2.7 V
■Power consumption in standby mode of 4.5 mW (typ.)
■3.0 V operation and 2.5 to 3.6 V operation for the digital outputs
■All digital inputs accept 5 V signals
■Active control pulses polarity selectable via serial interface
■8-bit DAC included for analog settings
■TTL compatible inputs, CMOS compatible outputs.
3. Applications
■Low-power, low-voltage CCD camera systems.

Philips Semiconductors TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Objective specification Rev. 03 — 16 January 2001 2 of 23
9397 750 07918 © Philips Electronics N.V. 2001. All rights reserved.
4. Quick reference data
5. Ordering information
Table 1: Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VCCA analog supply voltage 2.7 3.0 3.6 V
VCCD digital supply voltage 2.7 3.0 3.6 V
VCCO digital outputs supply voltage 2.5 2.7 3.6 V
ICCA analog supply current all clamps active −60 −mA
ICCD digital supply current −3−mA
ICCO digital outputs supply current fpix = 30 MHz; CL= 10 pF; input ramp
response time is 800 µs−1−mA
ADCres ADC resolution −12 −bits
Vi(CDS)(p-p) maximum CDS input voltage
(peak-to-peak value) VCC = 2.85 V 650 −−mV
VCC ≥3.0 V 800 −−mV
fpix(max) maximum pixel frequency 30 −−MHz
fpix(min) minimum pixel frequency tbf −−MHz
DRPGA PGA dynamic range −24 −dB
Ntot(rms) total noise from CDS input to
ADC output PGA gain = 0 dB; see Figure 8 −1.5 −LSB
Ein(rms) equivalent input noise (RMS
value) gain=24dB −70 −µV
Ptot total power consumption VCCA =V
CCD =V CCO =3V −195 −mW
VCCA =V
CCD =V CCO = 2.7 V −175 −mW
Table 2: Ordering information
Type number Package
Name Description Version
TDA9964HL LQFP48 plastic low profile quad flat package; 48 leads; body 7 ×7×1.4 mm SOT313-2

Philips Semiconductors TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
9397 750 07918 © Philips Electronics N.V. 2001. All rights reserved. Objective specification Rev. 03 — 16 January 2001 3 of 23 6. Block diagram
Fig 1. Block diagram.
FCE515
12-bit ADC
REGULATOR
CDS CLOCK GENERATOR
BLANKING OUTPUT
BUFFER
37
38
27
26
25
28
29
30
31
32
33
34
35
36
39
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
OGND2
D1
D0
23
24
VCCO1
10 DCLPC
21 VCCD1
VCCO2
22 DGND1
3
AGND2
7
VCCA2
9
CPCDS2
8
CPCDS1
4
IN
5
AGND3
11
OFDOUT
14
VCCA3
OE
43
BLK
47
CLK
40
AGND6
2
AGND1
1
VCCA1
41
VCCA4
48
CLPDM
44
CLPOB
45
SHP
SHIFT
CORRELATED
DOUBLE
SAMPLING
7-BIT
REGISTER
8-BIT
REGISTER
8-BIT
REGISTER
16
15
OPGA OPGAC
12 6 13
TEST AGND4 AGND5
46
SHD
SERIAL
INTERFACE
17
18
19
SEN SCLK SDATA
20
VSYNC
42
STDBY
PGA
CLAMP
Vref
OFD DAC
DATA
FLIP-
FLOP
CLAMP
TDA9964
OGND1
BLACK
LEVEL
SHIFT
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Philips Semiconductors TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Objective specification Rev. 03 — 16 January 2001 4 of 23
9397 750 07918 © Philips Electronics N.V. 2001. All rights reserved.
7. Pinning information
7.1 Pinning
7.2 Pin description
Fig 2. Pin configuration.
1
2
3
4
5
6
7
8
9
10
11
36
35
34
33
32
31
30
29
28
27
26
13 14 15 16 17 18 19 20 21 22 23
48 47 46 45 44 43 42 41 40 39 38
12
24 37
25
TDA9964HL
FCE516
D9
D10
D11
D8
D7
D6
D4
D3
D2
D1
D0
VCCA1
AGND1
AGND2
IN
AGND3
AGND4
VCCA2
CPCDS1
CPCDS2
OFDOUT
TEST
D5
CLK
SHD
SHP
CLPOB
BLK
STDBY
AGND6
OGND2
OE
VCCO2
CLPDM
VCCA4
DCLPC
OPGAC
OPGA
AGND5
VCCA3
VCCD1 VCCO1
DGND1
SCLK
SEN
OGND1 VSYNC
SDATA
Table 3: Pin description
Symbol Pin Description
VCCA1 1 analog supply voltage 1
AGND1 2 analog ground 1
AGND2 3 analog ground 2
IN 4 input signal from CCD
AGND3 5 analog ground 3
AGND4 6 analog ground 4
VCCA2 7 analog supply voltage 2
CPCDS1 8 clamp storage capacitor pin 1
CPCDS2 9 clamp storage capacitor pin 2
DCLPC 10 regulator decoupling pin
OFDOUT 11 analog output of the additional 8-bit control DAC
TEST 12 test mode input pin (should be connected to AGND5)
AGND5 13 analog ground 5
VCCA3 14 analog supply 3

Philips Semiconductors TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Objective specification Rev. 03 — 16 January 2001 5 of 23
9397 750 07918 © Philips Electronics N.V. 2001. All rights reserved.
OPGA 15 PGA output (test pin)
OPGAC 16 PGA complementary output (test pin)
SDATA 17 serial data input for serial interface control
SCLK 18 serial clock input for serial interface
SEN 19 strobe pin for serial interface
VSYNC 20 vertical sync pulse input
VCCD1 21 digital supply voltage 1
DGND1 22 digital ground 1
VCCO1 23 output supply voltage 1
OGND1 24 digital output ground 1
D0 25 ADC digital output 0 (LSB)
D1 26 ADC digital output 1
D2 27 ADC digital output 2
D3 28 ADC digital output 3
D4 29 ADC digital output 4
D5 30 ADC digital output 5
D6 31 ADC digital output 6
D7 32 ADC digital output 7
D8 33 ADC digital output 8
D9 34 ADC digital output 9
D10 35 ADC digital output 10
D11 36 ADC digital output 11 (MSB)
OGND2 37 output digital ground 2
VCCO2 38 output supply voltage 2
OE 39 output enable control input (LOW: outputs active; HIGH:
outputs are high impedance)
AGND6 40 analog ground 6
VCCA4 41 analog supply voltage 4
STDBY 42 standby mode control input (LOW: TDA9964 active; HIGH:
TDA9964 standby)
BLK 43 blanking control input
CLPOB 44 clamp pulse input at optical black
SHP 45 preset sample-and-hold pulse input
SHD 46 data sample-and-hold pulse input
CLK 47 data clock input
CLPDM 48 clamp pulse input at dummy pixel
Table 3: Pin description
…continued
Symbol Pin Description

Philips Semiconductors TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Objective specification Rev. 03 — 16 January 2001 6 of 23
9397 750 07918 © Philips Electronics N.V. 2001. All rights reserved.
8. Limiting values
[1] The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply voltage difference
∆VCC remains as indicated.
9. Thermal characteristics
10. Characteristics
Table 4: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCCA analog supply voltage [1] −0.3 +7.0 V
VCCD digital supply voltage [1] −0.3 +7.0 V
VCCO digital outputs supply voltage [1] −0.3 +7.0 V
∆VCC supply voltage difference:
between VCCA and VCCD −0.5 +0.5 V
between VCCA and VCCO −0.5 +1.2 V
between VCCD and VCCO −0.5 +1.2 V
Viinput voltage referenced to AGND −0.3 +7.0 V
Iodata output current −±10 mA
Tstg storage temperature −55 +150 °C
Tamb ambient temperature −20 +75 °C
Tjjunction temperature −150 °C
Table 5: Thermal characteristics
Symbol Parameter Conditions Value Unit
Rth(j-a) thermal resistance from junction to ambient in free air 76 K/W
Table 6: Characteristics
V
CCA
=V
CCD
= 3.0 V; V
CCO
= 2.7 V; f
pix
= 30 MHz; T
amb
=25 ° C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VCCA analog supply voltage 2.7 3.0 3.6 V
VCCD digital supply voltage 2.7 3.0 3.6 V
VCCO digital outputs supply voltage 2.5 2.7 3.6 V
ICCA analog supply current all clamps active −60 −mA
ICCD digital supply current −3−mA
ICCO digital outputs supply current CL= 10 pF on all data
outputs; input ramp
response time is 800 µs
−1−mA

Philips Semiconductors TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Objective specification Rev. 03 — 16 January 2001 7 of 23
9397 750 07918 © Philips Electronics N.V. 2001. All rights reserved.
Digital inputs
Pins: SHP, SHD and CLK (referenced to DGND)
VIL LOW-level input voltage 0 −0.6 V
VIH HIGH-level input voltage 2.2 −5.5 V
Iiinput current 0 ≤Vi≤5.5 V −3−+3 µA
Ziinput impedance fCLK = 30 MHz −50 −kΩ
Ciinput capacitance fCLK = 30 MHz −− 2pF
Pins: CLPDM, CLPOB, SEN, SCLK, SDATA, STBY, OE, BLK, VSYNC
VIL LOW-level input voltage 0 −0.6 V
VIH HIGH-level input voltage 2.2 −5.5 V
Iiinput current 0 ≤Vi≤5.5 V −2−+2 µA
Clamps
Global characteristics of the clamp loops
tW(clamp) clamp active pulse width in
number of pixels PGA code = 255 for maximum 4 LSB error 12 −−pixels
Input clamp (driven by CLPDM)
gm(CDS) CDS input clamp
transconductance −20 −mS
Correlated Double Sampling (CDS)
Vi(CDS)(p-p) maximum peak-to-peak CDS
input amplitude (video signal) VCC = 2.85 V 650 −−mV
VCC ≥3.0 V 800 −−mV
Vreset(max) maximum CDS input reset
pulse amplitude 500 −−mV
Ii(IN) input current into pin IN at floating gate level tbf −tbf µA
Ciinput capacitance −2−pF
tCDS(min) CDS control pulses minimum
active time Vi(CDS)(p-p) = 800 mV black to white transition in
1 pixel with 98.5%
Virecovery
8−−ns
th(IN;SHP) CDS input hold time (pin IN)
compared to control pulse
SHP
see Figure 3 and 44−−ns
th(IN;SHD) CDS input hold time (pin IN)
compared to control pulse
SHD
see Figure 3 and 44−−ns
Amplifier
DRPGA PGA dynamic range −24 −dB
∆GPGA PGA gain step 0.08 0.10 0.12 dB
Analog-to-Digital Converter (ADC)
DNL differential non linearity fpix = 30 MHz; ramp input −±0.5 ±0.9 LSB
Total chain characteristics (CDS + PGA + ADC)
fpix(max) maximum pixel frequency 30 −−MHz
Table 6: Characteristics
…continued
V
CCA
=V
CCD
= 3.0 V; V
CCO
= 2.7 V; f
pix
= 30 MHz; T
amb
=25 ° C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit

Philips Semiconductors TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Objective specification Rev. 03 — 16 January 2001 8 of 23
9397 750 07918 © Philips Electronics N.V. 2001. All rights reserved.
fpix(min) minimum pixel frequency tbf −−MHz
tCLKH CLK pulse width HIGH 12 −−ns
tCLKL CLK pulse width LOW 12 −−ns
td(SHD;CLK) time delay between
SHD and CLK see Figure 3 and 410 −−ns
tsu(BLK;SHD) set-up time of BLK compared
to SHD see Figure 3 and 45−−ns
Vi(IN) video input dynamic signal
for ADC full-scale output PGA code = 00 800 −−mV
PGA code = 255 50 −−mV
Ntot(rms) total noise from CDS input to
ADC output (RMS value) see Figure 8
PGA gain = 0 dB −1.5 −LSB
PGA gain = 9 dB −2.2 −LSB
Ein(rms) equivalent input noise
voltage (RMS value) PGA gain = 24 dB −70 −µV
PGA gain = 9 dB −140 −µV
OCCD(max) maximum offset between
CCD floating level and CCD
dark pixel level
−100 −+100 mV
Digital-to-analog converter (OFDOUT DAC)
VOFDOUT(p-p) additional 8-bit control DAC
(OFD) output voltage
(peak-to-peak value)
Ri=1MΩ−1.0 −V
VOFDOUT(0) DC output voltage for code 0 −AGND −V
VOFDOUT(255) DC output voltage for
code 255 −AGND + 1.0 −V
TCDAC DAC output range
temperature coefficient −250 −ppm/°C
ZOFDOUT DAC output impedance −2000 −Ω
IOFDOUT OFD output current drive static −− 100 µA
Digital outputs (fpix = 30 MHz; CL= 10 pF); see Figure 3 and 4
VOH HIGH-level output voltage IOH =−1mA V
CCO −0.5 −VCCO V
VOL LOW-level output voltage IOL =1mA 0 −0.5 V
IOZ output current in 3-state
mode 0.5 V < Vo<V
CCO −20 −+20 µA
th(o) output hold time 5 −−ns
td(o) output delay time CL= 10 pF; VCCO = 3.0 V −12 tbf ns
CL= 10 pF; VCCO = 2.7 V −14 tbf ns
CLoutput load capacitance −− 15 pF
Serial interface
fSCLK(max) maximum frequency of serial
interface 10 −−MHz
Table 6: Characteristics
…continued
V
CCA
=V
CCD
= 3.0 V; V
CCO
= 2.7 V; f
pix
= 30 MHz; T
amb
=25 ° C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit

Philips Semiconductors TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
9397 750 07918 © Philips Electronics N.V. 2001. All rights reserved. Objective specification Rev. 03 — 16 January 2001 9 of 23
Fig 3. Pixel frequency timing diagram; all polarities active HIGH.
N
0.6 V
2.2 V
tCDS(min)
tCLKH
th(IN;SHP)
0.6 V
0.6 V 0.6 V
0.6 V
th(IN;SHD)
2.2 V
tCDS(min)
td(SHD;CLK)
tsu(BLK;SHD)
2.2 V
2.2 V
2.2 V
FCE517
IN
SHP
SHD
CLK
DATA
BLK
th(o) td(o)
50%
2.2 V
NADC CLAMP
CODE
N −4
N +1N+2N+3N+4N+5
N −3N−2N−1
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hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh
hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh

Philips Semiconductors TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
9397 750 07918 © Philips Electronics N.V. 2001. All rights reserved. Objective specification Rev. 03 — 16 January 2001 10 of 23
Fig 4. Pixel frequency timing diagram; all polarities active LOW.
N
2.2 V
2.2 V
tCDS(min)
tCLKL
th(IN;SHP)
0.6 V
0.6 V
0.6 V 0.6 V
th(IN;SHD)
0.6 V
0.6 V
tCDS(min)
td(SHD;CLK)
tsu(BLK;SHD)
2.2 V
2.2 V 2.2 V
FCE518
IN
SHP
SHD
CLK
DATA
BLK
th(o) td(o)
N
50% ADC CLAMP
CODE
N −4
N +1N+2N+3N+4N+5
N −3N−2N−1
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