Portwell PGB-5120S User manual

PGB-5120S
Gaming Board
User's Manual
Version 1.1
Copyrigh © Por well, Inc., 2014. All righ s reserved.
All o her brand names are regis ered rademarks of heir respec ive owners.

Preface
Table of Contents
How to Use This Manual
Chapter 1 System Overview.......................................................................................................1-1
1.1 In roduc ion ....................................................................................................... 1-1
1.2 Check Lis ........................................................................................................... 1-2
1.3 Produc Specifica ion ........................................................................................ 1-2
1.3.1 Mechanical Drawing ................................................................................ 1-4
1.4 Sys em Archi ec ure .......................................................................................... 1-6
Chapter 2 Hardware Configuration ...........................................................................................2-1
2.1 Jumper Se ing ................................................................................................... 2-1
2.2 Connec or Alloca ion ........................................................................................ 2-2
Chapter 3 System Installation....................................................................................................3-1
3.1 In el LGA-1155 Processor ................................................................................. 3-1
3.2 Main Memory .................................................................................................... 3-5
3.3 Ins alling he Single Board Compu er ............................................................ 3-6
3.3.1 In el® BD82H61 PCH Chipse ............................................................... 3-6
3.3.2 In el® Core i processors in egra ed Graphics Engine ........................ 3-6
3.3.3 Real ek E herne Con roller .................................................................... 3-6
3.3.4 Audio Con roller ...................................................................................... 3-6
3.4 Clear CMOS Opera ionr ................................................................................... 3-7
Chapter 4 BIOS Setup Information............................................................................................4-1
4.1 En ering Se up -- Launch Sys em Se up ........................................................ 4-1
4.2 Main .................................................................................................................... 4-2
4.3 Advanced ........................................................................................................... 4-3
4.4 Chipse .............................................................................................................. 4-26
4.5 Boo ................................................................................................................... 4-32
4.6 Securi y ............................................................................................................. 4-35
4.7 Save & Exi ....................................................................................................... 4-36
Chapter 5 Troubleshooting........................................................................................................5-1
5.1 Hardware Quick Ins alla ion ........................................................................... 5-1
5.2 BIOS Se ing ....................................................................................................... 5-2
5.3 FAQ ..................................................................................................................... 5-3
Appendix A
Appendix B

Preface
How o Use This Manual
The manual describes how o configure your PGB-5120S sys em o mee various
opera ing requiremen s. I is divided in o five chap ers, wi h each chap er addressing
a basic concep and opera ion of Single Hos Board.
Chapter 1 : System Overview. Presen s wha you have in he box and give you an
overview of he produc specifica ions and basic sys em archi ec ure for his series
model of single hos board.
Chapter : Hardware Configuration. Shows he defini ions and loca ions of Jumpers
and Connec ors ha you can easily configure your sys em.
Chapter 3 : System Installation. Describes how o properly moun he CPU, main
memory and Compac Flash o ge a safe ins alla ion and provides a programming
guide of Wa ch Dog Timer func ion.
Chapter 4 : BIOS Setup Information. Specifies he meaning of each se up
parame ers, how o ge advanced BIOS performance and upda e new BIOS. In
addi ion, POST checkpoin lis will give users some guidelines of rouble-shoo ing.
Chapter 5 : Troubleshooting. Provides various useful ips o quickly ge PGB-5120S
running wi h success. As basic hardware ins alla ion has been addressed in Chap er
3, his chap er will basically focus on sys em in egra ion issues, in erms of backplane
se up, BIOS se ing, and OS diagnos ics.
The con en of his manual is subjec o change wi hou prior no ice. These changes
will be incorpora ed in new edi ions of he documen . Portwell may make
supplemen or change in he produc s described in his documen a any ime.
Upda es o his manual, echnical clarifica ion, and answers o frequen ly asked
ques ions will be shown on he following web si e : h p://www.por well.com. w/.

System Overview
PGB-5120S User’s Manual 1-1
Chapter 1
System Overview
1.1 Introduction
PGB-5120S is an indus rial All-in-one Game PCB complian wi h world famous GLI
& BMM regula ion. Combine wi h ei her he In el® SandyBridge/IvyBridge
processor, PGB-5120S provides powerful performance.
I suppor s ex raordinary fea ures such as, “Non-Vola ile RAM”, ”Triple Da a
Redundancy”,“ Secured RTC”, “Wa chdog Timer” , “Over Tempera ure Warning”
and “SAS”.
Slo Accoun ing Sys em (SAS) is a slo accoun ing pro ocol for gaming machines
such as video slo s. I was ini ialized by IGT and became he de-fac o casino
communica ions s andard. The la es version of he pro ocol is SAS 6.02 and i
suppor s me er repor ing, even logging, player racking, bonusing, icke ing and
cashless gamine.
Por well provide SAS API o help cus omer handle SAS Pro ocol low level behavior.
Our API fea ures in
Hardware 9-bi (wakeup) suppor ed
High performance logic engine o ensure da a ransmission can mee 20ms
response ime and 5ms In er-By e delay ime.
Synchroniza ion be ween Hos and Gaming Machine
Acknowledgemen for bo h general and long polls
CCITT based Cyclical Redundancy Check
Error Condi ion Handling, for example Gaming machine busy response, Loop
break indica ion, and e c.
All hese fea ures make PGB-5120S a value-orien ed solu ion for Slo s and
Mul i-players applica ion.
PGB-51 0S series features:
Complian wi h GLI/BMM
5+2 Years lifespan
Dual independen display by VGA/DVI
Ul ra fas 32bi , 66MHz PCI-Express opera ed SRAM
Full duplex RS-485 and ccTalk
SAS 6.02 complian

System Overview
PGB-5120S User’s Manual 1-2
1.2 Check List
PGB-5120S series package should con ain he following basic i ems:
One PGB-5120S All-in-one Game PCB
SATA power cable
SATA signal cable
If any of hese i ems is damaged or missing, please con ac your vendor and keep all
packing ma erials for fu ure replacemen and main enance.
1.3 Product Specification
General
Processor In el® SandyBridge/IvyBridge Processor
Chipse In el® H61 PCH
Memory Single channel up o 4GB DDR3 1333/1066 on one
SO
-
DIMM socke
S orage Devices 2x SATA 3.0 Gb/s
1x Compac Flash
Expansion
In erface
1x PCIe x16 slo
I/O Interface
Audio
 High Defini ion Audio 5.1 channels ou pu via Audio Jack
 Onboard S ereo 6W +6W Class A-B Amplifiers via 72-pin
golden finger
E herne Dual Gigabi E herne
Serial Por
2x RS232 por on rear I/O
2x RS232 por onboard pin header
1x SAS por onboard pin header
1x 4-wire RS485 por onboard pin header
1x ccTalk onboard pin header
USB
4x USB 2.0 on rear I/O
2x USB 2.0 onboard pin headers
2x USB 2.0 onboard ver ical connec or
Graphic
Graphic
Con roller
In el® HD Graphics in egra ed GPU
Graphic
Accelera ion
2D: Direc draw, UXA/SNA and XRandR
3D: Direc X 10.1, OpenGL 3.0
Video Playback H.264, MPEG-2, VC-1 hardware codecs
DXVA, VA API media accelera ion
Display In erface VGA: up o 2048x1536 (QXGA)
DVI: up o 1920x1200 (WUXGA)
Gaming Function

System Overview
PGB-5120S User’s Manual 1-3
Door Sensor
De ec ion
8 door inpu s
- 6 a golden finger
- 2 a onboard connec or
Opera es wi h and wi hou AC power
Logs of Da e/Time s amped of 44 even s
Ba ery vol age moni oring & warning
Programmable de-bounce ime
SAS 6.02
1 x SAS Por
Hardware 9-bi s da a suppor ed
20ms Response Time and 5ms Delay Time
Synchroniza ion and Acknowledgemen
Cyclical Redundancy Check
Error Condi ion Handling
NVRAM
 Ul ra fas 32bi , 66MHz PCI-Express opera ion
 1MBy es of ba ery backuped SRAM
 Dual independen physical banks and Dual ba ery
backup design o ensure in egri y
 4.5 Years Ba ery life wi hou AC power
 Ba ery vol age moni oring & warning
Digi al Inpu
 18 x Pho o-coupler Pro ec ed Inpu
 Individual in errup , riggered by rising/falling edges or
level changed
 Programmable de-bounce suppor ed
Digi al Ou pu 16 x open drain (150mA ~ 500mA); 50V
2 x 3A open drain
Mechanical& Environment
Dimension 170mm(L) x 215mm(W)
Power
Requiremen
 Typical: +12V, +5V, (+3.3V)
 Suppor ATX mode from 20pin inpu or AT mode from
20pin Golden Finger
Environmen
 Opera ion Tempera ure: 0~60 °C
 S orage Tempera ure: -20~85 °C
 Rela ive Humidi y: 10~85%, non-condensing

System Overview
PGB-5120S User’s Manual 1-4
1.3.1 Mechanical Drawing

System Overview
PGB-5120S User’s Manual 1-5

System Overview
PGB-5120S User’s Manual
1.4
System Architecture
All of de ails opera ing rela ions are shown in
PGB
System Architecture
All of de ails opera ing rela ions are shown in
PGB-5120S
Sys em Block Diagram
PGB
-51 0S System Block Diagram
1-6
Sys em Block Diagram
.

Hardware Configuration
PGB-5120S User’s Manual 2-1
Chapter 2
Hardware Configuration
This chap er indica es jumpers’, headers’ and connec ors’ loca ions. Users may find
useful informa ion rela ed o hardware se ings in his chap er.
2.1 Jumper Setting
For user o cus omize PGB-5120S fea ures. In he following sec ions, Short means
covering a jumper cap over jumper pins; Open or N/C (No Connec ed) means
removing a jumper cap from jumper pins. Users can refer o Figure 1 and Figure 2 for
he Jumper alloca ions.
Figure1. PGB-51 0S Top View

Hardware Configuration
PGB-5120S User’s Manual 2-2
2.2 Connector Allocation
I/O peripheral devices are connec ed o he in erface connec ors
Connector Function List
Connector Function
JP1 COM6 J6_Pin1 CCTALK_V+ Vol age Jumper Se ing
JP2 COM6 J6_Pin4 CCTALK Pull High Vol age Jumper Se ing
JP3 COM3 RI# Vol age Se ing
JP6 COM4 RI# Vol age Se ing
JP8 Programming por for PWM Con roller
JP9 Debug Por for PWM Con roller
JP10 Au o Power On Source Se ing
JP11 Programming Por for MCU
JP12 Configure / Recovery Se ing
JP13 Pro ec ed RTC Se ing
JP15 VCCSA Vol age Selec ion
JP17 CMOS Clear Header
JP18 FPGA VCCO Power Se ing
JP19 In ernal Case Open 6 Se ing
JP21 SATA1 / SATA DOM1 Se ing
JP22 SATA0 / SATA DOM0 Se ing
JP24 3.3V_FPGA Se ing
JP25 In ernal Case Open 7 Se ing
JP27 BIOS Pro ec
JP28 Power func ion selec
(Because au o selec in normal mode,
J30 GPI PULL HI 3.3V & 5V & +12V
Pin Assignments of Connectors
JP1: LVDS Backlight VDD Setting
JP1 Function
Shor 1-2 +12V *
Shor 2-3 VCC
No e : The “ * ” mark for defaul se ing
JP : COM6 J6_Pin4 CCTALK Pull High Voltage Jumper Setting
JP Function
Shor 1-2 +12V *
Shor 3-4 VCC
No e : The “ * ” mark for defaul se ing

Hardware Configuration
PGB-5120S User’s Manual 2-3
JP3: COM3 RI# Voltage Setting
JP3 Function
Shor 1-2 VCC
Shor 3-4 +12V
Shor 5-6 RI#_3 *
No e : The “ * ” mark for defaul se ing
JP6: COM4 RI# Voltage Setting
JP6 Function
Shor 1-2 VCC
Shor 3-4 +12V
Shor 5-6 RI#_4 *
No e : The “ * ” mark for defaul se ing
JP8: Programming port for PWM Controller
JP8 Function
Shor 1-2 VCC
JP9: Debug port for PWM Controlleoller
JP9 Function
Shor 1-2-3 Debug Por for PWM Con roller
JP10: Auto Power On Source Setting
JP10 Function
Short 1
-
2
Normal Opera ion *
Short 3
-
4
Normal Opera ion *
Open 1
-
2
While Programming PIC
Open 3
-
4
While Programming PIC
No e : The “ * ” mark for defaul se ing
JP11: Programming Port for MCU
JP11 Function
Shor 1-2-3-4-5-6 Programming Por for MCU
JP1 : Configure / Recovery Setting
JP1 Function
Shor 1-2 Normal *
Shor 2-3 Configure
Open Recovery
No e : The “ * ” mark for defaul se ing

Hardware Configuration
PGB-5120S User’s Manual 2-4
JP13: Protected RTC Setting
JP13 Function
Shor 1-2 Normal *
Shor 2-3 CLR RTC
No e : The “ * ” mark for defaul se ing
JP15: VCCSA Voltage Selection
JP15 Function
Open 1-2 0.925V *
Shor 1-2 0.85V (for fu ure processor compa ibili y)
No e : The “ * ” mark for defaul se ing
JP17: CMOS Clear Header
JP17 Function
Shor 1-2 Normal Opera ion *
Shor 2-3 Clear CMOS Con en s
No e : The “ * ” mark for defaul se ing
JP18: FPGA VCCO Power Setting
JP18 Function
Shor 1-2 VCC3 *
Shor 2-3 3.3V_FPGA Floa ing o ground
No e : The “ * ” mark for defaul se ing
JP19: Internal Case Open 6 Setting
JP19 Function
Shor 1-2 In rusion6
Open 1-2 Normally Mode *
No e : The “ * ” mark for defaul se ing
JP 1: SATA1 / SATA DOM1 Setting
JP 1 Function
Shor 1-2 SATA DOM
Shor 2-3 SATA *
No e : The “ * ” mark for defaul se ing
JP : SATA0 / SATA DOM0 Setting
JP Function
Shor 1-2 SATA DOM
Shor 2-3 SATA *
No e : The “ * ” mark for defaul se ing

Hardware Configuration
PGB-5120S User’s Manual 2-5
JP 4: 3.3V_FPGA Setting
JP 4 Function
Shor 1-2 FPGA Ex ernal Power Link o GND
Open 1-2 Normal *
No e : The “ * ” mark for defaul se ing
JP 5: Internal Case Open 7 Setting
JP 5 Function
Shor 1-2 In rusion7
Open 1-2 Normally Mode *
JP 7: BIOS Protec
JP 7 Function
Shor 1-2 BIOS Pro ec
Shor 2-3 BIOS Wri e
JP 8: Power function select
(Because auto select in normal mode,don’t use JP 8 in normal mode)
JP 8 Function
Shor 1-2 & 3-4 Power in by Gold finger
Disconnec 1-2 & 3-4 ATX power
J30: GPI PULL HI 3.3V & 5V & +1 V
J30 Function
Shor 2-4 GPI PULL HI 3.3V
Shor 3-4 GPI PULL HI 5V
Shor 4-6 GPI PULL HI +12V

Hardware Configuration
PGB-5120S User’s Manual 2-6
Connector Table
Connector
Reference
Function Descriptions
J1 VGA + DVI-D Connec or
J2 COM1, COM2 Connec or
J3 Audio Jack Connec or
J4 RJ45 + USB x 2 Connec or
J5 RJ45 + USB x 2 Connec or
J6 COM6 CCTalk Connec or
J7 USB x 2 Header
J8 USB Connec or
J9 USB Connec or
J10 COM4 RS-232 Connec or
J11 COM3 RS-232 Connec or
J12 LPC Debug Por Header
J13 ATX 4P Connec or
J14 ATX 20P Connec or
J15 CFEX Connec or
J16 PCI-E x 16 Connec or
J17 Sys em Rese Header
J18 CF / CF-SATA Connec or
J19 SAS COM PORT Pin Header
J20 SATA / SATA DOM Connec or
J21 SATA / SATA DOM Connec or
J22 PIC Program Header
J23 SYSFANOUT Header
J24 CPUFANOUT Header
J25 DIMM Connec or
J26 Power in Golden Finger 10P x 2
J27 Golden Finger 36P x 2
D1 Power and HDD LED
JP4 COM5 4-wire RS-485 Header
JP14 JTAG Programming Header
JP16 JTAG Programming Header
JP20 FPGA 3PX2 GPIO Header
JP23 SATA Power Header

Hardware Configuration
PGB-5120S User’s Manual 2-7
J1:VGA + DVI-D Connector
Pin Assignment Pin Assignment
A1 DVI_D_RD2N A2 DVI_D_RD2P
A3 Video GND A4 NC
A5 NC A6 DVI_CON_CLK0
A7 DVI_CON_DAT0 A8 NC
A9 DVI_D_GD1N A10 DVI_D_GD1P
A11 Video GND A12 NC
A13 NC A14 DVI_CON_5V
A15 Video GND A16 DVID_SHF_HPD
A17 DVI_D_BD0N A18 DVI_D_BD0P
A19 Video GND A20 NC
A21 NC A22 Video GND
A23 DVI_D_CLKP A24 DVI_D_CLKN
B1 VGA_RED B2 VGA_GREEN
B3 VGA_BLUE B4 NC
B5 Video GND B6 VGADCT
B7 VGA_VAGND B8 VGA_VAGND
B9 +5V B10 Video GND
B11 NC B12 VGA_DDD
B13 VGA_HSYNC B14 VGA_VSYNC
B15 VGA_DDC
J :COM1,COM Connector
Pin Assignment Pin Assignment
A1 DCD#1/DT- A2 RXD#1/DT+
A3 TXD#1/422R+ A4 DTR#1/422R-
A5 GND A6 DSR#1
A7 RTS#1 A8 CTS#1
A9 RI#1
B1 DCD#2 B2 RXD#2
B3 TXD#2 B4 DTR#2
B5 GND B6 DSR#2
B7 RTS#2 B8 CTS#2
B9 RI#2
J3:Audio Jack Connector
Pin Assignment Pin Assignment
Blue Line In Green Line Ou
Pink MIC

Hardware Configuration
PGB-5120S User’s Manual 2-8
J4:RJ45+USBx Connector
Pin Assignment Pin Assignment
C1 +1.05V C2 LAN1_MDIP0
C3 LAN1_MDIN0 C4 LAN1_MDIP1
C5 LAN1_MDIN1 C6 LAN1_MDIP2
C7 LAN1_MDIN2 C8 LAN1_MDIP3
C9 LAN1_MDIN3 C10 L1_MDC1
C11 LED1_LINK# C12 LAN1_ACT-
C13 LAN1_LINK1000 C14 LAN1_LINK100
B1 USBV0 B2 USBD0N
B3 USBD0P B4 USBG0
A1 USBV1 A2 USBD1N
A3 USBD1P A4 USBG1
J5:RJ45+USBx Connector
Pin Assignment Pin Assignment
C1 +1.05V C2 LAN2_MDIP0
C3 LAN2_MDIN0 C4 LAN2_MDIP1
C5 LAN2_MDIN1 C6 LAN2_MDIP2
C7 LAN2_MDIN2 C8 LAN2_MDIP3
C9 LAN2_MDIN3 C10 L2_MDC1
C11 LED2_LINK# C12 LAN2_ACT-
C13 LAN2_LINK1000 C14 LAN2_LINK100
B1 USBV2 B2 USBD2N
B3 USBD2P B4 USBG2
A1 USBV3 A2 USBD3N
A3 USBD3P A4 USBG3
J6: COM6 CC Talk Connector
Pin Assignment Pin Assignment
1 CCTALK_V+ 2 N/A
3 GND 4 CCTALK3
J7: USB x Header
Pin Assignment Pin Assignment
1 USBV6 2 USBV7
3 USBD6N 4 USBD7N
5 USBD6P 6 USBD7P
7 USBG6 8 USBG7

Hardware Configuration
PGB-5120S User’s Manual 2-9
J8: USB Connector
Pin Assignment
1 USBV5
2 USBD5N
3 USBD5P
4 USBG5
CG1 GND
CG2 GND
J9: USB Connector
Pin Assignment
1 USBV4
2 USBD4N
3 USBD4P
4 USBG4
CG1 GND
CG2 GND
J10: COM4 RS- 3 Connector
Pin Assignment Pin Assignment
1 DCD#_4 2 RXD#_4
3 TXD#_4 4 DTR#_4
5 GND 6 DSR#_4
7 RTS#_4 8 CTS#_4
9 RI4# 10 NC
J11: COM3 RS- 3 Connector
Pin Assignment Pin Assignment
1 DCD#_3 2 RXD#_3
3 TXD#_3 4 DTR#_3
5 GND 6 DSR#_3
7 RTS#_3 8 CTS#_3
9 RI3# 10 NC
J1 : LPC Debug Port Header
Pin Assignment Pin Assignment
1 LAD0 2 VCC3
3 LAD1 4 PCI_RST#
5 LAD2 6 LFRAME#
7 LAD3 8 PCLK_TPM
10 GND

Hardware Configuration
PGB-5120S User’s Manual 2-10
J13: ATX 4P Connector
Pin Assignment
1 GND
2 GND
3 +12V
4 +12V
J14: ATX 0P Connector
Pin Assignment Pin Assignment
1 VCC3_ATX 11 VCC3_ATX
2 VCC3_ATX 12 NC
3 GND 13 GND
4 VCC 14 PS_ON#
5 GND 15 GND
6 VCC 16 GND
7 GND 17 GND
8 ATX_PWROK 18 NC
9 5VSB 19 VCC
10 +12V 20 VCC
J15: CFEX Connector
Pin Assignment Pin Assignment
1 GND 26 VCC3
2 CLK_SPI_CFEX 27 GND
3 R_SPI_MISO_CFEX 28 GND
4 GND 29 SATA_TX3+
5 GND 30 SATA_TX3-
6 GND 31 SPI_CS0#_CFEX
7 SPI_MOSI_CFEX 32 GND
8 GND 33 SATA_RX3-
9 GND 34 SATA_RX3+
10 GND 35 SPI_WP#_CFEX
11 LAD0 36 SMB_CLK_MAIN
12 LAD1 37 V_3P3_EPW
13 VCC 38 VCC
14 LAD2 39 LFRAME#
15 LAD3 40 PLT_RST#
16 CFEX_LPC_CLK 41 SMB_DATA_MAIN
17 LDRQ#1 42 GND
18 NC 43 GND
19 NC 44 GND
20 GND 45 NC
21 SERIRQ 46 GND

Hardware Configuration
PGB-5120S User’s Manual 2-11
22 NC 47 GND
23 NC 48 GND
24 GND 49 NC
25 GND 50 GND
J16: PCI-E x 16 Connector
Reference s andard PCI-E defini ion SPEC
J17: System Reset Header
Pin Assignment
Shor 1-2 Sys em Rese
J18: CF / CF-SATA Connector
Pin Pure IDE Mode Definition CF-SATA
1 DGND DGND
8 DGND AGND
10 DGND (From Hos o SATA) RX+
11 DGND (From Hos o SATA) RX-
12 DGND AGND
13 VCC5 VCC5
14 DGND AGND
15 DGND (From Hos o SATA) TX-
16 DGND (From Hos o SATA) TX+
17 DGND AGND
38 VCC5 VCC5
J19: SAS COM PORT Pin Connector
Pin Assignment Pin Assignment
1 Reserved TX 2 COM TX
3 GND 4 GND
5 Reserved RX 6 COM RX
J 0: SATA / SATA DOM Connector
Pin Assignment Pin Assignment
1 GND 2 PCH_SATA_TX0+
3 PCH_SATA_TX0- 4 GND
5 PCH_SATA_RX0- 6 PCH_SATA_RX0+
7 GND / 5V_DOM CG1 GND
CG2 GND