Qorvo PAC2514 Series User manual

Power Application Controller Battery Management
PRODUCT USER GUIDE
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PAC2514x User Guide Preview
PAC Battery Management System
Multi-Mode Power ManagerTM
Configurable Analog Front EndTM
Application Specific Power DriversTM
Arm®Cortex®-M4F Controller Core

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TABLE OF CONTENTS
1OVERVIEW ........................................................................................................................ 8
2STYLE AND FORMATTING CONVENTIONS..................................................................... 9
2.1 Number Representation............................................................................................... 9
2.2 Formatting Styles......................................................................................................... 9
3ARCHITECTURAL BLOCK DIAGRAM ..............................................................................10
4ANALOG REGISTER ACCESS .........................................................................................11
4.1 Overview.....................................................................................................................11
4.2 Functional Description ................................................................................................11
4.3 USART Configuration .................................................................................................12
4.4 Protocol ......................................................................................................................12
4.5 Write Register Example ..............................................................................................12
4.6 Read Register Example ..............................................................................................14
5PAC2514X IO ....................................................................................................................15
5.1 Overview.....................................................................................................................15
5.2 ADC Channels ............................................................................................................16
5.3 Digital Peripheral Pins.................................................................................................17
6CONFIGURABLE POWER MANAGER .............................................................................19
6.1 Features .....................................................................................................................19
6.2 System Block Diagram................................................................................................19
6.3 Functional Description ................................................................................................19
6.4 Register Summary ......................................................................................................23
6.5 Register Details ..........................................................................................................23
6.5.1 SOC.FAULT.........................................................................................................23
6.5.2 SOC.STATUS......................................................................................................25
6.5.3 SOC.MISC...........................................................................................................26
6.5.4 SOC.PWRCTL.....................................................................................................27
6.5.5 SOC.FAULTENABLE...........................................................................................28
6.5.6 SOC.WATCHDOG...............................................................................................29
6.5.7 SOC.SYSCONF...................................................................................................30
7CONFIGURABLE ANALOG FRONT-END .........................................................................31
7.1 Overview.....................................................................................................................31
7.2 Features .....................................................................................................................31
7.3 System Block Diagram................................................................................................32
7.4 Functional Description ................................................................................................33

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7.4.1 Register Protection ..............................................................................................33
7.4.2 Current Sensing...................................................................................................33
7.4.3 IADC 16-bit Sigma-Delta ADC .............................................................................33
7.4.4 Over-Current Protection.......................................................................................34
7.4.5 Short- Circuit Protection.......................................................................................34
7.4.6 Over-Current Charge Protection ..........................................................................35
7.4.7 Over-Current Discharge Protection ......................................................................35
7.4.8 Battery Over-Voltage Protection...........................................................................36
7.4.9 Voltage Sensing...................................................................................................36
7.4.10 Measuring Independent Cell Voltages .................................................................36
7.4.11 AFE MUX.............................................................................................................37
7.4.12 Enabling the CAFE ..............................................................................................38
7.4.13 Push-Button (PB) Input ........................................................................................38
7.5 Analog I/O 0 (AIO0) ....................................................................................................39
7.5.1 AIO0 Block Diagram ............................................................................................39
8Miscellaneous AFE Registers and Controls .......................................................................40
8.1 General-Purpose Register ..........................................................................................40
8.2 AFE Registers.............................................................................................................41
8.3 Driver Manager ...........................................................................................................65
8.3.1 Block Diagram .....................................................................................................65
8.3.2 Detail Block Diagram ...........................................................................................66
8.4 Cell Balancing.............................................................................................................67
8.4.1 Block Diagram .....................................................................................................67
8.5 AFE MUX and EMUX..................................................................................................69
8.5.1 AFE MUX.............................................................................................................69
8.5.2 EMUX ..................................................................................................................70
8.5.3 High Voltage Signal EMUX Correction.................................................................72
9ARM®CORTEX M4F REFERENCE ..................................................................................73
9.1 PAC25xxx Architecture ...............................................................................................74
9.2 SYSTEM AND CLOCK CONTROL (SCC) ..................................................................75
9.2.1 Overview..............................................................................................................75
9.2.2 Features ..............................................................................................................75
9.3 MCU MEMORY MAP..................................................................................................77
9.4 INFO-2 Flash Register Map ........................................................................................78
10 Revision History.................................................................................................................80
11 Legal Information ...............................................................................................................81

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LIST OF FIGURES
Figure 3-1 PAC2514X Architectural Block Diagram ..................................................................10
Figure 4-1 PAC2514X Register Access ....................................................................................11
Figure 4-2 Analog Peripheral Register Write Timing .................................................................12
Figure 4-3 Analog Peripheral Register Read Timing .................................................................14
Figure 5-1 GPIO and DPM Block Diagram ................................................................................15
Figure 6-1 Power Manager System Block Diagram...................................................................19
Figure 7-1 Configurable Analog Front End System Block Diagram ...........................................32
Figure 7-2 Push Button Block Diagram .....................................................................................38
Figure 7-3 AIO0 Block Diagram ................................................................................................39
Figure 9-1 EMUX Timing Diagram ............................................................................................72
Figure 9-1 Top Level Block Diagram.........................................................................................74
Figure 9-2 Clock Control Block Diagram ...................................................................................76
Figure 9-3 High Level Memory ..................................................................................................77

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LIST OF TABLES
Table 5-1 PAC2514X ADC Input Pins .......................................................................................16
Table 5-2 PAC2514X Internal Connections...............................................................................16
Table 5-3 PAC2514X Digital Peripheral Pins ............................................................................17
Table 6-1 CPM Register Summary............................................................................................23
Table 8-1 Analog Front End Register Map ................................................................................41
Table 8-2 ADC MUX channels ..................................................................................................69
Table 8-3 AFE MUX channels...................................................................................................70
Table 9-1 PAC2514X INFO-2 Flash Register Map ....................................................................78

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LIST OF REGISTERS
Register 6-1 SOC.FAULT (Fault Condition, 00h).......................................................................23
Register 6-2 SOC.STATUS (System Status, 01h).....................................................................25
Register 6-3 SOC.MISC (SOC Miscellaneous Configuration, 02h)............................................26
Register 6-4 SOC.PWRCTL (Power Control, 03h) ....................................................................27
Register 6-5 SOC.FAULTENABLE (Fault enable, 04h) .............................................................28
Register 6-6 SOC.WATCHDOG (SOC Watchdog Configuration, 05h) ......................................29
Register 6-7 SOC.SYSCONF (System Configuration, 2Bh) ......................................................30
Register 8-1. SOC.AFECTL1 (AFE Control 1, SOC 0x00) ........................................................43
Register 8-2. SOC.DRVCTL (Driver Control, SOC 0x02) ..........................................................44
Register 8-3. SOC.AFEMUXCTL (AFE Mux Control, SOC 0x03) ..............................................44
Register 8-4. SOC.AFEMUXSEL (AFE Mux Select, SOC 0x04) ...............................................44
Register 8-5. SOC.HIBCTL (Hibernate Control, SOC 0x05)......................................................46
Register 8-6. SOC.HIBENTER (Hibernate Enter, SOC 0x06)....................................................47
Register 8-7. SOC.RSTSTAT (Reset Status, SOC 0x07)..........................................................47
Register 8-8. SOC.PB (Push Button, SOC 0x08) ......................................................................48
Register 8-9. SOC.AIO0CFG (Analog I/O 0 Configuration, SOC 0x09) .....................................49
Register 8-10. SOC.PROT_KEY (Protection Key, SOC 0x10) ..................................................49
Register 8-11. SOC.SIGMGRCTL1 (Signal Manager Control 1, SOC 0x11) .............................50
Register 8-12. SOC.SIGMGRCTL2 (Signal Manager Control 2, SOC 0x12) .............................50
Register 8-13. SOC.PROTEN (Reset Status, SOC 0x13) .........................................................50
Register 8-14. SOC.FUSE (Fuse Driver Control, SOC 0x14) ....................................................51
Register 8-15. SOC.PWRFAULTEN (Power Fault Interrupt Enable, SOC 0x15) .......................52
Register 8-16. SOC.PWRFAULT (Power Fault, SOC 0x16) ......................................................53
Register 8-17. SOC.TEMPFAULTEN (Temperature Fault Interrupt Enable, SOC 0x17) ...........53
Register 8-18. SOC.TEMPFAULT (Temperature Fault Flag, SOC 0x18) ..................................53
Register 8-19. SOC.SIGFAULTEN (Signal Manager Fault Interrupt Enable, SOC 0x19) ..........53
Register 8-20. SOC.SIGFAULT (Signal Manager Fault Flag, SOC 0x1A) .................................55
Register 8-21. SOC.BATRTS (Battery Protection Comparator Real-Time Status, SOC 0x1B) .56
Register 8-22. SOC.BATOVCFG (Battery Over Voltage Comparator Config., SOC 0x20) .......56
Register 8-23. SOC.BATOVDAC (Battery Over Voltage DAC, SOC 0x21)................................56
Register 8-24. SOC.VADCCTL (Voltage ADC Control, SOC 0x22)...........................................57
Register 8-25. SOC.VADCRESHI (Voltage ADC Result High, SOC 0x23) ................................57
Register 8-26. SOC.VADCRESLO (Voltage ADC Result Low, SOC 0x24)................................58
Register 8-27. SOC.IADCCTL (Current ADC Control, SOC 0x25).............................................58
Register 8-28. SOC.IADCRESHI (Current ADC Result High, SOC 0x26)..................................58
Register 8-29. SOC.IADCRESLO (Current ADC Result Low, SOC 0x27) .................................58
Register 8-30. SOC.SCPDAC (SCP DAC, SOC 0x28)..............................................................58
Register 8-31. SOC.SCPCFG (SCP Comparator Configuration, SOC 0x29)............................59
Register 8-32. SOC.OCDDAC (OCD DAC, SOC 0x2A) ............................................................59
Register 8-33. SOC.OCDCFG (OCD Comparator Configuration, SOC 0x2D) ..........................60
Register 8-34. SOC.OCCDAC (OCC DAC, SOC 0x2C) ............................................................60
Register 8-35. SOC.OCCCFG (OCC Comparator Configuration, SOC 0x2B) ..........................60

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Register 8-36. SOC.CELLEN1 (Cell Enable 1, SOC 0x30) .......................................................61
Register 8-37. SOC.CELLEN2 (Cell Enable 2, SOC 0x31) .......................................................61
Register 8-38. SOC.CELLEN3 (Cell Enable 3, SOC 0x32) .......................................................61
Register 8-39. SOC.CFGCB1 (Configure Cell Balance 1, SOC 0x33).......................................62
Register 8-40. SOC.CFGCB2 (Configure Cell Balance 2, SOC 0x34).......................................62
Register 8-41. SOC.CFGCB3 (Configure Cell Balance 3, SOC 0x35).......................................62
Register 8-42. SOC.GP (General-Purpose Register, SOC 0x40) ..............................................62
Register 8-43. SOC.CLKOUTCFG (Clock Out Configuration, SOC 0x41) .................................63
Register 8-44. SOC.WWDTCTL (Windowed Watchdog Timer Control, SOC 0x42) ..................63
Register 8-45. SOC.WWDTCTR (Windowed Watchdog Timer Counter, SOC 0x43).................64
Register 8-46. SOC.WWDTCDV (Windowed Watchdog Timer Count Down Value, SOC 0x44)64
Register 8-47. SOC.WWDTWIN (Windowed Watchdog Timer Window, SOC 0x45) .................64
Register 8-48. SOC.WWDTRST (Windowed Watchdog Timer Reset, SOC 0x46) ....................64
Register 8-49. EMUX Packet Structure ...................................................................................71

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1 OVERVIEW
This document is the PAC2514x Device User Guide. It details the operation of the analog
peripherals in the PAC25140, PAC25140N, PAC25141N.
For detailed information on the MCU and Digital Peripherals in the PAC2514x, see the
PAC55XX Family User Guide.

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2 STYLE AND FORMATTING CONVENTIONS
This chapter describes the formatting and styles used throughout this document.
2.1 Number Representation
Numbers other than decimal will have a postfix indicator. All numbers use little endian
formatting, with the most significant bit/digit to the left. Digits for binary and hexadecimal
representation are grouped with a single space every four digits to improve readability. Binary
numbers use “b” as a postfix and hexadecimal numbers use “h” as a postfix.
For example, 1011b binary = Bh hexadecimal = 11 decimal.
2.2 Formatting Styles
TYPE
EXAMPLE
DESCRIPTION
Register Name
RTCCTL
Register names use a capital letter and boldface type.
Register Bit(s)
RTCCTL.RTCCLKDIV
Register bits are always represented with the register name
separated with a period.
Function selected by
register bit(s)
[RTCCTL.RTCCLKDIV]
Within text blocks, functions selected with a register bit setting are
set in brackets. For example [RTCCTL.RTCCLKDIV] means divider
settings /2 to /65536.
Pin Function
PA5
Pin functions use capital letters
Internal signals
PWMA3
Internal signals use italicized font.
Formulas
CLK = FCLK / DIV
Formulas use monospaced text.
Links
Link
Hyperlinks are underlined and blue.
CPU Mnemonic
MRS
CPU Mnemonic uses monospaced text.
Operands
{Rd, }, Rn, Rm
Operands use monospaced italic text.
Code examples
b loopA
Code examples use monospaced text.

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3 ARCHITECTURAL BLOCK DIAGRAM
For Below is an architecture block diagram of the PAC2514X device.
Figure 3-1 PAC2514X Architectural Block Diagram
IO
128kB FLASH
32kB SRAM
CLOCK
CONTROL
RTC/Calendar
GPIO
USART (3)
I2C
CAN
SYSTEM
CONTROL
APB/AHB
PAC25140
Power Application Controller
PX.Y
DEBUG/
ETM
ARM
CORTEX-M4F
CORE
TIMERS (4)
DEAD TIME
(16)
PWM/CC (32)
PWM ENGINE
PX.Y
PX.Y
PX.Y
PX.Y
PX.Y
BRIDGE
WWDT
DTSE
DATA ACQUISITION
AND SEQUENCER
12-BIT
ADC
MUX
1kB INFO
FLASH
GP TIMER (2)
CRC
SOC BUS
POWER
MANAGER
Configurable Analog
Front End (CAFÉ)
PGA ISNSP
ISNSN
HSGD
APPLICATION SPECIFIC
POWER DRIVERS
HSGD
MUX
16-bit
SD ADC
VB1
VB20
PACK+, BAT, VIN
...
Cell
Balance
...
...
LSGD
LDOs VCORE
VCC33
VSYS
VCCIO
HIGH-
VOLTAGE
BUCK SUPPLY
VIN
DRM
VP
BST
SRC
CSM
HV
Charge Pump VCP
BAT
PACK+
AFE MUX
16-bit
SD ADC
VCP, VP, VSYS
VCC33, VCCIO, VCORE
VREF, VPTAT
FUSE, CHG, DSG
BAT
AIO0
Push
Button
AIO0
CHG
DSG
FUSE
VB20
VB19
...
VB0
VB1
PB
PX.Y

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4 ANALOG REGISTER ACCESS
4.1 Overview
All analog registers in the PAC2514X are accessible through a SOC bus in the device. Unlike
registers in the MCU (SRAM and digital peripheral registers), these analog registers are not
memory mapped.
The block diagram below shows the different system busses that the MCU uses to access the
different system registers.
Figure 4-1 PAC2514X Register Access
SWD
Cortex-M4F
MCU
PACXXXXX
Debug
Port
AHB/APB
Bridge Analog
Peripherals
GPIOAUSARTA
Memory
Controller
JTAG
AHB APB
Other
Digital
Peripherals
DPM
GPIO[A..G]
The PAC2514X contains two register buses: the AHB bus and the APB bus.
The AHB bus allows the MCU and Debug Port access to FLASH and SRAM via the Memory
Controller. To access other digital peripheral connected to the APB bus, there is a bridge from
the AHB to the APB bus so that the MCU or Debug Port can perform memory-mapped register
access to all digital peripherals. Some digital peripherals such as timers are flexibly connected
to IO using the DPM bus.
To access the Analog peripherals, the USARTA SPI peripheral is used to generate read and
write transactions to the Analog registers using the DPM and GPIOA.
4.2 Functional Description
External programming interfaces such as JTAG and SWD or the Arm®Cortex®-M4F MCU may
perform memory-mapped accesses to USART A through the AHB and APB busses on the
device.
USART A is a serial communication peripheral that supports a SPI-like protocol that can be
used to communicate to the Analog Peripherals for read and write transactions. The Digital

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Peripheral MUX (DPM) may be configured to connect the USART A SPI signals to GPIO A,
where they are connected to the Analog peripherals.
4.3 USART Configuration
USART A acts as a SPI bus master to communicate with the Analog Peripherals. The USART A
signals that are used for this communication are:
▪USASCLK –USART A SPI Clock
▪USAMOSI –USART A Master-Out/Slave-In
▪USAMISO –USART A Master-In/Slave-Out
▪USASS –USART A Slave Select
In order to communicate with the Analog Peripherals, the USART A should have the following
configuration:
▪8-bit mode
▪SCLK active high
▪CPH is sample/setup
▪SS active low
When communicating with the Analog Peripherals, the maximum SCLK frequency is 25MHz.
4.4 Protocol
The protocol for communicating with the Analog Peripherals is a simple two-byte protocol.
The first byte is always the address, which includes a 7-bit address [7:1] and a write bit [0]. For
write operations, the write bit [0] is set to 1b. For read operations, the write bit [0] is set to 0b.
For write operations, the 2nd byte will be the 8-bit data to write to the given address.
For read operations, the 2nd byte is ignored and MISO will contain the 8-bit data read from the
given address.
4.5 Write Register Example
To write the HPDACH register (address 11h) with the value 28h, issue the following
transactions to USART A:
▪Write SSPADAT with the value 23h (11h << 1 | 1b for write transaction)
▪Write SSPADAT with the value 28h
The timing diagram from a write operation is shown below.
Figure 4-2 Analog Peripheral Register Write Timing

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4.6 Read Register Example
To read the contents of the HPDACH register, issue the following transactions to USART A:
▪Write SSPADAT with the value 22h (11h << 1 | 0b for read transaction)
▪Write SSPADAT with a dummy character
▪Read last data from MISO from SSPADAT, this is the register value
The timing diagram from a read operation is shown below.
Figure 4-3 Analog Peripheral Register Read Timing
For more information on how to configure the DPM to support the USART A peripheral for
communicating with the Analog Registers, see the PAC55XX Family User Guide.

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5 PAC2514X IO
5.1 Overview
The Digital Peripheral MUX (DPM) on the PAC55XX family allows flexible assignment of
peripheral functions to IO pins.
Each member of the family has a different set of IO pins that are available. It is important during
application design that the designer consider the available IO pins to make sure the necessary
peripherals will be available.
Below is a diagram of the GPIO and MUX structure.
Figure 5-1 GPIO and DPM Block Diagram
Each IO can be configured to select 1 of up to 8 digital peripheral signals. Some IOs also may
be used as an ADC input. For information on how to configure the IO for each of these
situations, see the PAC55XX Family User Guide.

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5.2 ADC Channels
The ADC channels that are available on the PAC2514X are shown in the table below.
Table 5-1 PAC2514X ADC Input Pins
ADC Channel
MCU I/O PIN
Description
AD0
PG7
Internally Connected to AFE MUX
AD1
PD3,PG5
Package pin
AD2
PD2,PG6
Package pin
AD3
PD1
Package pin
AD4
PD0,PF4
Package pin
AD5
PF5
Package pin
AD6
PF6
Package pin
AD7
PF7
Package pin
Table 5-2 PAC2514X Internal Connections
AFE Function
MCU I/O PIN
Description
ICBCTL0
PB0
DSG Control Line
ICBCTL1
PB1
CHG Control Line
IADCBUSY
PB3
Current ADC Busy
VADCBUSY
PB4
Voltage ADC Busy
PBPT
PG6
Push Button
ADCIN
PG7
EMUX output Analog Signal input to MCU ADC
nIRQ1
PA7
Interrupt for Temperature Faults
nIRQ2
PA0
Interrupt for Current Faults and BATOV
MUXDATA
PA1
EMUX Setting
MUXCLK
PA2
EMUX Clock to load setting
SPICLK
PA3
SPI Clock
SPIMOSI
PA4
SPI MOSI
SPIMISO
PA5
SPI MISO
SPICS
PA6
SPI Chip Select

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5.3 Digital Peripheral Pins
The digital peripheral functions that are available in the PAC2514X are shown below.
Table 5-3 PAC2514X Digital Peripheral Pins
PORT
Pin
GPIOxMUXS.Py
000b
001b
010b
011b
100b
101b
110b
111b
GPIOA
P0
GPIOA0
P1
GPIOA1
EMUXD
P2
GPIOA2
EMUXC
P3
GPIOA3
USASCLK
USBSCLK
P4
GPIOA4
USAMOSI
USBMOSI
P5
GPIOA5
USAMISO
USBMISO
P6
GPIOA6
USASS
USBSS
P7
GPIOA7
GPIOB
P0
GPIOB0
TAPWM0
TBPWM0
P1
GPIOB1
TAPWM1
TBPWM1
P2
GPIOB2
TAPWM2
TBPWM2
P4
GPIOB4
TAPWM4
TBPWM4
P5
GPIOB5
TAPWM5
TBPWM5
P6
GPIOB6
TAPWM6
TBPWM6
GPIOC
P4
GPIOC4
TBPWM4
TCPWM4
TCIDX
USBMOSI
USCSCLK
CANRXD
I2CSCL
P5
GPIOC5
TBPWM5
TCPWM5
TCPHA
USBMISO
USCSS
CANTXD
I2CSDA
GPIOD
P0
GPIOD0
TBPWM0
TCPWM0
TDIDX
USCSCLK
CANTXD
EMUXD
P1
GPIOD1
TBPWM1
TCPWM1
TDPHA
USCSS
CANRXD
EMUXC
P2
GPIOD2
TBPWM2
TCPWM2
TDPHB
USCMOSI
GPIOE
P0
GPIOE0
TCPWM4
TDPWM0
TAIDX
TBIDX
USCSCLK
I2CSCL
EMUXC
P1
GPIOE1
TCPWM5
TDPWM1
TAPHA
TBPHA
USCSS
I2CSDA
EMUXD
P2
GPIOE2
TCPWM6
TDPWM2
TAPHB
TBPHB
USCMOSI
CANRXD
EXTCLK
P3
GPIOE3
TCPWM7
TDPWM3
FRCLK
USCMISO
CANTXD
GPIOF
P0
GPIOF0
TCPWM0
TDPWM0
TMS/SWDCLK
TBIDX
USBSCLK
TRACECLK
P1
GPIOF1
TCPWM1
TDPWM1
TMS/SWDIO
TBPHA
USBSS
TRACED0
P2
GPIOF2
TCPWM2
TDPWM2
TDI
TBPHB
USBMOSI
TRACED1
P3
GPIOF3
TCPWM3
TDPWM3
TDO
FRCLK
USBMISO
TRACED2
P4
GPIOF4
TCPWM4
TDPWM4
TCIDX
USDSCLK
TRACED3
EMUXC

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P5
GPIOF5
TCPWM5
TDPWM5
TCPHA
USDSS
EMUXD
P6
GPIOF6
TCPWM6
TDPWM6
TCPHB
USDMOSI
CANRXD
I2CSCL
For more information on how to configure the DPM for the PAC2514X, see the PAC55XX
Family User Guide.

PAC2514x Users Guide Preview
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6 CONFIGURABLE POWER MANAGER
6.1 Features
▪High Voltage BUCK
▪High Voltage Charge Pump for CHG/DSG high-side gate driver supply
▪4 additional Linear regulators with power and hibernate management
▪High-accuracy voltage reference for ADC and comparators
▪Power and temperature monitor, warning, fault detection
▪Extremely low hibernate mode IQ of 3µA at 80V
6.2 System Block Diagram
Figure 6-1 Power Manager System Block Diagram
POWER MANAGER
VP VOLTAGE
SETTING
POWER
OK & O VP
LINEAR
REG
VSYS
HIBERNATE
2.5V VREF
POWER
& TEMP
MON
VMON
VTEMP
HIGH VOLTAGE BUCK CONTROLLER (HV-BUCK)
-
ERROR
AMP
+
-
COMP &
CURR LIMIT
ERROR
COMP
-
+
START UP &
MODE CTRL
PWM
LOGIC
CLAMP
DRIVER DRM
MUX
CURR
SENSE-
+CSM
+
SRC
BST
1.2V
REG +5V_INT
LINEAR
REG
LINEAR
REG
VCORE
LINEAR
REG
VCC18VCCIO
REGO
BAT
VCP CHARGE
PUMP
CONTROL
HIGH VOLTAGE CHARGE PUMP
(HVCP)
POWER MONITOR
LDOs
VIN
0.5V VREF
BATOV
AFECTL1.HVCPEN
PWRFAULT
+
-
+
PWRFAULT.HVCPFLT
BATOVDAC
PWRFAULTEN.HVCPFLTEN
BATOVCFG
BATRTS.BATOV_RTS
PWRFAULTEN
BATFLT.BATOVFLT
BATFAULTEN.BATOVFLTEN
1/50
Vref 2.5V
PROTEN.BATOVCPROTEN
PROTEN.BATOVCPROTEN
FAULT/
PROTECT
BATOV-
DAC
LINEAR
REG
VCC33
6.3 Functional Description
The Configurable Power Manager (Figure 6-1) is optimized to efficiently provide “all-in-one”
power management required by the PAC and associated application circuitry. It incorporates a
high-voltage power supply controller that is used to convert power from a DC input source to

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generate a main supply output VP. There are also linear regulators to provide VSYS, VCC33
and VCORE supplies for 5V system, 3.3V mixed signal and micro-controller core circuitry. The
power manager also handles system functions including internal reference generation, timers,
hibernate mode management, and power and temperature monitoring.
The three other linear regulators provide VCCIO, VCC33, VCC18 and VCORE supplies for 3.3V I/O,
3.3V mixed signal, 1.8V analog and 1.9V microcontroller core circuitry. The power manager also
handles system functions including internal reference generation, timers, hibernate mode
management, and power and temperature monitoring.
It incorporates a High-Voltage Charge Pump (HVCP) to efficiently convert power from the
battery stack to generate a gate driver VCP.
Hibernate Mode
Hibernate mode on the device allows a very low IQ mode when not in operation to minimize
energy consumption when the motor is not running, and the battery pack need not provide
power. See control registers in Register 8-6.
To enter hibernate mode, configure the SOC.HIBCTL register settings, and the set
SOC.HIBENTER.HIB to 1b. This bit will be automatically cleared when exiting hibernate.
To wake-up from hibernate mode the user may either use the Hibernate Wake-up Timer, the
Push-button function or PACK+ detection. Before entering hibernate mode, one of these
methods should be configured.
Push Button
Before entering hibernate mode by setting SOC.HIBENTER.HIB to 1b, the system could be
configured to exit hibernate mode with a properly polarized push button assertion, by setting the
SOC.HIBCTL.PBWAKEEN bit to 1d.
The Push Button wake up method is selected by configuring the SOC.HIBCTL.WAKESRC to
0d.
Charger Pack+ Wake Up
Before entering hibernate mode by setting SOC.HIBENTER.HIB to 1b, the system could be
configured to exit hibernation mode by detecting the moment in which the battery pack is
connected to a charger, or a load, by setting the SOC. HIBCTL.HIB to 1b.
The Push Button wake up method is selected by configuring the SOC. HIBCTL.WAKESRC to
1d.
Wake Up Timer
Before entering hibernate mode by setting SOC.HIBENTER.HIB to 1b, the system could be
configured to periodically exit hibernate mode by configuring the SOC. HIBCTL.WUTIMER from