Quantum QDFLD25-***MUH1I Series User manual
Solid‐StateIDEFlashDrive
(NoMovingParts)
Capacity:128MB‐16GB
ATA‐5Compatible
ATATransfermodes:
PIO0‐6,MWDMA0‐4
SupportsTrueIDEandPCCard
MemoryandI/OModes
FormFactors:
2.5‐inchRuggedized
Enclosure
with44‐pinIDEConnector
EnduranceGuaranteeof
4,000,000
Write/EraseCycles
MasterorSlaveSelectby
Jumper
5Vor3.3VPowerSupply
CommercialandIndustrial
OperatingTemperature
Range
5‐ByteDetection,4‐Byte
CorrectionECCEngine
10YearDataRetention
RoHS‐6Compliant
QuantumDigitalFlashDrive
GeneralDescriptionandKeyFeatures
QuantumDigital’sflashstoragecomplieswithindustry’sstandardsandglobal
regulatorycompliance.Eachdeviceincorporatesaproprietaryflashcontroller
andSLCSamsungNandFlashMemorythatprovidesthegreatestflexibilityto
customer‐specificapplicationswhilesupportingkeyflashmanagement
featuresresultingintheindustry’shighestreliabilityandenduranceKey
featuresinclude:
Built‐inECCenginedetectsupto5‐byteandcorrectsupto4‐byteerrors.
Sophisticatedblockmanagementandwearlevelingalgorithmsguarantees
4,000,000write/erasecycles.
Power‐downdataprotectionensuresdataintegrityanderrorsincaseof
powerlossLifecyclemanagementfeatureallowsuserstomonitorthedevice’s
blockmanagement.
QuantumDigital’s2.5”IDEFlashDriveistheproductofchoiceinapplications
requiringhighreliabilityandhightolerancetoshock,vibration,humidity,
altitude,ESD,andtemperature.Theruggedindustrialdesigncombinedwith
industrialtemperature(‐40°Cto85°C)testingandadherencetorigidJEDEC
JESD22standardsensuresflawlessexecutionintheharshestenvironments.
Inadditiontocustomhardwareandfirmwaredesigns,QuantumDigitalalso
offersvalue‐addedservicesincluding:
•Customlabelingandpackaging.
•CustomsoftwareimagingandIDstrings.
•FullBOMcontrolandproductchangenotification
•Totalsupply‐chainmanagementtoensurecontinuityofsupply.
•In‐fieldapplicationengineeringtohelpcustomersthroughproduct
designing
QDFLD25-xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
OrderingInformation:IDEFlashDrive
OrderingInformation:
Part Number Form Factor Capacity
QDFLD25-128MUH1(I) 2.5-inch/44-pin 128 Mbytes
QDFLD25-256MUH1(I) 2.5-inch/44-pin 256 Mbytes
QDFLD25-512MUH1(I) 2.5-inch/44-pin 512 Mbytes
QDFLD25-1GUH1(I) 2.5-inch/44-pin 1 GByte
QDFLD25-2GUH1(I) 2.5-inch/44-pin 2 GBytes
QDFLD25-4GUH1(I) 2.5-inch/44-pin 4 GBytes
QDFLD25-8GUH1(I) 2.5-inch/44-pin 8 GBytes
QDFLD25-16GUH1(I) 2.5-inch/44-pin 16 GBytes
QDFLD = QDT standard 2.5” IDE Flash Drive part number prefix.
25 = 2.5-inch form factor.
(M/G)=proceedingcapacity(xxx)isinMegabytes(M)orGigabytes(G).
H1 = QDT H1 controller.
U=RoHS‐6compliantlead‐free.
Partnumberswithout(I)=Commercialtemperaturerange(0ºCto70ºC).
(I)=Industrialtemperaturerange(‐40ºCto+85ºC).
F = media set to fixed storage for non - removable IDE applications. Use with operating systems, such as
Windows XP, that require storage media to be identified as a fixed drive before it can be used as a bootable
drive.
QDFLD25-xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
i
CONTENTS
1. INTRODUCTION.................................................................................................................................... - 1-
1.1. SCOPE..................................................................................................................................................- 2-
1.2. SYSTEM FEATURES .............................................................................................................................-2-
1.3. ATA/ATAPI-6 STANDARD ................................................................................................................... - 2-
1.4. TECHNOLOGY INDEPENDENCE -STATIC WEAR LEVELING................................................................ - 2-
1.5. CONFORMAL COATING ........................................................................................................................ - 3-
2. PRODUCT SPECIFICATIONS ................................................................................................................. - 4-
2.1. SYSTEM ENVIRONMENTAL SPECIFICATIONS ......................................................................................- 4-
2.2. SYSTEM POWER REQUIREMENTS ....................................................................................................... - 4-
2.3. SYSTEM PERFORMANCE ..................................................................................................................... - 4-
2.4. SYSTEM RELIABILITY.......................................................................................................................... - 5-
2.5. PHYSICAL SPECIFICATIONS ................................................................................................................ - 5-
2.6. CAPACITY SPECIFICATIONS................................................................................................................. - 6-
3. INTERFACE DESCRIPTION ................................................................................................................... - 7-
3.1. PHYSICAL DESCRIPTION ..................................................................................................................... - 7-
3.2. PIN ASSIGNMENTS ..............................................................................................................................- 7-
3.3. ELECTRICAL DESCRIPTION................................................................................................................. - 8-
3.4. ELECTRICAL SPECIFICATION.............................................................................................................. - 9-
3.4.1. ABSOLUTE MAXIMUM RATING......................................................................................................... - 9-
3.4.2. RECOMMENDED OPERATING CONDITION ....................................................................................... - 9-
3.4.3. DC CHARACTERISTICS................................................................................................................... - 10 -
QDFLD25-xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
ii
3.4.4. TIMING SPECIFICATIONS............................................................................................................... - 10 -
4. COMMAND DESCRIPTIONS ................................................................................................................ - 16-
4.1. COMMAND SET..................................................................................................................................- 16 -
5. INSTALLATION PROCEDURE .............................................................................................................. - 17-
5.1. BEFORE UNPACKING ......................................................................................................................... - 17-
5.2. ESD PRECAUTIONS........................................................................................................................... - 17-
5.3. IDE DEVICE SETUP /AUTO-DETECTION..........................................................................................- 17 -
5.4. PARTITION &FORMAT ...................................................................................................................... - 18-
APPENDIX A. ORDERING INFORMATION ....................................................ERROR!BOOKMARK NOT DEFINED.
PART NUMBER LIST:.......................................................................................ERROR!BOOKMARK NOT DEFINED.
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 1 -
1. Introduction
The Industrial 2.5” PATA (IDE) SSD products are designed to follow ATA/ATAPI-6 standard. The main used Flash
memories are Samsung SLC-NAND Type Flash memory chips from 128MB up to 8GB, and Micron SLC-NAND Type
Flash memory chips for 16GB only. The operating temperature grade is optional for standard grade 0°C ~ 70°C and
industrial grade -40°C ~ +85°C. The Industrial 2.5” PATA (IDE) SSD are designed electrically compliant with the
conventional IDE hard disk and support True IDE Mode. The data transfer modes supports PIO 0~4, MWDMA 0~2, or
UDMA 0~4; Default setting are PIO mode-4 or UDMA-4. 2.5” PATA (IDE) SSD features an extremely light weight, reliable,
low-profile form factor.
The Industrial 2.5” PATA (IDE) SSD provides a high level interface to the host computer. This interface allows a host
computer to issue commands to the SSD to read or write blocks of memory. The host addresses the card in 512 byte
sectors. Each sector is protected by a powerful 4 bits Error Correcting Code (ECC). The Industrial 2.5” PATA (IDE) SSD,
it uses intelligent controller which manages interface protocols, data storage and retrieval as well as ECC, defect handling
and diagnostics, power management and clock control.
Figure 1 shows a block diagram of the used high tech Industrial 2.5” PATA (IDE) SSD controller.
Figure 1: 2.5” PATA (IDE) SSD Controller Block Diagram
ATA Host
ATA Interface
Data Signal
Control & Address
Signal
Buffer
Management
and Control
Micro
Processor
RAM ROM
Code
EDC/ECC
Circuit
Flash
Sequencer
and Control
Logic
Flash Flash
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 2 -
1.1. Scope
This document describes the features and specifications and installation guide of the Industrial 2.5” PATA (IDE) SSD.
1.2. System Features
zNon-volatile memory and no moving parts
zSLC NAND type flash technology
z2.5” IDE drive form-factor
zExtremely rugged metal casing to endure harsh environments
zDisk capacity from 128MB to 16GB
zATA interface and True IDE mode
zMaster/Slave Switch
zData transfer supports PIO-4 and UDMA-4 (Default setting)
zPerformance up to 40.0MB/sec
zAutomatic 4 bits error correction and retry capabilities
zSupports power down commands and Auto stand-by / sleep modes.
z+5 V ±10％operation
zWorking well in critical environment
zVery high performance, very low power consumption
zLow weight, Noiseless
zOptional for conformal-coating special PCB surface coating treatment
1.3. ATA/ATAPI-6 Standard
The Industrial 2.5” PATA (IDE) SSD disks are fully compatible with the ATA/ATAPI-6 standard.
1.4. Technology Independence - Static Wear Leveling
In order to gain the best management for flash memory, the Industrial Rugged Metal 2.5” PATA (IDE) SSD supports
Static Wear-leveling technology to manage the Flash system. The life of flash memory is limited; the management
is to increase the life of the flash product.
A static wear-leveling algorithm evenly distributes data over an entire Flash cell array and searches for the least used
physical blocks. The identified low cycled sectors are used to write the data to those locations. If blocks are empty, the
write occurs normally. If blocks contain static data, it moves that data to a more heavily used location before it moves the
newly written data. The static wear leveling maximizes effective endurance Flash array compared to no wear leveling or
dynamic wear leveling.
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 3 -
1.5. Conformal coating
Conformal coating is a protective, dielectric coating designed to conform to the surface of an assembled printed circuit
board. Commonly used conformal coatings include silicone, acrylic, urethane and epoxy. We apply only silicone on our
storages products upon requested especially by customers. The type of silicone coating features good thermal shock
resistance due to flexibility. It is also easy to apply and repair.
Conformal coating offers protection of circuitry from moisture, fungus, dust and corrosion caused by extreme
environments. It also prevents damage from those Flash storages handling during construction, installation and use, and
reduces mechanical stress on components and protects from thermal shock. The greatest advantage of conformal coating
is to allow greater component density due to increased dielectric strength between conductors.
We use MIL-I-46058C silicon conformal coating.
2. Product Specifications
For all the following specifications, values are defined at ambient temperature and nominal supply voltage unless
otherwise stated.
2.1. System Environmental Specifications
Table 1: Environmental Specification
The Industrial 2.5” PATA (IDE) SSD Standard Grade Industrial Grade
Temperature Operating:
Non-operating:
0ºC ~ +70ºC
-20ºC ~ +80ºC
-40ºC ~ +85ºC
-50ºC ~ +95ºC
Humidity Operating & Non-operating:
10% ~ 95% non-condensing
Vibration Operating & Non-operating: 15G compliance to MIL-STD-810F
Shock Operating & Non-operating: 1,500G compliance to MIL-STD-810F
Altitude Operating & Non-operating: 70,000 feet
2.2. System Power Requirements
Table 2: Power Requirement
The Industrial 2.5” PATA (IDE) SSD Standard Grade Industrial Grade
DC Input Voltage (VCC) 100mV max. ripple(p-p) +5 V ±10％
+5V Current
(Maximum average value)
Reading Mode : 124.0 mA (Max.)
Writing Mode : 121.0 mA (Max.)
Idle Mode : 1.8 mA (Max.)
2.3. System Performance
Table 3: System Performances
Data Transfer Mode supporting
- PIO mode: 0,1,2,3,4, (Default PIO-4)
- MWDMA mode: 0,2
- UDMA Mode: 0,1,2,3,4 (Default UDMA-4)
Data Transfer Rate To/Form Host 16.6Mybtes/sec burst under PIO Mode 4
66.6Mbytes/sec burst under UDMA-4 Mode
Average Access Time 0.2 ms(estimated)
Maximum Performance Sequential Read 40 Mbytes/sec Max.
Sequential Write 20 Mbytes/sec Max.
Note:
(1). All values quoted are typically at 25oC and nominal supply voltage.
(2). Testing of the Industrial 2.5” PATA (IDE) SSD maximum performance was performed under the following platform:
- Computer with AMD 3.0GHz processor
- Windows XP Professional operating system
- IDE transfer mode: Ultra DMA mode 4
- PATA (IDE) SSD capacity: 4GB
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 5 -
2.4. System Reliability
Table 4: System Reliability
MTBF >3,000,000 hours
Wear-leveling Algorithms Static Wear Leveling
ECC Technology 4 bits per 512 bytes block
Endurance Greater than 2,000,000 cycles Logically contributed by
Wear-leveling and advanced bad sector management
Data Retention 10 years
2.5. Physical Specifications
Refer to Table 5 and see Figure 2 for Industrial 2.5” PATA (IDE) SSD physical specifications and dimensions.
Table 5: Physical Specifications
2.5” PATA (IDE) SSD
Length: 99.70 ± 0.25mm(4.0 ± 0.010 in)
Width: 69.9 ± 0.25mm(2.76 ± 0.1.010 in)
Thickness: 9.5 ± 0.25mm(0.4 ± 0.010 in)
G. W. : 115g (4.6oz)
Figure 2: 2.5” PATA (IDE) SSD
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 6 -
2.6. Capacity Specifications
The table 6 shows the specific capacity for the various models and the default number of heads, sectors/track and
cylinders.
Table 6: Device Parameter
Unformatted Capacity Default Cylinder Default Head Default Sector Default CHS
Capacity
128MB 497 16 32 254,464
256MB 984 16 32 503,808
512MB 1,001 16 63 1,009,008
1,024MB 2,002 16 63 2,018,016
2.04GB 4,003 16 63 4,035,024
4GB 8,006 16 63 8,070,048
8GB 16,000 16 63 16,128,000
16GB 32,235 16 63 32,492,880
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 7 -
3. Interface Description
3.1. Physical Description
The pin 1 ~ pin 44 are for IDE interface. The pin A ~ pin D are for option selection via physical jumpers.
Figure 3: The front view of 2.5” PATA (IDE) SSD 44-pin IDE Connector
3.2. Pin Assignments
Signals whose source is the host is designated as inputs while signals that the Industrial 44-pin micro IDE Flash (2.5”
PATA (IDE) SSD) Disk sources are outputs. The pin assignments are listed in below table 7.
Table 7: Pin Assignments
Pin No. Signal Name Description Pin No. Pin Name Description
1 HRESET Host Reset 2
GND Ground
3 HDB[7] Host Data Bit 7 4 HDB[8] Host Data Bit 8
5 HDB[6] Host Data Bit 6 6 HDB[9] Host Data Bit 9
7 HDB[5] Host Data Bit 5 8 HDB[10] Host Data Bit 10
9 HDB[4] Host Data Bit 4 10 HDB[11] Host Data Bit 11
11 HDB[3] Host Data Bit 3 12 HDB[12] Host Data Bit 12
13 HDB[2] Host Data Bit 2 14 HDB[13] Host Data Bit 13
15 HDB[1] Host Data Bit 1 16 HDB[14] Host Data Bit 14
17 HDB[0] Host Data Bit 0 18 HDB[15] Host Data Bit 15
19 GND Ground 20 KEY1Key-pin
21 DMARQ DMA Request 22 GND Ground
23
HIOW3Host I/O Write
24 24 GND
STOP4Stop Ultra DMA burst
25
HIOR3Host I/O Read
26 GND Ground
HDMARDY4Ultra DMA ready
HSTROBE4Ultra DMA data strobe
27
IORDY3I/O Ready
28 CSEL Cable select
DDMARDY4Ultra DMA ready
DSTROBE4Ultra DMA data strobe
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 8 -
29 DMACK DMA Acknowledge 30 GND Ground
31 INTRQ Interrupt Request 32 IOCS16 CS I/O 16-Bit
33 HAB[1] Host Address Bit 1 34 PDIAG Passed Diagnostic
35 HAB[0] Host Address Bit 0 36 HAB[2] Host Address Bit 2
37 CS0 Chip Select 0 38 CS1 Chip Select 1
39 DASP Drive Active 40 GND Ground
41 VCC Supply Voltage 42 VCC Supply Voltage
43 GND Ground 442NC Not Connected
In the 44-pin version, this pin is defined as KEY, according to the ATA standard.
NC = These pins are not connected internally.
Signal usage in PIO & Multiword DMA mode.
Signal usage in Ultra DMA mode.
3.3. Electrical Description
The Industrial 2.5” PATA (IDE) SSD is optimized for operation with hosts. Table 8 describes the signals of 44-pin IDE
interface.
Table 8: Signal Description
Pin No. Signal Name Type Description
1 HRESET- I Host reset signal, High: Reset.
37 CS0- I Chip select CS0
38 CS1- I Chip select CS1
31 INTRQ O Host interrupt signal.
25
HIOR-3
I
I/O read strobe signal.
HDMARDY-4DMA ready during Ultra DMA data in burst
HSTROBE4Data strobe during Ultra DMA data out burst
23
HIOW-3
I
I/O write strobe signal.
STOP4Stop during Ultra DMA data bursts
32 IOCS16- O Asserted in 16-bit access.
27
IORDY3
O
I/O Ready Signal
DDMARDY-4DMA ready during Ultra DMA data out burst
DSTROBE4Data strobe during Ultra DMA data in burst
18, 16, 14, 12,
10, 8, 6, 4, 3,
5, 7, 9, 11, 13,
15, 17
HDB[15:0] I/O Host data bus
33, 35, 36 HAB[2:0] I/O Host Address bus
28 CSEL- I I
Master/Slave select signal (cable select signal).
Low: Device operates as a master, High: Device operates as a slave.
Switch used.
39 DASP- I/O
Used as an input port to check in the master mode to see if the slave
is present or not, and as an output port to check in the slave mode to
see if the slave for the master is present or not.
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 9 -
34 PDIAG- I/O
Used as an input port to evaluate the result of slave diagnosis in the
master mode, and as an output port to return the result of diagnosis
to the master.
21 DMARQ O DMA Request.
29 DMACK- I DMA Acknowledge.
201, 412, 422VCC VCC Connect to VCC
2, 19, 22, 24,
26, 30, 40, 432GND GND
Connect to GND.
442NC N/A
Not used. Please do not connect.
In the 44-pin version, this pin is defined as KEY, according to the ATA standard.
NC = These pins are not connected internally.
Signal usage in PIO & Multiword DMA mode
Signal usage in Ultra DMA mode
3.4. Electrical Specification
Table 10, Table 11, and Table 12 defines all D.C. Characteristics for the Industrial 2.5” PATA (IDE) SSD. Unless
otherwise stated, a condition is as below Table 9:
Table 9: Electrical Condition
Standard Grade Industrial Grade
Vcch = 5V ±10%
Ta = 0°C to 70°C
Vcch = 5V ±10%
Ta = -40°C to 85°C
3.4.1. Absolute Maximum Rating
Table 10: Absolute Maximum Rating
Parameter Symbol Rating Unit
DC Power Supply VDD - VSS -0.3 ~ +5.5 V
Input voltage VIN V
SS-0.3 ~ VDD+0.3 V
Output voltage VOUT V
SS-0.3 ~ VDD+0.3 V
Operating Temperature TAStandard: -10 ~ +70 °C
Industrial: -40 ~ +85 °C
Storage Temperature TST Standard: -20 ~ +80 °C
Industrial: -50 ~ +95 °C
3.4.2. Recommended Operating Condition
Table 11: Recommended Operating Condition
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 10 -
3.4.3. DC Characteristics
Table 12: DC Characteristics
Parameter Symbol Value Unit
Min Standard Max
Power Supply VCCH 4.5 5.0 5.5 V
Power Supply VCCF 3.0 3.3 3.6 V
Input low voltage VIL -0.3 0.8 V
Input high voltage VIH 2.0 Vcc+0.3 V
Output low voltage VOL
0.45 (at
4mA) V
Output high voltage VOH 2.4 (at
1mA) V
Operating CurrentV
Sleep Mode
Operation
Icc
1.4
140
mA
mA
Input Leakage Current ILI ±10 uA
Output leakage current LLO ±10 μA
Input/output Capacitance CI/O 10 pF
3.4.4. Timing Specifications
PIO Mode
Figure 4: Read/Write Timing Diagram, PIO Mode
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 11 -
Table 13: Read/Write Timing Specifications, PIO Mode 0-4
PIO timing parameters Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
t0Cycle time (min.) 600 383 240 180 120
t1Address valid to HIOR-/HIOW- setup (min.) 70 50 30 30 25
t2HIOR-/HIOW- 16-bit (min.) 165 125 100 80 70
t2HIOR-/HIOW- Register 8-bit (min.) 290 290 290 80 70
t2i HIOR-/HIOW- recovery time (min.) - - - 70 25
t3HIOW- data setup (min.) 60 45 30 30 20
t4HIOW- data hold (min.) 30 20 15 10 10
t5HIOR- data setup (min.) 50 35 20 20 20
t6HIOR- data hold (min.) 5 5 5 5 5
t6z HIOR- data tri-state (max.) 30 30 30 30 30
t7Address valid to IOCS16- assertion (max.) 90 50 40 n/a n/a
t8Address valid to IOCS16- released (max.) 60 45 30 n/a n/a
t9HIOR-/HIOW- to address valid hold 20 15 10 10 10
tRD Read data valid to IORDY active (min.) 0 0 0 0 0
tAIORDY setup time 35 35 35 35 35
tBIORDY pulse width (max.) 1250 1250 1250 1250 1250
tCIORDY assertion to release (max.) 5 5 5 5 5
Multiword DMA
Figure 5: Read/Write Timing Diagram, Multiword DMA Mode
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 12 -
Table 14: Read/Write Timing Specifications, Multiword DMA Mode 0-2
Multiword DMA timing parameters Mode 0 Mode 1 Mode 2
t0Cycle time (min.) 480 150 120
tDHIOR-/HIOW- assertion width (min.) 215 80 70
tEHIOR- data access (max.) 150 60 50
tFHIOR- data hold (min.) 5 5 5
tGHIOR-/HIOW- data setup (min.) 100 30 20
tHHIOW- data hold (min.) 20 15 10
tIDMACK to HIOR-/HIOW- setup (min.) 0 0 0
tJHIOR-/HIOW- to DMACK hold (min.) 20 5 5
tKR HIOR- negated width (min.) 50 50 25
tKW HIOW- negated width (min.) 215 50 25
tLR HIOR- to DMARQ delay (max.) 120 40 35
tLW HIOW- to DMARQ delay (max.) 40 40 35
tMCS1-, CS0- valid to HIOR-/HIOW- 50 30 25
tNCS1-, CS0- hold 15 10 10
tZDMACK- 20 25 25
Ultra DMA mode
Figure 6: Ultra DMA Mode Data-in Burst Initiation Timing Diagram
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 13 -
Figure 7: Ultra DMA Mode Data-out Burst Initiation Timing Diagram
Figure 8: Sustained Ultra DMA Mode Data-in Burst Timing Diagram
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 14 -
Figure 9: Sustained Ultra DMA Mode Data-out Burst Timing Diagram
Table 15: Timing Diagram, Ultra DMA Mode 0-4
Ultra DMA timing parameters Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
t2CYC Typical sustained average two cycle time 240 - 160 - 120 - 90 - 60 -
tCYC
Cycle time allowing for asymmetry and
clock variations (from STROBE edge to
STROBE edge)
112 - 73 - 54 - 39 - 25 -
t2CYC
Two cycle time allowing for clock variations
(from rising edge to next rising edge or from
falling edge to next falling edge of
STROBE)
230 - 153 - 115 - 86 - 57 -
tDS Data setup time (at recipient) 15 - 10 - 7 - 7 - 5 -
tDH Data hold time (at recipient) 5 - 5 - 5 - 5 - 5 -
tDVS Data valid setup time at sender (from data
bus being valid until STROBE edge) 70 - 48 - 31 - 20 - 6.7 -
tDVH
Data valid hold time at sender (from
STROBE edge until data may become
invalid)
6.2 - 6.2 - 6.2 - 6.2 - 6.2 -
tFS
First STROBE time (for device to first
negate DSTROBE from STOP during a data
in burst)
- 230 - 200 - 170 - 130 - 120
Ultra DMA timing parameters Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100
tMLI Interlock time with minimum 20 - 20 - 20 - 20 - 20 -
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 15 -
Ultra DMA timing parameters Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tUI Unlimited interlock time 0 - 0 - 0 - 0 - 0 -
tAZ Maximum time allowed for output drivers to
release (from being asserted or negated) - 10 - 10 - 10 - 10 - 10
tZAH Minimum delay time required for output
drivers to assert or negate (from released
state)
20 - 20 - 20 - 20 - 20 -
tZAD 0 - 0 - 0 - 0 - 0 -
tENV Envelope time (from DMACK- to STOP and
HDMARDY- during data out burst initiation) 20 70 20 70 20 70 20 55 20 55
tRFS
Ready-to-final-STROBE time (no STROBE
edges shall be sent this long after negation
of DMARDY-)
- 75 - 70 - 60 - 60 - 60
tRP
Ready-to-pause time (time that recipient
shall wait to initiate pause after negating
DMARDY-)
160 - 125 - 100 - 100 - 100 -
tIORDYZ Pull-up time before allowing IORDY to be
released - 20 - 20 - 20 - 20 - 20
tZIORDY Minimum time device shall wait before
driving IORDY 0 - 0 - 0 - 0 - 0 -
tACK Setup and hold times for DMACK- (before
assertion or negation) 20 - 20 - 20 - 20 - 20 -
tSS
Time from STROBE edge to negation of
DMARQ or assertion of STOP (when
sender terminates a burst)
50 50 - 50 - 20 - 20 -
QDFLD25‐xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 16 -
4. Command Descriptions
4.1. Command Set
The following table summarizes the command defined in ATAPI-6 specification and lists the commands
supported by the controller.
Table 16: IDE Commands
Command Name Command Code
Check Power Mode 98H or E5H
Execute Device Diagnostic 90H
Erase Sector C0H
Format Track 50H
Identify Device ECH
Idle 97H or E3H
Idle immediate 95H or E1H
Initialize Device Parameters 91H
NOP 00H
Read Buffer E4H
Read Long Sector 22H or 23H
Read Multiple C4H
Read Sector 20H or 21H
Read Verify Sector 40H or 41H
Recalibrate 1XH
Seek 7XH
Set Features EFH
Set Multiple Mode C6H
Set Sleep Mode 99H or E6H
Standby 96H or E2H
Standby Immediate 94H or E0H
Write Buffer E8H
Write Long Sector 32H or 33 H
Write Multiple C5H
Write Sector 30H or 31H
Write Verify 3CH
This manual suits for next models
18
Table of contents
Other Quantum Storage manuals
Quantum
Quantum DXi6700 series Technical manual
Quantum
Quantum DXi3500 Technical manual
Quantum
Quantum ATL StackLink User manual
Quantum
Quantum Tape Drive SDLT 600A User manual
Quantum
Quantum FastStor 1 User manual
Quantum
Quantum Scalar 218FC User manual
Quantum
Quantum Q2000 User manual
Quantum
Quantum FastStor 2 User manual
Quantum
Quantum LTO-3 User manual
Quantum
Quantum DLTtape DLT1 User manual
Quantum
Quantum Bigfoot 1.2AT User manual
Quantum
Quantum DLTtape DLT 8000 User manual
Quantum
Quantum Scalar i500 User manual
Quantum
Quantum Scalar i40 Operating and safety instructions
Quantum
Quantum StorNext QS1200 User manual
Quantum
Quantum ACL 4/52 Manual
Quantum
Quantum DXi4701 User manual
Quantum
Quantum P3000 Series User manual
Quantum
Quantum DXi V1000 Installation instructions
Quantum
Quantum ActiveScale X100 User manual
