Renesas DA16200 H/W User manual

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User Manual
DA16200 H/W Design Guide
UM-WI-006

UM-WI-006
DA16200 H/W Design Guide
NDA Confidential
User Manual
Revision 1.5
11-Apr-2022
CFR0012
2 of 44
© 2022 Renesas Electronics
Contents
Contents............................................................................................................................................... 2
Figures.................................................................................................................................................. 4
Tables ................................................................................................................................................... 4
Terms and Definitions......................................................................................................................... 5
References ........................................................................................................................................... 5
1 Introduction.................................................................................................................................... 6
2 Guidelines of Schematic Design ................................................................................................. 6
2.1 Package Type ....................................................................................................................... 7
2.1.1 48-Pin QFN............................................................................................................ 7
2.1.2 72-Pin fcCSP ......................................................................................................... 8
2.1.3 Pin Description....................................................................................................... 9
2.2 Power Supply...................................................................................................................... 11
2.2.1 Power Management............................................................................................. 11
2.2.2 VBAT.................................................................................................................... 12
2.2.3 Internal DC-DC (DCDC_LX and DCDC_FB).......................................................12
2.2.4 VDD_DA and VDD_PA........................................................................................ 12
2.2.5 VDD_ANA............................................................................................................ 13
2.2.6 VDD_DIG.............................................................................................................13
2.2.7 VDD_FDIO and FDIO_LDO_OUT....................................................................... 13
2.2.8 VDD_DIO1 and VDD_DIO2.................................................................................13
2.3 RBIAS.................................................................................................................................. 13
2.4 RF........................................................................................................................................ 14
2.4.1 Antenna................................................................................................................ 14
2.4.2 Antenna Information of DA16200MOD................................................................ 14
2.4.3 RF Input Requirements........................................................................................ 16
2.5 Clock ...................................................................................................................................16
2.5.1 RF Main Clock (40 MHz) .....................................................................................16
2.5.1.1 40 MHz RF XTAL Trimming ............................................................ 17
2.5.2 RTC Clock (32.768 KHz)..................................................................................... 19
2.6 Serial Flash ......................................................................................................................... 20
2.6.1 Serial Flash Interface........................................................................................... 20
2.6.2 Serial Flash Selection Guide ............................................................................... 20
2.7 External Control Pins ..........................................................................................................23
2.7.1 RTC Power Key (RTC_PWR_KEY) .................................................................... 23
2.7.1.1 Input High/Low Voltage of RTC Block.............................................23
2.7.1.2 Power On Sequence........................................................................ 23
2.7.2 RTC Wakeup Key (RTC_WAKE_UP and RTC_WAKE_UP2) ............................24
2.7.2.1 Input High/Low Voltage of RTC Block.............................................24
2.7.2.2 Pull-Down Resistor..........................................................................24
2.7.2.3 GPIO Wakeup Pin ........................................................................... 24
2.8 RTC_GPO........................................................................................................................... 25
2.9 GPIO Pin Multiplexing.........................................................................................................25
2.10 Interface Pull-Up ................................................................................................................. 28
2.10.1 I2C ....................................................................................................................... 28

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2.10.2 SDIO.................................................................................................................... 29
3Application Schematic ................................................................................................................ 30
3.1 DA16200 QFN, 1.8 V Flash Memory .................................................................................. 30
3.2 DA16200 QFN, 3.3 V Flash Memory .................................................................................. 32
3.3 DA16200 fcCSP, Normal TX Power Mode, 1.8 V Flash Memory.......................................34
3.4 DA16200 fcCSP, Low TX Power Mode, 1.8 V Flash Memory............................................36
4 PCB Layout Example .................................................................................................................. 38
4.1 Grounding ........................................................................................................................... 38
4.2 PCB Layout Example: DA16200MOD ................................................................................39
5 Recommended Footprint............................................................................................................ 41
Revision History ................................................................................................................................ 42

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Figures
Figure 1: DA16200 QFN48 Pinout Diagram (Top View) ....................................................................... 7
Figure 2: DA16200 fcCSP72 Pinout Diagram (Top View)..................................................................... 8
Figure 3: Power Management Block Diagram.....................................................................................11
Figure 4: High/Low Tx Power Mode Connection................................................................................. 13
Figure 5: Tested Antenna Dimension.................................................................................................. 14
Figure 6: Tested Antenna Usage ........................................................................................................ 15
Figure 7: Tested Antenna Radiation Pattern.......................................................................................15
Figure 8: LC Filter Circuit.....................................................................................................................16
Figure 9: LC Filter Layout.................................................................................................................... 16
Figure 10: Setup for Transmitting CW Tx Power ................................................................................ 18
Figure 11: Read XTAL Value............................................................................................................... 18
Figure 12: Write New XTAL Value ...................................................................................................... 19
Figure 13: Serial Flash Application Schematic....................................................................................20
Figure 14: Part Name Description.......................................................................................................22
Figure 15: RTC_PWR_KEY Circuit..................................................................................................... 24
Figure 16: RTC_WAKE_UP Circuit..................................................................................................... 24
Figure 17: I2C Pull-Up Resistors.........................................................................................................28
Figure 18: SDIO Pull-Up Resistors......................................................................................................29
Figure 19: Application Schematic –QFN, 1.8 V Flash........................................................................ 30
Figure 20: Application Schematic –QFN, 3.3 V Flash........................................................................ 32
Figure 21: Application Schematic –fcCSP, 1.8 V Flash, Normal Tx Power Mode............................. 34
Figure 22: Application Schematic –fcCSP, 1.8 V Flash, Low Tx Power Mode.................................. 36
Figure 23: Ground Vias on PAD..........................................................................................................38
Figure 24: PCB Layout Example: Top Layer.......................................................................................39
Figure 25: PCB Layout Example: 2nd Layer....................................................................................... 39
Figure 26: PCB Layout Example: 3rd Layer........................................................................................40
Figure 27: PCB Layout Example: Bottom Layer ................................................................................. 40
Figure 28: DA16200 Ground Footprint................................................................................................41
Tables
Table 1: Pin Description ........................................................................................................................ 9
Table 2: Pin Type Definition ................................................................................................................ 10
Table 3: Power Pin Descriptions .........................................................................................................12
Table 4: WLAN Crystal Clock Requirements ...................................................................................... 16
Table 5: Selected Main RF XTAL Specification .................................................................................. 17
Table 6: RTC Crystal Requirements ...................................................................................................19
Table 7: Connections Between DA16200 and Serial Flash ................................................................ 20
Table 8: Recommended Serial Flash List ...........................................................................................21
Table 9: New Flash Verification Process............................................................................................. 22
Table 10: DC Parameters for RTC Block, 3.3 V VBAT .......................................................................23
Table 11: DC Parameters for RTC Block, 2.1 V VBAT .......................................................................23
Table 12: DA16200 Pin Multiplexing ................................................................................................... 26
Table 13: Parameters from I2C Specification...................................................................................... 28
Table 14: Component for DA16200 QFN, 1.8 V Flash Mode..............................................................31
Table 15: IO Power Domain................................................................................................................ 31
Table 16: Components for DA16200 QFN, 3.3 V Flash Mode............................................................ 33
Table 17: IO Power Domain................................................................................................................ 33
Table 18: Components for DA16200 fcCSP, 1.8 V Flash, Normal Power Mode................................ 35
Table 19: IO Power Domain................................................................................................................ 35
Table 20: Components for DA16200 fcCSP, 1.8 V Flash, Low Power Mode..................................... 37
Table 21: IO Power Domain................................................................................................................ 37

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Terms and Definitions
PCB Printed Circuit Board
QFN Quad Flat No-Leads
RF Radio Frequency
GPIO General Purpose In/Out
DCDC Direct Current Direct Current
LDO Low Dropout
RTC Real-Time Clock
SFDP Serial Flash Discoverable Parameters
QSPI Quad Serial Peripheral Interface
SPI Serial Peripheral Interface
AMBA Advanced Microcontroller Bus Architecture
References
[1] <DA16200>, Datasheet, Dialog Semiconductor
[2] UM-WI-011, DA16200 Mass Production User Manual
[3] UM-WI-004, DA16200 AT GUI Tool User Manual

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1 Introduction
This document provides a set of guidelines that help users prepare schematics and PCB layouts for
products with the DA16200. Recommended schematic, chip interfaces, and surrounding components
as well as PCB layout guidelines of both devices are provided.
2 Guidelines of Schematic Design
The DA16200 application schematic includes the following five parts:
●Power supply: Digital Power Supply, Analog Power Supply
●RF: contains antenna part
●Clock: Main Clock, RTC Clock
●Flash interface
●Digital I/O: GPIO pin assignment, can be changed based on application requirement
To choose the proper schematic, check the items below:
●Package type: the DA16200 provides QFN and fcCSP packages
●VDD of flash memory: 1.8 V and 3.3 V VDD of flash memory are possible with the DA16200.
When 1.8 V VDD of flash memory is applied, the DA16200 can control the flash memory through
VDD_FDIO/FDIO_LDO_OUT (QFN pin 20 and 21, fcCSP pin M4). When 3.3 V VDD of flash
memory is applied, additional switch is needed to control flash memory to achieve low power
●Tx power mode: the fcCSP type can support normal or low Tx power mode. See 5.5 Current
Consumption in the DA16200 datasheet. For the application which doesn’t need higher Tx power,
the low Tx power mode can be applied. The QFN type supports only normal Tx power mode. See
Sections 2.2.4 and 3.4 how to apply the low Tx power mode
See Section 3 for information on each application.

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2.1 Package Type
The DA16200 provides two types of package –6x6 48-pin QFN and 3.8x3.8 72-pin fcCSP.
2.1.1 48-Pin QFN
Figure 1: DA16200 QFN48 Pinout Diagram (Top View)

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2.1.2 72-Pin fcCSP
A7
VDD_DA
/PA
A9
GND
A11
ANT
A1
GND
B6
GND
B8
VDD_DA
/PA
B10
GND
B12
GND
B4
RTC_XI
C5
RTC_XO
C7
GND
C9
GND
C11
GND
C1
VDD_DI
O1
D6
RTC_WA
KE_UP
D8
GND
D10
GND
D2
GPIOA5
E5
GND
E7
RTC_GP
O
E9
GND
E11
RBIAS
E3
GPIOA6
E1
GPIOA7
F6
GND
F8
GND
F10
GND
F12
GND
F4
GPIOA4
F2
GPIOA10
G5
GND
G7
GND
G9
GND
G11
RF_XI
G3
GPIOA8
G1
GPIOA11
H6
RTC_WA
KE_UP2
H8
GND
H10
GND
H12
RF_XO
H4
GND
H2
GPIOA9
J5
F_CSN
J7
F_IO2
J9
TCLK
J11
TMS
J3
GND
J1
DCDC_FB
K6
F_IO3 K8
F_IO0
K4
F_CLK
K2
GND
L5
GND
L7
F_IO1
L9
UART_T
XD
L11
GPIOC6
L1
DCDC_LX
M6
GND M8
DIO2
M10
UART_R
XD
M12
GND
M4
VDD_FDI
O
M2
VBAT
L3
VDD_DI
G
K12
GPIOC7
K10
GPIOC8
D12
VDD_AN
A
A5
RTC_PWR_
KEY
C3
GPIOA1
D4
GPIOA3
B2
GPIOA2
A3
GPIOA0
Figure 2: DA16200 fcCSP72 Pinout Diagram (Top View)

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2.1.3 Pin Description
Table 1: Pin Description
QFN
#Pin
fcCSP
#Pin
Pin Name
Type
(Table 2)
Drive
(mA)
Initial
State
(Note 1)
Description
1
GND
GND
Ground
2
D12
VDD_ANA
VDD
RF VDD
3
E11
RBIAS
AIO
External reference resistor pin
4
G11
RF_XI
AI
40 MHz crystal clock input
5
H12
RF_XO
AO
40 MHz crystal clock output
6
J11
TMS
DIO
2/4/8/12
I-PU
JTAG I/F, SWDIO
7
J9
TCLK
DIO
2/4/8/12
I-PD
JTAG I/F, SWCLK, General Purpose
I/O
8
K10
GPIOC8
DIO
2/4/8/12
I-PD
General Purpose I/O
9
K12
GPIOC7
DIO
2/4/8/12
I-PD
General Purpose I/O
10
L11
GPIOC6
DIO
2/4/8/12
I-PD
General Purpose I/O
11
L9
UART_TXD
DO
2/4/8/12
O
UART transmit data
12
M10
UART_RXD
DI
2/4/8/12
I
UART receive data
13
M8
VDD_DIO2
VDD
Supply power for digital I/O
GPIOC6~GPIOC8, TMS/TCLK,
TXD/RXD
14
K8
F_IO0
DIO
External Flash Memory I/F
15
L7
F_IO1
DIO
External Flash Memory I/F
16
J7
F_IO2
DIO
External Flash Memory I/F
17
K6
F_IO3
DIO
External Flash Memory I/F
18
J5
F_CSN
DIO
External Flash Memory I/F
19
K4
F_CLK
DIO
External Flash Memory I/F
20
M4
VDD_FDIO
VDD
Flash IO Power
21
FDIO_LDO_
OUT
AIO
Flash and IO LDO output and connect
to external cap. For flash LDO
22
L3
VDD_DIG
VDD
Digital power and connect to external
cap. For DIG LDO
23
H6
RTC_WAKE
_UP2
DI
RTC block wake-up signal
24
M2
VBAT
VDD
Supply power for internal DC-DC,
DIO_LDO, and analog IP
25
L1
DCDC_LX
AIO
Connection from power MOSFETs to
the Inductor in internal DCDC
26
J1
DCDC_FB
AIO
Feedback voltage from the output of
the power supply in internal DCDC
27
G1
GPIOA11
DIO
2/4/8/12
I-PD
General Purpose I/O
28
F2
GPIOA10
DIO
2/4/8/12
I-PD
General Purpose I/O
29
H2
GPIOA9
DIO
2/4/8/12
I-PD
General Purpose I/O

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QFN
#Pin
fcCSP
#Pin
Pin Name
Type
(Table 2)
Drive
(mA)
Initial
State
(Note 1)
Description
30
G3
GPIOA8
DIO
2/4/8/12
I-PD
General Purpose I/O
31
E1
GPIOA7
DIO
2/4/8/12
I-PD
General Purpose I/O
32
E3
GPIOA6
DIO
2/4/8/12
I-PD
General Purpose I/O
33
D2
GPIOA5
DIO
2/4/8/12
I-PD
General Purpose I/O
34
F4
GPIOA4
DIO
2/4/8/12
I-PD
General Purpose I/O
35
C1
VDD_DIO1
VDD
Supply power for digital I/O
GPIOA0~GPIOA11
36
D4
GPIOA3
AI/DIO
2/4/8/12
I-PD
Aux.ADC input/General Purpose I/O
37
B2
GPIOA2
AI/DIO
2/4/8/12
I-PD
Aux.ADC input/General Purpose I/O
38
C3
GPIOA1
AI/DIO
2/4/8/12
I-PD
Aux.ADC input/General Purpose I/O
39
A3
GPIOA0
AI/DIO
2/4/8/12
I-PD
Aux.ADC input/General Purpose I/O
40
C5
RTC_XO
AO
32.768 kHz crystal clock output
41
B4
RTC_XI
AI
32.768 kHz crystal clock input
42
A5
RTC_PWR_
KEY
DI
RTC block enable signal
43
D6
RTC_WAKE
_UP
DI
RTC block wake-up signal
44
E7
RTC_GPO
DO
General Purpose Output
45
A7,
B8
VDD_DA
VDD
Tx DA power and RTC block power
46
VDD_PA
VDD
Supply power for integrated power
amplifier
47
GND
GND
Ground
48
A11
ANT
AI
ANT
fcCSP GND Pin A1, A9, B6, B10, B12, C7, C9, C11, D8, D10, E5, E9, F6, F8, F10, F12, G5, G7, G9, H4, H8,
H10, J3, K2, L5, M6, M12
Note 1 Status of RTC_PWR_KEY is asserted and digital power (VDD_DIG) is stable.
Table 2: Pin Type Definition
Pin Type
Description
Pin Type
Description
DI
Digital input
AI
Analog input
DO
Digital output
AO
Analog output
DIO
Digital input/output
AIO
Analog input/output
DIOD
Digital input/output open drain
BP
Back drive protection
PU
Pull-up resistor (fixed)
SPU
Switchable pull-up resistor
PD
Pull-down resistor (fixed)
SPD
Switchable pull-down resistor
PWR
Power
GND
Ground

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2.2 Power Supply
2.2.1 Power Management
The DA16200 has one internal DC-DC converter and multiple LDOs to supply power to all internal
sub-blocks. Power management performs the on-off control of these regulators and is implemented
through the register setting inside the RTC block.
RF Block
Digital Core /
Memory
Flash control
/ External
Flash Memory
RTC Block
DCDC
DIG_LDO
1.4V
1.1V
VDD_PA, VDD_RF
VDD_FDIO
VBAT
FDIO_LDO 1.8V
GPIOs
VDD_DIO1
VDD_DIO2
QFN,
fcCSP normal power fcCSP low power
Using the same power supply as
external device ( ex.CPU) ( 1.8V or 3.3V)
Figure 3: Power Management Block Diagram
Details of the internal DC-DC converters and LDOs are explained below:
●DC-DC converter: from the power supply of external VBAT input, it generates 1.4 V power for
the digital LDO and RF block
●LDO for digital Blocks: from the DC-DC output, it generates 1.1 V power which is used for
digital blocks
●LDO for I/O and external flash memory:
○This LDO output is used only for 1.8 V digital I/O applications
○From external VBAT power input, it generates 1.8 V output voltage which is used for digital
I/O power domain in 1.8 V digital I/O applications
○It is also used for external flash memory
○For 3.3 V digital I/O applications, external power (3.3 V) is directly supplied for digital I/O
power
●FDIO_LDO_OUT supports only 1.8 V
Internal DC-DC converters and LDOs generate enough power for all of the DA16200's internal sub-
blocks.

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Table 3: Power Pin Descriptions
QFN
#Pin
fcCSP
#Pin
Pin Name
Type
Description
1
GND
GND
Ground
2
D12
VDD_ANA
VDD
RF VDD
13
M8
VDD_DIO2
VDD
Supply power for digital I/O
GPIOC6~GPIOC8, TMS/TCLK, TXD/RXD
20
M4
VDD_FDIO
VDD
Flash IO Power
21
FDIO_LDO_OUT
AIO
Flash and IO LDO output and connect to external
capacitor for flash LDO
22
L3
VDD_DIG
VDD
Digital power and connect to external cap. for DIG
LDO
24
M2
VBAT
VDD
Supply power for internal DC-DC, DIO_LDO, and
analog IP
25
L1
DCDC_LX
AIO
Internal DC-DC feedback input for digital block
supply
26
J1
DCDC_FB
AIO
Internal DC-DC feedback output for digital block
supply
35
C1
VDD_DIO1
VDD
Supply power for digital I/O
GPIOA0~GPIOA11
45
A7
B8
VDD_DA
VDD
Tx DA power and RTC block power
46
VDD_PA
VDD
Supply power for integrated power amplifier
47
GND
GND
Ground
fcCSP GND Pin: A1, A9, B6, B10, B12, C7, C9, C11, D8, D10, F6, F8, F10, F12, G5, G7, G9, H4, H8,
H10, J3, K2, L5, M6, M12, E5
2.2.2 VBAT
The DA16200 can operate one source for an I/O interface and internal power source (LDO and DC-
DC converter), so it is important to reduce the noise component on this power line. All the input de-
coupling capacitors should be located nearby the DA61200 IC and the thickness of power traces
should be higher than 0.3 mm.
The operating voltage level of VDD is from 2.1 V to 3.6 V. This allows the use of two alkaline
batteries.
2.2.3 Internal DC-DC (DCDC_LX and DCDC_FB)
The DA16200 contains one DC-DC converter for the analog and digital parts. This DC-DC converter
needs to connect a series 4.7 µH power inductor for high-power efficiency and a shunt 10 µF
capacitor to reduce switching noise, so the inductor and capacitor should be located as close as
possible for stable power supply. And 1 µF bypass capacitors are required for the power supply.
2.2.4 VDD_DA and VDD_PA
The DA16200 supports low Tx power mode for special application which doesn’t need high Tx output
power. Only fcCSP type can support both low and normal Tx power mode and QFN package
supports normal Tx power mode only.
The difference between low and normal Tx power mode is the connection of VDD_PA and VDD_DA.
Those VDDs are connected to VBAT in normal Tx power mode and connected to DCDC output in

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low Tx power mode. See Figure 4 below for the VDD connection and refer to the application
examples of both normal and low Tx power mode in figure xx and figure xx.
Figure 4: High/Low Tx Power Mode Connection
The typical output Tx power at 1 Mbps DSSS for each mode is 18.5 dBm in normal Tx power mode
and 9.5 dBm in low Tx power mode. See the datasheet for detailed performance.
2.2.5 VDD_ANA
VDD_ANA is connected to DC-DC output.
2.2.6 VDD_DIG
VDD_DIG is not connected to the power supply but requires 470 nF bypass capacitor.
2.2.7 VDD_FDIO and FDIO_LDO_OUT
VDD_FDIO is connected to VDD of flash memory. This pin can be connected to FDIO_LDO_OUT
when 1.8 V VDD of flash memory is used.
FDIO_LDO_OUT is internal LDO output of the DA16200 for flash memory. The voltage level of
FDIO_LDO_OUT is 1.8 V, so this pin can be used when 1.8 V VDD of flash memory is used.
FDIO_LDO_OUT is turned off in sleep mode to reduce the power consumption.
When 3.3 V VDD of flash memory is used, an additional load switch to control the flash VDD is
needed to reduce the power consumption in sleep mode.
2.2.8 VDD_DIO1 and VDD_DIO2
These are I/O voltage pin of DA16200 and should be same level with I/O voltage of external IC such
as MCU. The DA16200 can support both 1.8 V and 3.3 V of I/O voltage.
2.3 RBIAS
RBIAS (#3 of QFN and #E11 of fcCSP) determine the bias current of DA16200.
1 % tolerance of 30 kΩ of resistor should be adopted to this pin to minimize the variation of current
consumption.

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2.4 RF
The RF application circuit is important to get an optimum performance from the device. An improper
circuit and layout can cause performance degradation for sensitivity, output power, error vector
magnitude (EVM) and spectral mask.
2.4.1 Antenna
The antenna is the element used to convert the guided waves on the PCB traces to free-space
electromagnetic radiation. The position and layout of the antenna is very important to increase
coverage and data rates. Section 2.4.2 has details on the tested antenna components.
2.4.2 Antenna Information of DA16200MOD
The DA16200 chip antenna type module (DA16200MOD-AAC4WA32) includes 2.4 GHz chip type
antenna. See the antenna information below.
●Part number: WALSIN RFECA32160AM1T62
○Datasheet: http://www.passivecomponent.com/wp-
content/uploads/2018/10/ASC_RFECA3216060A1T_V09.pdf
○Walsin homepage: http://www.passivecomponent.com/
○Antenna product page: http://www.passivecomponent.com/product-
search/Antenna/?c2VsZWN0%5Bseries%5D%5Bvalue%5D=Chip+Antenna+%28BT%2C+Wi
fi+BAND%29
●Dimension
Figure 5: Tested Antenna Dimension

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User Manual
Revision 1.5
11-Apr-2022
CFR0012
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●Tested Antenna usage example
Figure 6: Tested Antenna Usage
●Radiation Pattern
Figure 7: Tested Antenna Radiation Pattern

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Below is the consideration for the antenna part.
1. Put the antenna on the edge or corner of the PCB.
2. Signal lines must not be routed across the antenna elements on any layer of the PCB.
3. The ground is needed for copper keep-out on all layers, including inner layers.
4. Matching components for the antenna are needed to optimize each board.
5. The return loss measured at the matching components of the antenna needs to be better
than -10 dB to get the optimum system performance.
2.4.3 RF Input Requirements
The RF part must have matching components and an RF filter to suppress any harmonic element.
A passive filter which is made by lumped components can meet the system requirements because
the DA16200 has good harmonic suppression performance.
Figure 8: LC Filter Circuit
Figure 9: LC Filter Layout
The RF line needs to be isolated by using ground plane with clearance to ensure good performance
(output power, EVM, SEM and sensitivity).
2.5 Clock
2.5.1 RF Main Clock (40 MHz)
The DA16200 has a crystal oscillator for the main clock source, which supports the external crystal
clock. Basically, the external clock is 40 MHz. Make sure that the load capacitance is tuned based on
the board parasitic so that the frequency tolerance is within ±20 ppm. And the clock line needs to
route closer to the XTAL routing to avoid any phase noise degradation.
The recommended operating conditions are given in Table 4.
Table 4: WLAN Crystal Clock Requirements
Parameter
Condition
Min
Typ
Max
Units
Frequency
40
MHz
Frequency accuracy
Initial + temp + aging
-20
+20
ppm
Crystal ESR
50
Ω
Load Capacitance (Note 1)
6
8
10
pF
Note 1 Not exceed ±20 ppm, there is an internal adjustable shunt capacitor inside the chipset, which must be
written to the OTP block after crystal correction. There is a 0~12.7 pF tunable capacitor inside the
DA16200, to use without shunt capacitors outside, it must be selected a crystal with a load
capacitance of 6~10 pF.

UM-WI-006
DA16200 H/W Design Guide
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The selected crystal for the DA16200MOD is the 8Z40000047 of TXC. The crystal specification is
presented in Table 5.
Table 5: Selected Main RF XTAL Specification
Parameter
Symbol
Min
Typ
Max
Units
Note
Nominal Frequency
FL
40.00000
MHz
Oscillator Mode
-
Fundamental
-
Load Capacitance
CL
10
pF
Frequency Tolerance
-
±7
ppm
at 25 ℃± 3 ℃
Frequency Stability
-
±13
ppm
Over operating temp. range
(Reference 25 ℃)
Operating Temperature
-
-40
~
-85
℃
Aging
-
±1
ppm
5 years
Drive Level
DL
-
100
-
uW
Equivalent Series Resistance
Rr
-
-
30
Ω
Shunt Capacitance C0
C0
-
-
2
pF
Insulation Resistance
-
500
-
-
MΩ
at DC 100 V
Storage Temperature Range
-
-40
~
85
℃
2.5.1.1 40 MHz RF XTAL Trimming
The 40 MHz crystal oscillator has trimming capability. The frequency is trimmed by two on-chip
variable capacitor banks. Dialog provides AT GUI tool and the frequency can be tuned easily by the
tool. The tool is available on Dialog website below.
DA16200 AT GUI Tool: https://www.dialog-semiconductor.com/products/wi-fi/da16200#tab-
field_tab_content_resources
To tune the frequency on DA16200 EVK, do the following:
1. Connect DA16200 EVK to PC and run AT GUI Tool with DA16200 EVK.
○See [3] for details
2. On Certification tab, transmit CW Tx power.
a. Click Test Mode.
b. Click the Select button.
c. Click CW.
d. Select desired channel (frequency).
e. Select power level (0 is maximum power).
f. Click the Start Tx button.
g. Check the exact Tx frequency using spectrum analyzer.

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Figure 10: Setup for Transmitting CW Tx Power
3. On the OTP tab, check current internal load capacitor value of the DA16200.
a. Select the OTP Enable checkbox.
b. Click the Read XTAL button to check current internal capacitor value of the DA16200. ‘0x3a’
is the value in this example.
Figure 11: Read XTAL Value
4. On console window, write the desired value.

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a. Enter ‘AT+XTALWR=<value>’ command. <value> is desired value and seven-bits to write [h’1 ~
h’7f].
b. Click the Send button.
Figure 12: Write New XTAL Value
NOTE
If the register value is changed significantly, writing the value may not be possible. Change the
value within 10.
5. Check Tx frequency change on spectrum analyzer.
6. Repeat steps 4 and 5 to find the correct value.
Dialog highly recommend calibrating the RF XTAL on production line as the frequency tolerance of
Wi-Fi specification is within ±20 ppm. [2]describes how to adopt the calibration on mass production.
See section 5. XTAL Calibration on UM-WI-011.
In the DA16200 module (DA16200MOD), RF XTAL is calibrated. So, customer doesn’t need to think
about the calibration.
2.5.2 RTC Clock (32.768 KHz)
The 32.768 kHz RTC clock source is necessary for the free-running counter in the RTC block. The
external clock is 32.768 kHz. Make sure that the load capacitance is tuned based on the board
parasitic so that the frequency tolerance is within ±250 ppm.
The recommended operating conditions are given in Table 6.
Table 6: RTC Crystal Requirements
Parameter
Condition
Min
Typ
Max
Units
Frequency
32.768
kHz
Frequency accuracy
Initial + temp + aging
-250
+250
ppm
Crystal ESR
32.768 kHz, C1 = C2 = 9 pF
90
Ω

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2.6 Serial Flash
2.6.1 Serial Flash Interface
Serial Flash
1
2
3
4
8
7
6
5
F_CSN
F_IO1
F_IO2
F_IO0
F_CLK
F_IO3
VDD_FDIO
R5
DNI
R6
10K
R7
DNI
Figure 13: Serial Flash Application Schematic
The QSPI master supports 4-line SPI communication with commercial flash memory devices and
uses a Motorola SPI-compatible interface among SPI communication modes. The highest
communication speed is the same as the AMBA bus clock, and the speed is adjustable in integer
multiples. The designed QSPI supports 4-/2-/1-line types depending on the purpose. These types
should be combined. Especially when 1-line communication mode is used, it can be used as the SPI
master. Table 7 shows the connections between DA16200 and serial flash.
Table 7: Connections Between DA16200 and Serial Flash
DA16200
Serial Flash
Note
Pin name
QFN
fcCSP
Pin name
Pin #
F_IO0
14
K8
DI / SI / IO0
5
F_IO1
15
L7
DO / SO / IO1
2
F_IO2
16
J7
WP / IO3
3
F_IO3
17
K6
HOLD / RESET
7
F_CSN
18
J5
CSN / CSB
1
10 kΩpull-up resistor
F_CLK
19
K4
CLK / SCK
6
2.6.2 Serial Flash Selection Guide
SFDP (Serial Flash Discoverable Parameters) is a standard table for the main parameters of serial
flash defined by JEDEC. This is information about the characteristics (access timing, supported
commands, delay parameter) of each serial flash manufactured by various vendors, which should be
optimized for each serial flash.
NOTE
The FreeRTOS SDK supports flash sizes greater than 4MB.
Currently the DA16200 SDK supports SFDP tables for serial flashes listed in Table 8 below.