Renesas H8/300 Series Owner's manual

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April 1, 2003
Renesas Technology Corp.

H8/300
Programming Manual

Contents
Section 1. CPU................................................................................................... 1
1.1 General CPU Architecture............................................................................................... 2
1.2 Registers.......................................................................................................................... 5
1.3 Instructions...................................................................................................................... 8
Section 2. Instruction Set................................................................................................. 32
ADD (ADD binary) (byte) ..............................................................................................37
ADD (ADD binary) (word).............................................................................................38
ADDS (ADD with Sign extension).................................................................................39
ADDX (ADD with eXtend carry) ...................................................................................40
AND (AND logical)........................................................................................................41
ANDC (AND Control register)....................................................................................... 42
BAND (Bit AND) ...........................................................................................................43
Bcc (Branch conditionally) .............................................................................................44
BCLR (Bit CLeaR)..........................................................................................................47
BIAND (Bit Invert AND)................................................................................................ 49
BILD (Bit Invert LoaD) ..................................................................................................50
BIOR (Bit Invert OR)......................................................................................................51
BIST (Bit Invert STore)................................................................................................... 52
BIXOR (Bit Invert eXclusive OR)..................................................................................53
BLD (Bit LoaD) ..............................................................................................................54
BNOT (Bit NOT) ............................................................................................................55
BOR (Bit inclusive OR)..................................................................................................57
BSET (Bit SET)............................................................................................................... 59
BSR (Branch to SubRoutine)..........................................................................................61
BST (Bit STore)...............................................................................................................62
BTST (Bit TeST)............................................................................................................. 63
BXOR (Bit eXclusive OR)..............................................................................................65
CMP (CoMPare) (byte)...................................................................................................67
CMP (CoMPare) (word)..................................................................................................68
DAA (Decimal Adjust Add)............................................................................................ 69
DAS (Decimal Adjust Subtract)......................................................................................71
DEC (DECrement) .......................................................................................................... 73
DIVXU (DIVide eXtend as Unsigned) ........................................................................... 74
EEPMOV (MOVe data to EEPROM) .............................................................................76

INC (INCrement) ............................................................................................................ 78
JMP (JuMP).....................................................................................................................79
JSR (Jump to SubRoutine)..............................................................................................80
LDC (LoaD to Control register)......................................................................................81
MOV(MOVe data) (byte)................................................................................................ 82
MOV(MOVe data) (word)............................................................................................... 83
MOV(MOVe data) (byte)................................................................................................ 84
MOV(MOVe data) (word)............................................................................................... 85
MOV(MOVe data) (byte)................................................................................................ 86
MOV(MOVe data) (word)............................................................................................... 87
MOVFPE (MOVe data From Peripheral with E clock) ..................................................88
MOVTPE (MOVe data To Peripheral with E clock).......................................................89
MULXU (MULtiply eXtend as Unsigned) .....................................................................90
NEG (NEGate) ................................................................................................................ 91
NOP (No OPeration) .......................................................................................................92
NOT (NOT = logical complement)................................................................................. 93
OR (inclusive OR logical)...............................................................................................94
ORC (inclusive OR Control register)..............................................................................95
POP (POP data)............................................................................................................... 96
PUSH (PUSH data) .........................................................................................................97
ROTL (ROTate Left)....................................................................................................... 98
ROTR (ROTate Right) .................................................................................................... 99
ROTXL (ROTate with eXtend carry Left)......................................................................100
ROTXR (ROTate with eXtend carry Right)....................................................................101
RTE (ReTurn from Exception)........................................................................................102
RTS (ReTurn from Subroutine).......................................................................................103
SHAL (SHift Arithmetic Left) ........................................................................................104
SHAR (SHift Arithmetic Right)......................................................................................105
SHLL (SHift Logical Left)..............................................................................................106
SHLR (SHift Logical Right) ...........................................................................................107
SLEEP (SLEEP)..............................................................................................................108
STC (STore from Control register)..................................................................................109
SUB (SUBtract binary) (byte).........................................................................................110
SUB (SUBtract binary) (word)........................................................................................112
SUBS (SUBtract with Sign extension)............................................................................113
SUBX (SUBtract with eXtend carry)..............................................................................114
XOR (eXclusive OR logical) ..........................................................................................115

XORC (eXclusive OR Control register) .........................................................................116
Appendix A. Operation Code Map ..............................................................................117
Appendix B. Instruction Set List ..................................................................................118
Appendix C. Number of Execution States .................................................................124

Preface
The H8/300 CPU forms the common core of all chips in the H8/300 Series. Featuring a
Hitachi-original, high-speed, RISC-like architecture, it has eight 16-bit (or sixteen 8-bit)
general registers and a concise, optimized instruction set.
This manual gives detailed descriptions of the H8/300 instructions. The descriptions apply to
all chips in the H8/300 Series. Assembly-language programmers should also read the separate
H8/300 Series Cross Assembler User's Manual.
For hardware details, refer to the hardware manual of the specific chip.

Section 1. CPU
This document is a reference manual for programming the H8/300, a high-speed central
processing unit with a Hitachi-original RISC-like architecture that is employed as a CPU core
in a series of low-cost single-chip microcomputers intended for applications ranging from
smart cards to office and factory automation.
The H8/300 features a concise instruction set in which most frequently-used instructions are
two bytes long and execute in just two states (0.2µs with a 10MHz system clock). Its general
registers can be accessed as 16-bit word registers or 8-bit byte registers. The instruction set
includes both 8-bit and 16-bit instructions.
Section 1 of this manual summarizes the CPU architecture and instruction set. Section 2 gives
detailed descriptions of the instructions. Appendices give an operation code map, a complete
list of the instruction set, and tables for calculating instruction execution time. Programmers
should also refer to the User's Manual of the chip being programmed for information on bus
cycles, interrupt service, I/O ports, power-down modes, and on-chip facilities such as memory
and timers, and for a memory map.
1

1.1 General CPU Architecture
1.1.1 Features
Table 1-1 summarizes the CPU architecture. Figures 1-1 and 1-2 show how data are
stored in registers and memory.
Table 1-1. CPU Architecture
Notes:
1. Word data stored in memory must be stored at an even address.
2. Instructions must be stored at even addresses.
3. General register R7 is used as the stack pointer (SP).
1.1.2 Data Structure
The H8/300 CPU can process 1-bit data, 4-bit (packed BCD) data, 8-bit (byte) data, and 16-bit
(word) data.
• Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a
byte operand.
• All operational instructions except ADDS and SUBS can operate on byte data.
Item Description
Address space 64K bytes, H'0000 to H'FFFF
Data types Bit, 4-bit (packed BCD), byte, word (2 bytes)
General registers Sixteen 8-bit general registers (R0H, R0L, ..., R7H, R7L),
also accessible as eight 16-bit general registers (R0 to R7)
Control registers Program counter (PC)
Condition code register (CCR)
Addressing modes Rn Register direct
@Rn Register indirect
@(d:16, Rn) Register indirect with 16-bit displacement
@Rn+ Register indirect with post-increment
@–Rn Register indirect with pre-decrement
@aa:8, @aa:16 Absolute address (8 or 16 bits)
#xx:8, #xx:16 Immediate (8-, or 16-bit data)
@(d:8, PC) PC-relative (8-bit displacement)
@@aa:8 Memory indirect
Instruction length 2 or 4 bytes
2

• The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in
packed BCD form. Each 4-bit of the byte is treated as a decimal digit.
• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits ×8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions operate on word data.
Data Structure in General Registers: Data of all the sizes above can be stored in general
registers as shown in figure 1-1.
Figure 1-1. Register Data Structure
1-Bit data
1-Bit data
Byte data
Byte data
Word data
4-Bit BCD data
Data type
Don't-care
4
3
7
0
Data format
7
0
7
6
5
4
3
2
1
0
Don't-care
Don't-care
7
6
5
4
3
2
1
0
Don't-care
7
0
Don't-care
7
0
0
15
Don't-care
4
3
7
0
RnL
RnH
RnL
RnH
RnL
Rn
RnH
Register No.
7
0
4-Bit BCD data
M
S
B
M
S
B
M
S
B
L
S
B
L
S
B
L
S
B
Upperdigit
Lowerdigit
Upperdigit
Lowerdigit
RnH: Upper 8 bits of General Register
RnL: Lower 8 bits of General Register
MSB: Most Significant Bit
LSB: Least Significant Bit
3

Memory Data Structure: Figure 1-2 indicates the data structure in memory.
Word data stored in memory must always begin at an even address. In word access the least
significant bit of the address is regarded as “0.” If an odd address is specified, no address error
occurs but the access is performed at the preceding even address. This rule affects MOV.W
instructions and branching instructions, and implies that only even addresses should be stored
in the vector table.
Figure 1-2. Memory Data Formats
The stack is always accessed a word at a time. When the CCR is pushed on the stack, two
identical copies of the CCR are pushed to make a complete word. When they are returned, the
lower byte is ignored.
1.1.3 Address Space
The H8/300 CPU supports a 64K-byte address space. The memory map differs depending on
the particular chip in the H8/300 Series and its operating mode. See the Hardware Manual of
the chip for details.
L
S
B
Upper8bits
7
0
7
6
5
4
3
2
1
0
1-Bit data
Byte data
Word data
Byte data (CCR) on stack
Word data on stack
Data type
Data format
Address
Address n
Address n
Even address
Odd address
Even address
Odd address
Even address
Odd address
Lower8bits
M
S
B
M
S
B
L
S
B
M
S
B
L
S
B
M
S
B
L
S
B
M
S
B
L
S
B
Upper8bits
Lower8bits
CCR
CCR
*
CCR: Condition code register.
Note: Word data must begin at an even address.
*: Ignored when return.
4