Renesas H8/300 Series Owner's manual

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H8/300
Programming Manual

Contents
Section 1. CPU................................................................................................... 1
1.1 General CPU Architecture............................................................................................... 2
1.2 Registers.......................................................................................................................... 5
1.3 Instructions...................................................................................................................... 8
Section 2. Instruction Set................................................................................................. 32
ADD (ADD binary) (byte) ..............................................................................................37
ADD (ADD binary) (word).............................................................................................38
ADDS (ADD with Sign extension).................................................................................39
ADDX (ADD with eXtend carry) ...................................................................................40
AND (AND logical)........................................................................................................41
ANDC (AND Control register)....................................................................................... 42
BAND (Bit AND) ...........................................................................................................43
Bcc (Branch conditionally) .............................................................................................44
BCLR (Bit CLeaR)..........................................................................................................47
BIAND (Bit Invert AND)................................................................................................ 49
BILD (Bit Invert LoaD) ..................................................................................................50
BIOR (Bit Invert OR)......................................................................................................51
BIST (Bit Invert STore)................................................................................................... 52
BIXOR (Bit Invert eXclusive OR)..................................................................................53
BLD (Bit LoaD) ..............................................................................................................54
BNOT (Bit NOT) ............................................................................................................55
BOR (Bit inclusive OR)..................................................................................................57
BSET (Bit SET)............................................................................................................... 59
BSR (Branch to SubRoutine)..........................................................................................61
BST (Bit STore)...............................................................................................................62
BTST (Bit TeST)............................................................................................................. 63
BXOR (Bit eXclusive OR)..............................................................................................65
CMP (CoMPare) (byte)...................................................................................................67
CMP (CoMPare) (word)..................................................................................................68
DAA (Decimal Adjust Add)............................................................................................ 69
DAS (Decimal Adjust Subtract)......................................................................................71
DEC (DECrement) .......................................................................................................... 73
DIVXU (DIVide eXtend as Unsigned) ........................................................................... 74
EEPMOV (MOVe data to EEPROM) .............................................................................76

INC (INCrement) ............................................................................................................ 78
JMP (JuMP).....................................................................................................................79
JSR (Jump to SubRoutine)..............................................................................................80
LDC (LoaD to Control register)......................................................................................81
MOV(MOVe data) (byte)................................................................................................ 82
MOV(MOVe data) (word)............................................................................................... 83
MOV(MOVe data) (byte)................................................................................................ 84
MOV(MOVe data) (word)............................................................................................... 85
MOV(MOVe data) (byte)................................................................................................ 86
MOV(MOVe data) (word)............................................................................................... 87
MOVFPE (MOVe data From Peripheral with E clock) ..................................................88
MOVTPE (MOVe data To Peripheral with E clock).......................................................89
MULXU (MULtiply eXtend as Unsigned) .....................................................................90
NEG (NEGate) ................................................................................................................ 91
NOP (No OPeration) .......................................................................................................92
NOT (NOT = logical complement)................................................................................. 93
OR (inclusive OR logical)...............................................................................................94
ORC (inclusive OR Control register)..............................................................................95
POP (POP data)............................................................................................................... 96
PUSH (PUSH data) .........................................................................................................97
ROTL (ROTate Left)....................................................................................................... 98
ROTR (ROTate Right) .................................................................................................... 99
ROTXL (ROTate with eXtend carry Left)......................................................................100
ROTXR (ROTate with eXtend carry Right)....................................................................101
RTE (ReTurn from Exception)........................................................................................102
RTS (ReTurn from Subroutine).......................................................................................103
SHAL (SHift Arithmetic Left) ........................................................................................104
SHAR (SHift Arithmetic Right)......................................................................................105
SHLL (SHift Logical Left)..............................................................................................106
SHLR (SHift Logical Right) ...........................................................................................107
SLEEP (SLEEP)..............................................................................................................108
STC (STore from Control register)..................................................................................109
SUB (SUBtract binary) (byte).........................................................................................110
SUB (SUBtract binary) (word)........................................................................................112
SUBS (SUBtract with Sign extension)............................................................................113
SUBX (SUBtract with eXtend carry)..............................................................................114
XOR (eXclusive OR logical) ..........................................................................................115

XORC (eXclusive OR Control register) .........................................................................116
Appendix A. Operation Code Map ..............................................................................117
Appendix B. Instruction Set List ..................................................................................118
Appendix C. Number of Execution States .................................................................124

Preface
The H8/300 CPU forms the common core of all chips in the H8/300 Series. Featuring a
Hitachi-original, high-speed, RISC-like architecture, it has eight 16-bit (or sixteen 8-bit)
general registers and a concise, optimized instruction set.
This manual gives detailed descriptions of the H8/300 instructions. The descriptions apply to
all chips in the H8/300 Series. Assembly-language programmers should also read the separate
H8/300 Series Cross Assembler User's Manual.
For hardware details, refer to the hardware manual of the specific chip.

Section 1. CPU
This document is a reference manual for programming the H8/300, a high-speed central
processing unit with a Hitachi-original RISC-like architecture that is employed as a CPU core
in a series of low-cost single-chip microcomputers intended for applications ranging from
smart cards to office and factory automation.
The H8/300 features a concise instruction set in which most frequently-used instructions are
two bytes long and execute in just two states (0.2µs with a 10MHz system clock). Its general
registers can be accessed as 16-bit word registers or 8-bit byte registers. The instruction set
includes both 8-bit and 16-bit instructions.
Section 1 of this manual summarizes the CPU architecture and instruction set. Section 2 gives
detailed descriptions of the instructions. Appendices give an operation code map, a complete
list of the instruction set, and tables for calculating instruction execution time. Programmers
should also refer to the User's Manual of the chip being programmed for information on bus
cycles, interrupt service, I/O ports, power-down modes, and on-chip facilities such as memory
and timers, and for a memory map.
1

1.1 General CPU Architecture
1.1.1 Features
Table 1-1 summarizes the CPU architecture. Figures 1-1 and 1-2 show how data are
stored in registers and memory.
Table 1-1. CPU Architecture
Notes:
1. Word data stored in memory must be stored at an even address.
2. Instructions must be stored at even addresses.
3. General register R7 is used as the stack pointer (SP).
1.1.2 Data Structure
The H8/300 CPU can process 1-bit data, 4-bit (packed BCD) data, 8-bit (byte) data, and 16-bit
(word) data.
• Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a
byte operand.
• All operational instructions except ADDS and SUBS can operate on byte data.
Item Description
Address space 64K bytes, H'0000 to H'FFFF
Data types Bit, 4-bit (packed BCD), byte, word (2 bytes)
General registers Sixteen 8-bit general registers (R0H, R0L, ..., R7H, R7L),
also accessible as eight 16-bit general registers (R0 to R7)
Control registers Program counter (PC)
Condition code register (CCR)
Addressing modes Rn Register direct
@Rn Register indirect
@(d:16, Rn) Register indirect with 16-bit displacement
@Rn+ Register indirect with post-increment
@–Rn Register indirect with pre-decrement
@aa:8, @aa:16 Absolute address (8 or 16 bits)
#xx:8, #xx:16 Immediate (8-, or 16-bit data)
@(d:8, PC) PC-relative (8-bit displacement)
@@aa:8 Memory indirect
Instruction length 2 or 4 bytes
2

• The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in
packed BCD form. Each 4-bit of the byte is treated as a decimal digit.
• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits ×8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions operate on word data.
Data Structure in General Registers: Data of all the sizes above can be stored in general
registers as shown in figure 1-1.
Figure 1-1. Register Data Structure
1-Bit data
1-Bit data
Byte data
Byte data
Word data
4-Bit BCD data
Data type
Don't-care
4
3
7
0
Data format
7
0
7
6
5
4
3
2
1
0
Don't-care
Don't-care
7
6
5
4
3
2
1
0
Don't-care
7
0
Don't-care
7
0
0
15
Don't-care
4
3
7
0
RnL
RnH
RnL
RnH
RnL
Rn
RnH
Register No.
7
0
4-Bit BCD data
M
S
B
M
S
B
M
S
B
L
S
B
L
S
B
L
S
B
Upperdigit
Lowerdigit
Upperdigit
Lowerdigit
RnH: Upper 8 bits of General Register
RnL: Lower 8 bits of General Register
MSB: Most Significant Bit
LSB: Least Significant Bit
3

Memory Data Structure: Figure 1-2 indicates the data structure in memory.
Word data stored in memory must always begin at an even address. In word access the least
significant bit of the address is regarded as “0.” If an odd address is specified, no address error
occurs but the access is performed at the preceding even address. This rule affects MOV.W
instructions and branching instructions, and implies that only even addresses should be stored
in the vector table.
Figure 1-2. Memory Data Formats
The stack is always accessed a word at a time. When the CCR is pushed on the stack, two
identical copies of the CCR are pushed to make a complete word. When they are returned, the
lower byte is ignored.
1.1.3 Address Space
The H8/300 CPU supports a 64K-byte address space. The memory map differs depending on
the particular chip in the H8/300 Series and its operating mode. See the Hardware Manual of
the chip for details.
L
S
B
Upper8bits
7
0
7
6
5
4
3
2
1
0
1-Bit data
Byte data
Word data
Byte data (CCR) on stack
Word data on stack
Data type
Data format
Address
Address n
Address n
Even address
Odd address
Even address
Odd address
Even address
Odd address
Lower8bits
M
S
B
M
S
B
L
S
B
M
S
B
L
S
B
M
S
B
L
S
B
M
S
B
L
S
B
Upper8bits
Lower8bits
CCR
CCR
*
CCR: Condition code register.
Note: Word data must begin at an even address.
*: Ignored when return.
4

1.2 Registers
Figure 1-3 shows the register structure of the H8/300 CPU. There are sixteen 8-bit general
registers (R0H, R0L, ..., R7H, R7L), which can also be accessed as eight 16-bit registers (R0
to R7). There are two control registers: the 16-bit program counter (PC) and the 8-bit
condition code register (CCR).
Figure 1-3. CPU Registers
0
7
R0H
R0L
R1H
R1L
R2H
R2L
R3L
R3H
R4L
R4H
R5H
R5L
R6H
R6L
R7H
R7L
(SP)
0
15
PC
0
2
3
5
C
V
Z
H
0
7
CCR
N
I
1
7
SP: Stack Pointer
Program Counter
Condition Code Register
Carryflag
Overflow flag
Zero flag
Half-carryflag
Interrupt mask bit
User bit
Negative flag
U
U
6
4
5

1.2.1 General Registers
All the general registers can be used as both data registers and address registers. When used as
address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used
as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high (R0H to R7H)
and low (R0L to R7L) bytes can be accessed separately as 8-bit registers. The register length
is determined by the instruction.
R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and
subroutine calls. In assembly language, the letters SP can be coded as a synonym for R7. As
indicated in figure 1-4, R7 (SP) points to the top of the stack.
Figure 1-4. Stack Pointer
1.2.2 Control Registers
The CPU has a 16-bit program counter (PC) and an 8-bit condition code register (CCR).
(1) Program Counter (PC): This 16-bit register indicates the address of the next instruction
the CPU will execute. Instructions are fetched by 16-bit (word) access, so the least significant
bit of the PC is ignored (always regarded as 0).
(2) Condition Code Register (CCR): This 8-bit register indicates the internal status of the
CPU with an interrupt mask (I) bit and five flag bits: half-carry (H), negative (N), zero (Z),
overflow (V), and carry (C) flags. The two unused bits are available to the user. The bit
configuration of the condition code register is shown below.
Unused area
Stackarea
SP (R7)
6

* Undetermined
Bit 7—Interrupt Mask Bit (I): When this bit is set to "1," all interrupts except NMI are
masked. This bit is set to "1" automatically by a reset and at the start of interrupt handling.
Bits 6 and 4—User Bits (U): These bits can be written and read by software for its own
purposes.
Bit 5—Half-Carry (H): This bit is used by add, subtract, and compare instructions to indicate
a borrow or carry out of bit 3 or bit 11. It is referenced by the decimal adjust instructions.
Bit 3—Negative (N): This bit indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2—Zero (Z): This bit is set to "1" to indicate a zero result and cleared to "0" to indicate a
nonzero result.
Bit 1—Overflow (V): This bit is set to "1" when an arithmetic overflow occurs, and cleared
to "0" at other times.
Bit 0—Carry (C): This bit is used by:
• Add, subtract, and compare instructions, to indicate a carry or borrow at the most
significant bit
• Shift and rotate instructions, to store the value shifted out of the most or least significant
bit
• Bit manipulation instructions, as a bit accumulator
System control instructions can load and store the CCR, and perform logic operations to set,
clear, or toggle selected bits.
1.2.3 Initial Register Values
When the CPU is reset, the program counter (PC) is loaded from the vector table and the
interrupt mask bit (I) in the CCR is set to “1.” The other CCR bits and the general registers are
not initialized.
Bit 7 6 5 4 3 2 1 0
I U H U N Z V C
Initial value 1 * * * * * * *
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
7

In particular, the stack pointer (R7) is not initialized. To prevent program crashes the stack
pointer should be initialized by software, by the first instruction executed after a reset.
1.3 Instructions
Features:
• The H8/300 has a concise set of 57 RISC-like instructions.
• Arithmetic and logic are performed as register-to-register operations, or with immediate
data.
• All instructions are 2 or 4 bytes long.
• Fast multiply/divide instructions; extensive bit manipulation instructions.
• Eight addressing modes.
1.3.1 Types of Instructions
Table 1-2 classifies the H8/300 instructions by type. Tables 1-3 to 1-10 briefly describe their
functions. Section 2, Instruction Set, gives detailed descriptions.
Table 1-2. Instruction Classification
* POP Rn is equivalent to MOV.W @SP+, Rn.
PUSH Rn is equivalent to MOV.W Rn, @-SP.
** Bcc is a conditional branch instruction in which cc represents a condition .
Function Instructions Types
Data transfer
MOV, MOVFPE, MOVTPE, POP*, PUSH* 3
Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, 14
DAA, DAS, MULXU, DIVXU, CMP, NEG
Logic operations AND, OR, XOR, NOT 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, 8
ROTXR
Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR 14
BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST
Branch Bcc**, JMP, BSR, JSR, RTS 5
System control RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 8
Block data transfer EEPMOV 1
Total 57
8

1.3.2 Instruction Functions
Tables 1-3 to 1-10 give brief descriptions of the instructions in each functional group.
The following notation is used.
:3, :8, :16 3-bit, 8-bit, or 16-bit length.
Notation
Rd General register (destination)
Rs General register (source)
Rn General register
(EAd) Destination operand
(EAs) Source operand
CCR Condition code register
N N (negative) bit of CCR
Z Z (zero) bit of CCR
V V (overflow) bit of CCR
C C (carry) bit of CCR
PC Program counter
SP Stack pointer (R7)
#Imm Immediate data
#xx:3 3-Bit immediate data
#xx:8 8-Bit immediate data
#xx:16 16-Bit immediate data
op Operation field
disp Displacement
+ Addition
– Subtraction
×Multiplication
÷ Division
∧AND logical
∨OR logical
⊕Exclusive OR logical
→Move
¬ Not
9

Table 1-3. Data Transfer Instructions
Instruction Size* Function
MOV B/W (EAs) →Rd, Rs →(EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @–Rn, and
@Rn+ addressing modes are available for byte or word data. The
@aa:8 addressing mode is available for byte data only.
The @–R7 and @R7+ modes require word operands. Do not
specify byte size for these two modes.
MOVFPE B (EAs) →Rd
Transfers data from memory to a general register in
synchronization with the E clock.
MOVTPE B Rs →(EAd)
Transfers data from a general register to memory in
synchronization with the E clock.
POP W @SP+ →Rn
Pops a 16-bit general register from the stack.
Equivalent to MOV.W @SP+, Rn.
PUSH W Rn →@–SP
Pushes a 16-bit general register onto the stack.
Equivalent to MOV.W Rn, @-SP.
* Size: Operand size
B: Byte
W: Word
10

Table 1-4. Arithmetic Instructions
Instruction Size* Function
ADD B/W Rd ± Rs →Rd, Rd + #Imm →Rd
SUB Performs addition or subtraction on data in two general registers,
or addition on immediate data and data in a general register.
Immediate data cannot be subtracted from data in a general register.
Word data can be added or subtracted only when both words are in
general registers.
ADDX B Rd ± Rs ± C →Rd, Rd ± #Imm ± C →Rd
SUBX Performs addition or subtraction with carry or borrow on byte data
in two general registers, or addition or subtraction on immediate data
and data in a general register.
INC B Rd ± 1 →Rd
DEC Increments or decrements a general register.
ADDS W Rd ± 1 →Rd, Rd ± 2 →Rd
SUBS Adds or subtracts immediate data to or from data in a general
register. The immediate data must be 1 or 2.
DAA B Rd decimal adjust →Rd
DAS Decimal-adjusts (adjusts to packed BCD) an addition or
subtraction result in a general register by referring to the CCR.
MULXU B Rd × Rs →Rd
Performs 8-bit ×8-bit unsigned multiplication on data in two
general registers, providing a 16-bit result.
DIVXU B Rd ÷ Rs →Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder.
CMP B/W Rd – Rs, Rd – #Imm
Compares data in a general register with data in another general
register or with immediate data. Word data can be compared only
between two general registers.
NEG B 0 – Rd →Rd
Obtains the two’s complement (arithmetic complement) of data in
a general register.
* Size: Operand size
B: Byte
W: Word
11

Table 1-5. Logic Operation Instructions
Instruction Size* Function
AND B Rd ∧Rs →Rd, Rd ∧#Imm →Rd
Performs a logical AND operation on a general register and
another general register or immediate data.
OR B Rd ∨Rs →Rd, Rd ∨#Imm →Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR B Rd ⊕Rs →Rd, Rd ⊕#Imm →Rd
Performs a logical exclusive OR operation on a general register
and another general register or immediate data.
NOT B ¬ Rd →Rd
Obtains the one’s complement (logical complement) of general
register contents.
* Size: Operand size
B: Byte
Table 1-6. Shift Instructions
Instruction Size* Function
SHAL B Rd shift →Rd
SHAR Performs an arithmetic shift operation on general register contents.
SHLL B Rd shift →Rd
SHLR Performs a logical shift operation on general register contents.
ROTL B Rd rotate →Rd
ROTR Rotates general register contents.
ROTXL B Rd rotate through carry → Rd
ROTXR Rotates general register contents through the C (carry) bit.
* Size: Operand size
B: Byte
12

Table 1-7. Bit-Manipulation Instructions
Instruction Size* Function
BSET B 1 →(<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory to “1.” The bit
is specified by a bit number, given in 3-bit immediate data or the lower
three bits of a general register.
BCLR B 0 →(<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory to “0.” The
bit is specified by a bit number, given in 3-bit immediate data or the
lower three bits of a general register.
BNOT B¬(<bit-No.> of <EAd>) →(<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory. The bit is
specified by a bit number, given in 3-bit immediate data or the lower
three bits of a general register.
BTST B ¬ (<bit-No.> of <EAd>) →Z
Tests a specified bit in a general register or memory and sets or
clears the Z flag accordingly. The bit is specified by a bit number,
given in 3-bit immediate data or the lower three bits of a general
register.
BAND B C ∧(<bit-No.> of <EAd>) →C
ANDs the C flag with a specified bit in a general register or
memory.
BIAND B C ∧[¬ (<bit-No.> of <EAd>)] →C
ANDs the C flag with the inverse of a specified bit in a general
register or memory.
The bit number is specified by 3-bit immediate data.
BOR B C ∨(<bit-No.> of <EAd>) →C
ORs the C flag with a specified bit in a general register or memory.
BIOR B C ∨[¬ (<bit-No.> of <EAd>)] →C
ORs the C flag with the inverse of a specified bit in a general
register or memory.
The bit number is specified by 3-bit immediate data.
13

Table 1-7. Bit-Manipulation Instructions (Cont.)
Instruction Size* Function
BXOR B C ⊕(<bit-No.> of <EAd>) →C
Exclusive-ORs the C flag with a specified bit in a general register
or memory.
BIXOR B C ⊕[¬ (<bit-No.> of <EAd>)] →C
Exclusive-ORs the C flag with the inverse of a specified bit in a
general register or memory.
The bit number is specified by 3-bit immediate data.
BLD B (<bit-No.> of <EAd>) →C
Copies a specified bit in a general register or memory to the C flag.
BILD B ¬ (<bit-No.> of <EAd>) →C
Copies the inverse of a specified bit in a general register or
memory to the C flag.
The bit number is specified by 3-bit immediate data.
BST B C →(<bit-No.> of <EAd>)
Copies the C flag to a specified bit in a general register or memory.
BIST B ¬ C →(<bit-No.> of <EAd>)
Copies the inverse of the C flag to a specified bit in a general
register or memory.
The bit number is specified by 3-bit immediate data.
* Size: Operand size
B: Byte
14