Renesas M16C/29 User manual

RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY / M16C/Tiny SERIES
M16C/29 Group
16
Rev. 1.00
Revision date: Nov. 1, 2004
Hardware Manual
www.renesas.com
Before using this material, please visit our website to confirm that this is the most
current document available.
REJ09B0101-0100Z

Keep safety first in your circuit designs!
Notes regarding these materials
•Renesas Technology Corporation puts the maximum effort into making semiconductor prod-
ucts better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with ap-
propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
• These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corporation product best suited to the customer's application; they do
not convey any license under any intellectual property rights, or any other rights, belonging
to Renesas Technology Corporation or a third party.
• Renesas Technology Corporation assumes no responsibility for any damage, or infringe-
ment of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
• All information contained in these materials, including product data, diagrams, charts, pro-
grams and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corporation without notice
due to product improvements or other reasons. It is therefore recommended that custom-
ers contact Renesas Technology Corporation or an authorized Renesas Technology Cor-
poration product distributor for the latest product information before purchasing a product
listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or
other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by
various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
• When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa-
tion as a total system before making a final decision on the applicability of the information
and products. Renesas Technology Corporation assumes no responsibility for any dam-
age, liability or other loss resulting from the information contained herein.
• Renesas Technology Corporation semiconductors are not designed or manufactured for
use in a device or system that is used under circumstances in which human life is poten-
tially at stake. Please contact Renesas Technology Corporation or an authorized Renesas
Technology Corporation product distributor when considering the use of a product con-
tained herein for any specific purposes, such as apparatus or systems for transportation,
vehicular, medical, aerospace, nuclear, or undersea repeater use.
• The prior written approval of Renesas Technology Corporation is necessary to reprint or
reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions,
they must be exported under a license from the Japanese government and cannot be im-
ported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/
or the country of destination is prohibited.
• Please contact Renesas Technology Corporation for further details on these materials or t
he products contained therein.

How to Use This Manual
This hardware manual provides detailed information on features in the M16C/29 Group
microcomputer.
Users are expected to have basic knowledge of electric circuits, logical circuits and micro-
computer.
*2
RW: Read and write
RO: Read only
WO: Write only
–: Nothing is assigned
*1
Blank:Set to "0" or "1" according to your intended use
0: Set to "0"
1: Set to "1"
X: Nothing is assigned
*3
Terms to use here are explained as follows.
•Nothing is assigned
Nothing is assigned to the bit concerned. When write, set to "0" for new function
in future plan.
•Reserved bit
Reserved bit. Set the specified value.
•Avoid this setting
The operation at having selected is not guaranteed.
•Function varies depending on each operation mode
Bit function varies depending on peripheral function mode.
Refer to register diagrams in each mode.
*3
XXX register
Symbol Address After reset
XXX XXX 00
16
Bit nameBit symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
XXX bit 1 0: XXX
0 1: XXX
1 0: Avoid this setting
1 1: XXX
b1 b0
XXX1
XXX0
XXX4
Reserved bit
XXX5
XXX7
XXX6
Function
Nothing is assigned.
When write, should set to "0". When read, its content is indeterminate.
XXX bit
Function varies depending on each
operation mode
Should set to "0"
0
(b3)
(b2)
RW
RW
RW
RW
WO
RW
RO
XXX bit
0: XXX
1: XXX
*1
*2
Each register diagram contains bit functions with the following symbols and descriptions.

Contents
Hardware overview
Hardware overview and electrical characteristics
Hardware specifications (pin assignments,
memory maps, specifications of peripheral func-
tions, electrical characteristics, timing charts)
Detailed description about instructions and mi-
crocomputer performance by each instruction
•Application examples of peripheral functions
•Sample programs
•Introductory description about basic functions in
M16C family
•Programming method with the assembly and C
languages
Document
Short Sheet
M16C Family Documents
Data Sheet
Hardware Manual
Software Manual
Application Note

A-1
Table of Contents
Quick Reference to Pages Classified by Address ................................................................. B-1
1. Overview ......................................................................................................... 1
1.1 Applications ...................................................................................................................... 1
1.2 Performance Outline.........................................................................................................2
1.3 Block Diagram .................................................................................................................. 4
1.4 Product List....................................................................................................................... 6
1.5 Pin Configuration ............................................................................................................ 10
1.6 Pin Description ............................................................................................................... 12
2. Central Processing Unit (CPU) ......................................................................14
2.1 Data Registers (R0, R1, R2 and R3) .............................................................................. 14
2.2 Address Registers (A0 and A1) ...................................................................................... 14
2.3 Frame Base Register (FB).............................................................................................. 15
2.4 Interrupt Table Register (INTB)....................................................................................... 15
2.5 Program Counter (PC).................................................................................................... 15
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .......................................... 15
2.7 Static Base Register (SB) ............................................................................................... 15
2.8 Flag Register (FLG) ........................................................................................................ 15
2.8.1 Carry Flag (C Flag) .................................................................................................. 15
2.8.2 Debug Flag (D Flag)................................................................................................. 15
2.8.3 Zero Flag (Z Flag) ................................................................................................... 15
2.8.4 Sign Flag (S Flag) .................................................................................................... 15
2.8.5 Register Bank Select Flag (B Flag) .......................................................................... 15
2.8.6 Overflow Flag (O Flag) ............................................................................................. 15
2.8.7 Interrupt Enable Flag (I Flag) ................................................................................... 15
2.8.8 Stack Pointer Select Flag (U Flag) ........................................................................... 15
2.8.9 Processor Interrupt Priority Level (IPL) .................................................................... 15
2.8.10 Reserved Area ....................................................................................................... 15
3. Memory ..........................................................................................................16
4. Special Function Register (SFR) Map............................................................17
5. Reset ..............................................................................................................28
5.1 Hardware Reset..............................................................................................................28
5.1.1 Hardware Reset 1 .................................................................................................... 28
5.1.2 Hardware Reset 2 .................................................................................................... 28

A-2
5.2 Software Reset ............................................................................................................... 29
5.3 Watchdog Timer Reset ................................................................................................... 29
5.4 Oscillation Stop Detection Reset .................................................................................... 29
5.5 Voltage Detection Circuit .............................................................................................. 31
5.5.1 Voltage Down Detection Interrupt ........................................................................... 34
5.5.2 Limitations on Exiting Stop Mode ............................................................................ 36
5.5.3 Limitations on Exiting Wait Mode ............................................................................ 36
6. Processor Mode .............................................................................................37
7. Clock Generation Circuit ................................................................................38
7.1 Main Clock ...................................................................................................................... 45
7.2 Sub Clock ....................................................................................................................... 46
7.3 On-chip Oscillator Clock ................................................................................................. 47
7.4 PLL Clock ....................................................................................................................... 47
7.5 CPU Clock and Peripheral Function Clock ..................................................................... 49
7.5.1 CPU Clock................................................................................................................ 49
7.5.2 Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32, fCAN0).... 49
7.5.3 ClockOutput Function............................................................................................... 49
7.6 Power Control ................................................................................................................. 50
7.6.1 Normal Operation Mode ........................................................................................... 50
7.6.1.1 High-speed Mode ............................................................................................. 50
7.6.1.2 PLL Operation Mode ......................................................................................... 50
7.6.1.3 Medium-speed Mode ........................................................................................ 50
7.6.1.4 Low-speed Mode .............................................................................................. 50
7.6.1.5 Low Power Dissipation Mode ........................................................................... 50
7.6.1.6 On-chip Oscillator Mode .................................................................................... 51
7.6.1.7 On-chip Oscillator Low Power Dissipation Mode ............................................... 51
7.6.2 Wait Mode ................................................................................................................ 51
7.6.2.1 Peripheral Function Clock Stop Function ......................................................... 51
7.6.2.2 Entering Wait Mode .......................................................................................... 51
7.6.2.3 Pin Status During Wait Mode ............................................................................ 52
7.6.2.4 Exiting Wait Mode ............................................................................................. 52
7.6.3 Stop Mode ............................................................................................................... 53
7.6.3.1 Entering Stop Mode ........................................................................................... 53
7.6.3.2 Pin Status during Stop Mode ............................................................................. 53
7.6.3.3 Exiting Stop Mode.............................................................................................. 53
7.7 System Clock Protective Function .................................................................................. 57
7.8 Oscillation Stop and Re-oscillation Detect Function ....................................................... 57

A-3
7.8.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset)........................... 58
7.8.2 Operation When CM27 bit = 1
(Oscillation Stop and Re-oscillation Detect Interrupt) ....... 58
7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function ............................. 59
8. Protection .......................................................................................................60
9. Interrupts ........................................................................................................61
9.1 Type of Interrupts ............................................................................................................ 61
9.1.1 Software Interrupts ................................................................................................... 62
9.1.1.1 Undefined Instruction Interrupt .......................................................................... 62
9.1.1.2 Overflow Interrupt .............................................................................................. 62
9.1.1.3 BRK Interrupt ..................................................................................................... 62
9.1.1.4 INT Instruction Interrupt ..................................................................................... 62
9.1.2 Hardware Interrupts ................................................................................................. 63
9.1.2.1 Special Interrupts ............................................................................................... 63
_______
9.1.2.1.1 NMI Interrupt ............................................................................................... 63
________
9.1.2.1.2 DBC Interrupt .............................................................................................. 63
9.1.2.1.3 Watchdog Timer Interrupt ............................................................................ 63
9.1.2.1.4 Oscillation Stop and Re-oscillation Detection Interrupt ............................... 63
9.1.2.1.5 Voltage Down Detection Interrupt................................................................ 63
9.1.2.1.6 Single-step Interrupt .................................................................................... 63
9.1.2.1.7 Address Match Interrupt .............................................................................. 63
9.1.2.2 Peripheral Function Interrupts ........................................................................... 63
9.2 Interrupts and Interrupt Vector ........................................................................................ 64
9.2.1 Fixed Vector Tables .................................................................................................. 64
9.2.2 Relocatable Vector Tables........................................................................................ 65
9.3 Interrupt Control.............................................................................................................. 66
9.3.1 I Flag ........................................................................................................................ 69
9.3.2 IR Bit ........................................................................................................................ 69
9.3.3 ILVL2 to ILVL0 Bits and IPL...................................................................................... 69
9.4 Interrupt Sequence ......................................................................................................... 70
9.4.1 Interrupt Response Time .......................................................................................... 71
9.4.2 Variation of IPL when Interrupt Request is Accepted ............................................... 71
9.4.3 Saving Registers ...................................................................................................... 72
9.4.4 Returning from an Interrupt Routine......................................................................... 74
9.5 Interrupt Priority .............................................................................................................. 74
9.5.1 Interrupt Priority Resolution Circuit .......................................................................... 74
______
9.6 INT Interrupt ................................................................................................................... 76
______
9.7 NMI Interrupt................................................................................................................... 76

A-4
9.8 Key Input Interrupt .......................................................................................................... 77
9.9 CAN0 Wake-up Interrupt ................................................................................................ 77
9.10 Address Match Interrupt ............................................................................................... 78
10. Watchdog Timer ...........................................................................................80
10.1 Count source protective mode...................................................................................... 80
10.2 Cold start / Warm start .................................................................................................. 82
11. DMAC ...........................................................................................................83
11.1 Transfer Cycles ............................................................................................................ 88
11.1.1 Effect of Source and Destination Addresses ......................................................... 88
11.1.2 Effect of Software Wait ..........................................................................................88
11.2. DMA Transfer Cycles ...................................................................................................90
11.3 DMA Enable .................................................................................................................. 91
11.4 DMA Request................................................................................................................91
11.5 Channel Priority and DMA Transfer Timing .................................................................. 92
12. Timers ..........................................................................................................93
12.1 Timer A ........................................................................................................................ 95
12.1.1. Timer Mode ........................................................................................................... 98
12.1.2. Event Counter Mode ............................................................................................. 99
12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing....................... 103
12.1.3. One-shot Timer Mode ......................................................................................... 104
12.1.4. Pulse Width Modulation (PWM) Mode ................................................................ 106
12.2 Timer B ...................................................................................................................... 109
12.2.1 Timer Mode ......................................................................................................... 111
12.2.2 Event Counter Mode ............................................................................................ 112
12.2.3 Pulse Period and Pulse Width Measurement Mode............................................ 113
12.2.4 A/D Trigger Mode ................................................................................................ 115
12.3 Three-phase Motor Control Timer Function................................................................ 117
12.3.1 Position-data-retain Function ............................................................................... 128
12.3.1.1 Operation of the Position-data-retain Function .............................................. 128
12.3.1.2 Position-data-retain Function Control Register .............................................. 129
12.3.1.2.1 W-phase Position Data Retain Bit (PDRW) ............................................. 129
12.3.1.2.2 V-phase Position Data Retain Bit (PDRV) ............................................... 129
12.3.1.2.3 U-phase Position Data Retain Bit (PDRU) .............................................. 129
12.3.1.2.4 Retain-trigger Polarity Select Bit (PDRT) ................................................ 129
12.3.2 Three-phase/Port Output Switch Function ........................................................... 130
13. Timer S (Input Capture/Output Compare) ..................................................132

A-5
13.1 Base Timer ................................................................................................................. 144
13.1.1 Base Timer Reset Register .................................................................................. 148
13.2 Interrupt Operation ..................................................................................................... 149
13.3 DMA Support .............................................................................................................. 149
13.4 Time Measurement Function ...................................................................................... 150
13.5 Waveform Generation Function .................................................................................. 154
13.5.1 Single-Phase Waveform Output Mode ................................................................. 155
13.5.2 Phase-Delayed Waveform Output Mode.............................................................. 157
13.5.3 Set/Reset Waveform Output (SR Waveform Output) Mode ................................. 159
13.6 I/O Port Function Select ............................................................................................. 161
13.6.1 INPC17 Alternate Input Pin Selection .................................................................. 162
________
13.6.2 Digital Debounce Function for Pin P17/INT5/INPC17 .......................................... 162
14. Serial I/O ....................................................................................................163
14.1. UARTi (i=0 to 2) ......................................................................................................... 163
14.1.1. Clock Synchronous serial I/O Mode .................................................................... 173
14.1.1.1 CLK Polarity Select Function ......................................................................... 177
14.1.1.2 LSB First/MSB First Select Function ............................................................ 177
14.1.1.3 Continuous receive mode .............................................................................. 178
14.1.1.4 Serial data logic switch function (UART2) ..................................................... 178
14.1.1.5 Transfer clock output from multiple pins function (UART1) ........................... 178
_______ _______
14.1.1.6 CTS/RTS separate function (UART0)............................................................ 179
14.1.2. Clock Asynchronous Serial I/O (UART) Mode .................................................... 180
14.1.2.1. LSB First/MSB First Select Function ............................................................ 184
14.1.2.2. Serial Data Logic Switching Function (UART2) ............................................ 185
14.1.2.3. TxD and RxD I/O Polarity Inverse Function (UART2) ................................... 185
_______ _______
14.1.2.4. CTS/RTS Separate Function (UART0) ......................................................... 186
14.1.3 Special Mode 1 (I2C bus mode)(UART2) ............................................................. 187
14.1.3.1 Detection of Start and Stop Condition ........................................................... 193
14.1.3.2 Output of Start and Stop Condition ................................................................ 193
14.1.3.3 Arbitration....................................................................................................... 194
14.1.3.4 Transfer Clock................................................................................................ 195
14.1.3.5 SDA Output .................................................................................................... 195
14.1.3.6 SDA Input....................................................................................................... 195
14.1.3.7 ACK and NACK............................................................................................. 196
14.1.3.8 Initialization of Transmission/Reception........................................................ 196
14.1.4 Special Mode 2 (UART2) ..................................................................................... 197
14.1.4.1 Clock Phase Setting Function....................................................................... 200
14.1.4.1.1 Master (Internal Clock) ............................................................................ 200

A-6
14.1.4.1.2 Slave (External Clock) ............................................................................. 200
14.1.5 Special Mode 3 (IEBus mode)(UART2) .............................................................. 202
14.1.6 Special Mode 4 (SIM Mode) (UART2)................................................................. 204
14.1.6.1 Parity Error Signal Output .............................................................................. 207
14.1.6.2 Format .......................................................................................................... 208
14.2 SI/O3 and SI/O4 ........................................................................................................ 209
14.2.1 SI/Oi Operation Timing ........................................................................................ 212
14.2.2 CLK Polarity Selection ........................................................................................ 212
14.2.3 Functions for Setting an SOUTi Initial Value ....................................................... 213
15. A/D Converter.............................................................................................214
15.1 Operation Modes ........................................................................................................ 220
15.1.1 One-Shot Mode .................................................................................................... 220
15.1.2 Repeat mode........................................................................................................ 222
15.1.3 Single Sweep Mode ............................................................................................ 224
15.1.4 Repeat Sweep Mode 0......................................................................................... 226
15.1.5 Repeat Sweep Mode 1......................................................................................... 228
15.1.6 Simultaneous Sample Sweep Mode .................................................................... 230
15.1.7 Delayed Trigger Mode 0 ....................................................................................... 233
15.1.8 Delayed Trigger Mode 1 ....................................................................................... 239
15.2 Resolution Select Function ......................................................................................... 245
15.3 Sample and Hold ........................................................................................................ 245
15.4 Current Consumption Reducing Function .................................................................. 245
15.5 Analog Input Pin and External Sensor Equivalent Circuit Example ............................ 245
15.6 Precautions of Using A/D Converter ........................................................................... 246
16. Multi-master I2C bus Interface ....................................................................247
16.1 I2C0 Data Shift Register (S00 register) ....................................................................... 256
16.2 I2C0 Address Register (S0D0 register) ...................................................................... 256
16.3 I2C0 Clock Control Register (S20 register) ................................................................ 257
16.3.1 Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) ....................................... 257
16.3.2 Bit 5: SCL mode specification bit (FAST MODE) ............................................... 257
16.3.3 Bit 6: ACK bit (ACK BIT)...................................................................................... 257
16.3.4 Bit 7: ACK clock bit (ACK) ................................................................................... 257
16.4 I2C0 Control Register 0 (S1D0 register) .................................................................... 259
16.4.1 Bits 0 to 2: Bit counter (BC0–BC2)...................................................................... 259
16.4.2 Bit 3: I2C interface enable bit (ES0) .................................................................... 259
16.4.3 Bit 4: Data format select bit (ALS) ....................................................................... 259
16.4.4 Bit 6: I2C bus interface reset bit (IHR) ................................................................. 259

A-7
16.4.5 Bit 7: I2C bus interface pin input level select bit (TISS) ....................................... 260
16.5 I2C0 Status Register (S10 register) ........................................................................... 261
16.5.1 Bit 0: Last receive bit (LRB) ................................................................................ 261
16.5.2 Bit 1: General call detection flag (ADR0) ............................................................ 261
16.5.3 Bit 2: Slave address comparison flag (AAS) ....................................................... 261
16.5.4 Bit 3: Arbitration lost detection flag (AL)(Note 1) ................................................. 261
16.5.5 Bit 4: I2C bus interface interrupt request bit (PIN) ............................................... 262
16.5.6 Bit 5: Bus busy flag (BB) ..................................................................................... 262
16.5.7 Bit 6: Communication mode select bit (transfer direction select bit: TRX) .......... 263
16.5.8 Bit 7: Communication mode select bit (master/slave select bit: MST) ............... 263
16.6 I2C0 control register 1 (S3D0 register)...................................................................... 264
16.6.1 Bit 0 : Interrupt enable bit by STOP condition (SIM ) .......................................... 264
16.6.2 Bit 1: Interrupt enable bit at the completion of data receive (WIT) ...................... 264
16.6.3 Bits 2,3 : Port function select bits PED, PEC ...................................................... 265
16.6.4 Bits 4,5 : SDA/SCL logic output value monitor bits SDAM/SCLM ....................... 266
16.6.5 Bits 6,7 : I2C system clock select bits ICK0, ICK1 ............................................... 266
16.6.6 The address receive in STOP mode/WAIT mode ............................................... 266
16.7 I2C0 control register 2 (S3D0 register)....................................................................... 267
16.7.1 Bit0: Time out detection function enable bit (TOE).............................................. 268
16.7.2 Bit1: Time out detection flag (TOF ) .................................................................... 268
16.7.3 Bit2: time out detection period select bit (TOSEL) .............................................. 268
16.7.4 Bits 3,4,5: I2C system clock select bits (ICK2-4) ................................................. 268
16.7.5 Bit7: STOP condition detection interrupt request bit (SCPIN) ............................. 268
16.8 I2C0 START/STOP condition control registers (S2D0 register) ................................. 269
16.8.1 Bit0-Bit4: START/STOP condition setting bits (SSC0-SSC4) ............................. 269
16.8.2 Bit5: SCL/SDA interrupt pin polarity select bit (SIP) ............................................ 269
16.8.3 Bit6 : SCL/SDA interrupt pin select bit (SIS) ....................................................... 269
16.8.4 Bit7: START/STOP condition generation select bit (STSPSEL).......................... 269
16.9 START Condition Generation Method ....................................................................... 270
16.10 START condition duplicate protect function .............................................................. 271
16.11 STOP Condition Generation Method ........................................................................ 271
16.12 START/STOP Condition Detect Operation ............................................................... 273
16.13 Address Data Communication ................................................................................. 274
16.13.1 Example of Master Transmit ............................................................................. 274
16.13.2 Example of Slave Receive ................................................................................ 275
16.14 Usage precautions.................................................................................................... 277
17. CAN Module ...............................................................................................280
17.1. CAN Module-Related Registers ................................................................................ 281

A-8
17.1.1. CAN0 Message Box ............................................................................................ 282
17.1.2. Acceptance Mask Registers ................................................................................ 284
17.1.3. CAN SFR Registers ............................................................................................ 285
17.1.3.1. C0MCTLj Register (j = 0 to 15) ..................................................................... 285
17.1.3.2. C0CTLR Register ......................................................................................... 286
17.1.3.3. C0STR Register............................................................................................ 287
17.1.3.4. C0SSTR Register ......................................................................................... 288
17.1.3.5. C0ICR Register............................................................................................. 289
17.1.3.6. C0IDR Register............................................................................................. 289
17.1.3.7. C0CONR Register ........................................................................................ 290
17.1.3.8. C0RECR Register......................................................................................... 291
17.1.3.9. C0TECR Register ......................................................................................... 291
17.1.3.10. C0TSR Register.......................................................................................... 292
17.1.3.11. C0AFS Register .......................................................................................... 292
17.2. Operational Modes .................................................................................................... 293
17.2.1. CAN Reset/Initialization Mode ............................................................................ 293
17.2.2. CAN Operation Mode .......................................................................................... 294
17.2.3. CAN Sleep Mode ................................................................................................ 294
17.2.4. CAN Interface Sleep Mode ................................................................................. 295
17.2.5. Bus Off State ....................................................................................................... 295
17.3. Configuration of the CAN Module System Clock ....................................................... 296
17.3.1. Bit Timing Configuration ...................................................................................... 296
17.3.2. Bit-rate................................................................................................................. 297
17.4. Acceptance Filtering Function and Masking Function ............................................... 298
17.5. Acceptance Filter Support Unit (ASU) ....................................................................... 299
17.6. Basic CAN Mode ....................................................................................................... 300
17.7. Return from Bus off Function..................................................................................... 301
17.8. Time Stamp Counter and Time Stamp Function........................................................ 301
17.9. Listen-Only Mode ...................................................................................................... 301
17.10. Reception and Transmission ................................................................................... 302
17.10.1. Reception .......................................................................................................... 303
17.10.2. Transmission ..................................................................................................... 304
17.11. CAN Interrupt ........................................................................................................... 305
18. CRC Calculation Circuit ............................................................................ 306
18.1. CRC Snoop ............................................................................................................... 306
19. Programmable I/O Ports ............................................................................309
19.1 Port Pi Direction Register (PDi Register, i = 0 to 3, 6 to 10) ....................................... 309

A-9
19.2 Port Pi Register (Pi Register, i = 0 to 3, 6 to 10)......................................................... 309
19.3 Pull-up Control Register 0 to Pull-up Control Register 2
(PUR0 to PUR2 Registers) ..... 309
19.4 Port Control Register .................................................................................................. 309
19.5 Pin Assignment Control register (PACR) .................................................................... 310
19.6 Digital Debounce function........................................................................................... 310
20. Electrical Characteristics ............................................................................323
20.1. Normal version .......................................................................................................... 323
20.2. T version .................................................................................................................... 344
21. Flash Memory Version ...............................................................................365
21.1 Flash Memory Performance ....................................................................................... 365
21.2 Memory Map............................................................................................................... 367
21.3 Functions To Prevent Flash Memory from Rewriting .................................................. 370
21.3.1 ROM Code Protect Function ................................................................................ 370
21.3.2 ID Code Check Function ...................................................................................... 370
21.4 CPU Rewrite Mode ..................................................................................................... 372
21.4.1 EW0 Mode ........................................................................................................... 373
21.4.2 EW1 Mode ........................................................................................................... 373
21.5 Register Description ................................................................................................... 374
21.5.1 Flash memory control register 0 (FMR0): ............................................................ 374
•FMR 00 Bit.................................................................................................................. 374
•FMR01 Bit................................................................................................................... 374
•FMR02 Bit................................................................................................................... 374
•FMSTP Bit .................................................................................................................. 374
•FMR06 Bit................................................................................................................... 374
•FMR07 Bit................................................................................................................... 374
21.5.2 Flash memory control register 1 (FMR1): ............................................................ 375
•FMR11 Bit ................................................................................................................... 375
•FMR16 Bit................................................................................................................... 375
•FMR17 Bit................................................................................................................... 375
21.5.3 Flash memory control register 4 (FMR4): ............................................................ 375
•FMR40 Bit................................................................................................................... 375
•FMR41 Bit................................................................................................................... 375
•FMR46 Bit................................................................................................................... 375
21.6 Precautions in CPU Rewrite Mode ............................................................................. 380
21.6.1 Operation Speed .................................................................................................. 380
21.6.2 Prohibited Instructions.......................................................................................... 380
21.6.3 Interrupts .............................................................................................................. 380

A-10
21.6.4 How to Access...................................................................................................... 380
21.6.5 Writing in the User ROM Space ........................................................................... 380
21.6.5.1 EW0 Mode ..................................................................................................... 380
21.6.5.2 EW1 Mode ..................................................................................................... 380
21.6.6 DMA Transfer ....................................................................................................... 381
21.6.7 Writing Command and Data ................................................................................. 381
21.6.8 Wait Mode ............................................................................................................ 381
21.6.9 Stop Mode ............................................................................................................ 381
21.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption
Mode ........................................................................................................................... 381
21.7 Software Commands .................................................................................................. 382
21.7.1 Read Array Command (FF16) ............................................................................... 382
21.7.2 Read Status Register Command (7016)................................................................ 382
21.7.3 Clear Status Register Command (5016) ............................................................... 383
21.7.4 Program Command (4016) ................................................................................................................................................. 383
21.7.5 Block Erase .......................................................................................................... 384
21.8 Status Register ........................................................................................................... 386
21.8.1 Sequence Status (SR7 and FMR00 Bits )............................................................ 386
21.8.2 Erase Status (SR5 and FMR07 Bits) ................................................................... 386
21.8.3 Program Status (SR4 and FMR06 Bits) ............................................................... 386
21.8.4 Full Status Check ................................................................................................. 387
21.9 Standard Serial I/O Mode ........................................................................................... 389
21.9.1 ID Code Check Function ...................................................................................... 389
21.9.2 Example of Circuit Application in Standard Serial I/O Mode ................................ 393
21.10 Parallel I/O Mode ...................................................................................................... 395
21.10.1 ROM Code Protect Function .............................................................................. 395
21.11 CAN I/O Mode .......................................................................................................... 396
21.11.1 ID code check function ....................................................................................... 396
21.11.2 Example of Circuit Application in CAN I/O Mode ................................................ 399
22. Package .................................................................................................... 400
Register Index ..................................................................................................401

B-1
Quick Reference to Pages Classified by Address
CAN0 wakeup interrupt control register C01WKIC 67
CAN0 successful reception interrupt control register C0RECIC 67
CAN0 successful transmission interrupt control regiser C0TRMIC 67
INT3 interrupt control register INT3IC 67
IC/OC 0 interrupt control register ICOC0IC 67
IC/OC 1 interrupt control register, ICOC1IC 67
I
2
C bus interface interrupt control register IICIC 67
IC/OC base timer interrupt control register, BTIC 67
S
CL S DA interrupt control register SCLDAIC 67
SI/O4 interrupt control register, S4IC, 67
INT5 interrupt control register INT5IC 67
SI/O3 interrupt control register, S3IC, 67
INT4 interrupt control register INT4IC 67
UART2 Bus collision detection interrupt control register BCNIC 67
DMA0 interrupt control register DM0IC 67
DMA1 interrupt control register DM1IC 67
CAN0 error interrupt control register C01ERRIC 67
A/D conversion interrupt control register ADIC 67
Key input interrupt control register KUPIC 67
UART2 transmit interrupt control register S2TIC 67
UART2 receive interrupt control register S2RIC 67
UART0 transmit interrupt control register S0TIC 67
UART0 receive interrupt control register S0RIC 67
UART1 transmit interrupt control register S1TIC 67
UART1 receive interrupt control register S1RIC 67
Timer A0 interrupt control register TA0IC 67
Timer A1 interrupt control register TA1IC 67
Timer A2 interrupt control register TA2IC 67
Timer A3 interrupt control register TA3IC 67
Timer A4 interrupt control register TA4IC 67
Timer B0 interrupt control register TB0IC 67
Timer B1 interrupt control register TB1IC 67
Timer B2 interrupt control register TB2IC 67
INT0 interrupt control register INT0IC 67
INT1 interrupt control register INT1IC 67
INT2 interrupt control register INT2IC 67
CAN0 message box 0: Identifier/DLC 282
CAN 0 message box 0: Data field 282
CAN0 message box 0: Time stamp 282
CAN0 message box 1: Identifier/DLC 282
CAN 0 message box 1: Data field 282
CAN0 message box 1: Time stamp 282
0000 16
0001 16
0002 16
0003 16
0004 16
0005 16
0006 16
0007 16
0008 16
0009 16
000A 16
000B 16
000C 16
000D 16
000E 16
000F 16
0010 16
0011 16
0012 16
0013 16
0014 16
0015 16
0016 16
0017 16
0018 16
0019 16
001A 16
001B 16
001C 16
001D 16
001E 16
001F 16
0020 16
0021 16
0022 16
0023 16
0024 16
0025 16
0026 16
0027 16
0028 16
0029 16
002A 16
002B 16
002C 16
002D 16
002E 16
002F 16
0030 16
0031 16
0032 16
0033 16
0034 16
0035 16
0036 16
0037 16
0038 16
0039 16
003A 16
003B 16
003C 16
003D 16
003E 16
003F 16
Address
Note: The blank areas are reserved and cannot be accessed by users.
Register Symbol Page
0040 16
0041 16
0042 16
0043 16
0044 16
0045 16
0046 16
0047 16
0048 16
0049 16
004A 16
004B 16
004C 16
004D 16
004E 16
004F 16
0050 16
0051 16
0052 16
0053 16
0054 16
0055 16
0056 16
0057 16
0058 16
0059 16
005A 16
005B 16
005C 16
005D 16
005E 16
005F 16
0060 16
0061 16
0062 16
0063 16
0064 16
0065 16
0066 16
0067 16
0068 16
0069 16
006A 16
006B 16
006C 16
006D 16
006E 16
006F 16
0070 16
0071 16
0072 16
0073 16
0074 16
0075 16
0076 16
0077 16
0078 16
0079 16
007A 16
007B 16
007C 16
007D 16
007E 16
007F 16
Processor mode register 0 PM0 37
Processor mode register 1 PM1 37
System clock control register 0 CM0 40
System clock control register 1 CM1 41
Address match interrupt enable register AIER 79
Protect register PRCR 60
Oscillation stop detection register CM2 42
Watchdog timer start register WDTS 81
Watchdog timer control register WDC 81
Address match interrupt register 0 RMAD0 79
Address match interrupt register 1 RMAD1 79
Voltage detection register 1 VCR1 32
Voltage detection register 2 VCR2 32
PLL control register 0 PLC0 44
Processor mode register 2 PM2 43
Voltage down detection interrupt register D4INT 32
DMA0 source pointer SAR0 87
DMA0 destination pointer DAR0 87
DMA0 transfer counter TCR0 87
DMA0 control register DM0CON 86
DMA1 source pointer SAR1 87
DMA1 destination pointer DAR1 87
DMA1 transfer counter TCR1 87
DMA1 control register DM1CON 86
Address
Register Symbol Page

B-2
Quick Reference to Pages Classified by Address
0080 16
0081 16
0082 16
0083 16
0084 16
0085 16
0086 16
0087 16
0088 16
0089 16
008A 16
008B 16
008C 16
008D 16
008E 16
008F 16
0090 16
0091 16
0092 16
0093 16
0094 16
0095 16
0096 16
0097 16
0098 16
0099 16
009A 16
009B 16
009C 16
009D 16
009E 16
009F 16
00A0 16
00A1 16
00A2 16
00A3 16
00A4 16
00A5 16
00A6 16
00A7 16
00A8 16
00A9 16
00AA 16
00AB 16
00AC 16
00AD 16
00AE 16
00AF 16
00B0 16
00B1 16
00B2 16
00B3 16
00B4 16
00B5 16
00B6 16
00B7 16
00B8 16
00B9 16
00BA 16
00BB 16
00BC 16
00BD 16
00BE 16
00BF 16
Address
Note: The blank areas are reserved and cannot be accessed b
y
users.
Register Symbol Page
00C0 16
00C1 16
00C2 16
00C3 16
00C4 16
00C5 16
00C6 16
00C7 16
00C8 16
00C9 16
00CA 16
00CB 16
00CC 16
00CD 16
00CE 16
00CF 16
00D0 16
00D1 16
00D2 16
00D3 16
00D4 16
00D5 16
00D6 16
00D7 16
00D8 16
00D9 16
00DA 16
00DB 16
00DC 16
00DD 16
00DE 16
00DF 16
00E0 16
00E1 16
00E2 16
00E3 16
00E4 16
00E5 16
00E6 16
00E7 16
00E8 16
00E9 16
00EA 16
00EB 16
00EC 16
00ED 16
00EE 16
00EF 16
00F0 16
00F1 16
00F2 16
00F3 16
00F4 16
00F5 16
00F6 16
00F7 16
00F8 16
00F9 16
00FA 16
00FB 16
00FC 16
00FD 16
00FE 16
00FF 16
CAN0 message box 2: Identifier/DLC 282
CAN0 message box 2: Data field 282
CAN0 message box 2: time stamp 282
CAN0 message box 3: Identifier/DLC 282
CAN0 message box 3: Data field 282
CAN0 message box 3: time stamp 282
CAN0 message box 4: Identifier/DLC 282
CAN0 message box 4: Data field 282
CAN0 message box 4: time stamp 282
CAN0 message box 5: Identifier/DLC 282
CAN0 message box 5: Data field 282
CAN0 message box 5: time stamp 282
Address
Register Symbol Page
CAN0 message box 6: Identifier/DLC 282
CAN0 message box 6: Data field 282
CAN0 message box 6: time stamp 282
CAN0 message box 7: Identifier/DLC 282
CAN0 message box 7: Data field 282
CAN0 message box 7: time stamp 282
CAN0 message box 8: Identifier/DLC 282
CAN0 message box 8: Data field 282
CAN0 message box 8: time stamp 282
CAN0 message box 9: Identifier/DLC 282
CAN0 message box 9: Data field 282
CAN0 message box 9: time stamp 282

B-3
Quick Reference to Pages Classified by Address
0100 16
0101 16
0102 16
0103 16
0104 16
0105 16
0106 16
0107 16
0108 16
0109 16
010A 16
010B 16
010C 16
010D 16
010E 16
010F 16
0110 16
0111 16
0112 16
0113 16
0114 16
0115 16
0116 16
0117 16
0118 16
0119 16
011A 16
011B 16
011C 16
011D 16
011E 16
011F 16
0120 16
0121 16
0122 16
0123 16
0124 16
0125 16
0126 16
0127 16
0128 16
0129 16
012A 16
012B 16
012C 16
012D 16
012E 16
012F 16
0130 16
0131 16
0132 16
0133 16
0134 16
0135 16
0136 16
0137 16
0138 16
0139 16
013A 16
013B 16
013C 16
013D 16
013E 16
013F 16
Address
Note: The blank areas are reserved and cannot be accessed b
y
users.
Register Symbol Page
0140 16
0141 16
0142 16
0143 16
0144 16
0145 16
0146 16
0147 16
0148 16
0149 16
014A 16
014B 16
014C 16
014D 16
014E 16
014F 16
0150 16
0151 16
0152 16
0153 16
0154 16
0155 16
0156 16
0157 16
0158 16
0159 16
015A 16
015B 16
015C 16
015D 16
015E 16
015F 16
0160 16
0161 16
0162 16
0163 16
0164 16
0165 16
0166 16
0167 16
0168 16
0169 16
016A 16
016B 16
016C 16
016D 16
016E 16
016F 16
0170 16
0171 16
0172 16
0173 16
0174 16
0175 16
0176 16
0177 16
0178 16
0179 16
017A 16
017B 16
017C 16
017D 16
017E 16
017F 16
CAN0 message box 10: Identifer/DLC 282
CAN0 message box 10: Data field 282
CAN0 message box 10: time stamp 282
CAN0 message box 11: Identifier/DLC 282
CAN0 message box 11: Data field 282
CAN0 message box 11: time stamp 282
CAN0 message box 12: Identifier/DLC 282
CAN0 message box 12: Data field 282
CAN0 message box 12: time stamp 282
CAN0 message box 13: Identifier/DLC 282
CAN0 message box 13: Data field 282
CAN0 message box 13: time stamp 282
Address
Register Symbol Page
CAN0 message box 14: Identifier/DLC 282
CAN0 message box 14: Data field 282
CAN0 message box 14: time stamp 282
CAN0 message box 15: Identifier/DLC 282
CAN0 message box 15: Data field 282
CAN0 message box 15: time stamp 282
CAN0 global mask register C0GMR 284
CAN0 local mask A register C0LMAR 284
CAN0 local mask B register C0LMBR 284

B-4
Quick Reference to Pages Classified by Address
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: This register is included in the flash memory version.
018016
018116
018216
018316
018416
018516
018616
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
020016
020116
020216
020316
020416
020516
020616
020716
020816
020916
020A16
020B16
020C16
020D16
020E16
020F16
021016
021116
021216
021316
021416
021516
021616
021716
021816
021916
021A16
021B16
021C16
021D16
021E16
021F16
021016
02FE16
02FF16
Address Register Symbol Page
Flash memory control register 4 (Note 2) FMR4 377
Flash memory control register 1 (Note 2) FMR1 376
Flash memory control register 0 (Note 2) FMR0 376
CAN0 message control register 0 C0MCTL0 285
CAN0 message control register 1 C0MCTL1 285
CAN0 message control register 2 C0MCTL2 285
CAN0 message control register 3 C0MCTL3 285
CAN0 message control register 4 C0MCTL4 285
CAN0 message control register 5 C0MCTL5 285
CAN0 message control register 6 C0MCTL6 285
CAN0 message control register 7 C0MCTL7 285
CAN0 message control register 8 C0MCTL8 285
CAN0 message control register 9 C0MCTL9 285
CAN0 message control register 10 C0MCTL10 285
CAN0 message control register 11 C0MCTL11 285
CAN0 message control register 12 C0MCTL12 285
CAN0 message control register 13 C0MCTL13 285
CAN0 message control register 14 C0MCTL14 285
CAN0 message control register 15 C0MCTL15 285
CAN0 control register C0CTLR 286
CAN0 status register C0STR 287
CAN0 slot status register C0SSTR 288
CAN 0 interrupt control register C0ICR 289
CAN0 extended ID register C0IDR 289
CAN0 configuration register C0CONR 290
CAN0 receive error count register C0RECR 291
CAN0 transmit error count register C0TECR 291
CAN0 time stamp register C0TSR 292
024016
024116
024216
024316
024416
024516
024616
024716
024816
024916
024A16
024C16
024D16
024E16
024F16
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
026016
02DF16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
02FE16
02FF16
Address Register Symbol Page
CAN0 acceptance filter support register C0AFS 292
Three-phase protect control register TPRC 131
0n-chip oscillator control register ROCR 41
Pin assignment control register PACR 319
Peripheral clock select register PCLKR 43
CAN0 clock select register CCLKR 44
I2C0 data shift register S00 250
I2C0 address register S0D0 249
I2C0 control register 0 S1D0 251
I2C0 clock control register S20 250
I2C0 start/stop condition control register S2D0 255
I2C0 control register 1 S3D0 253
I2C0 control register 2 S4D0 254
I2C0 status register S10 252

B-5
Quick Reference to Pages Classified by Address
Note : The blank areas are reserved and cannot be accessed by users.
0340 16
0341 16
0342 16
0343 16
0344 16
0345 16
0346 16
0347 16
0348 16
0349 16
034A 16
034B 16
034C 16
034D 16
034E 16
034F 16
0350 16
0351 16
0352 16
0353 16
0354 16
0355 16
0356 16
0357 16
0358 16
0359 16
035A 16
035B 16
035C 16
035D 16
035E 16
035F 16
0360 16
0361 16
0362 16
0363 16
0364 16
0365 16
0366 16
0367 16
0368 16
0369 16
036A 16
036B 16
036C 16
036D 16
036E 16
036F 16
0370 16
0371 16
0372 16
0373 16
0374 16
0375 16
0376 16
0377 16
0378 16
0379 16
037A 16
037B 16
037C 16
037D 16
037E 16
037F 16
Timer A1-1 register TA11 122
Timer A2-1 register TA21 122
Timer A4-1 register TA41 122
Three-phase PWM control register 0 INVC0 119
Three-phase PWM control register 1 INVC1 120
Three-phase output buffer register 0 IDB0 121
Three-phase output buffer register 1 IDB1 121
Dead time timer DTT 121
Timer B2 interrupt occurrence frequency set counter ICTB2 121
Position-data-retain function contol register PDRF 129
Port Function control register PFCR 131
Interrupt request cause select register 2 IFSR2A 68
Interrupt request cause select register IFSR 68, 76
SI/O3
transmit/receive register S3TRR 210
SI/O3 control register S3C 210
SI/O3
bit rate generator S3BRG 210
SI/O4
transmit/receive register S4TRR 210
SI/O4 control register S4C 210
SI/O4
bit rate generator S4BRG 210
UART2 special mode register 4 U2SMR4 172
UART2 special mode register 3 U2SMR3 172
UART2 special mode register 2 U2SMR2 171
UART2 special mode register U2SMR 171
UART2 transmit/receive mode register U2MR 168
UART2 bit rate generator U2BRG 167
UART2 transmit buffer register U2TB 167
UART2 transmit/receive control register 0 U2C0 169
UART2 transmit/receive control register 1 U2C1 170
UART2 receive buffer register U2RB 167
Address Register Symbol Page
0300 16
0301 16
0302 16
0303 16
0304 16
0305 16
0306 16
0307 16
0308 16
0309 16
030A 16
030B 16
030C 16
030D 16
030E 16
030F 16
0310 16
0311 16
0312 16
0313 16
0314 16
0315 16
0316 16
0317 16
0318 16
0319 16
031A 16
031B 16
031C 16
031D 16
031E 16
031F 16
0320 16
0321 16
0322 16
0323 16
0324 16
0325 16
0326 16
0327 16
0328 16
0329 16
032A 16
032B 16
032C 16
032D 16
032E 16
032F 16
0330 16
0331 16
0332 16
0333 16
0334 16
0335 16
0336 16
0337 16
0338 16
0339 16
033A 16
033B 16
033C 16
033D 16
033E 16
033F 16
Address Register Symbol Page
TM, WG register 0 G1TM0, G1PO0 139, 140
TM, WG register 1 G1TM1, G1PO1 139, 140
TM, WG register 2 G1TM2, G1PO2 139, 140
TM, WG register 3 G1TM3, G1PO3 139, 140
TM, WG register 4 G1TM4, G1PO4 139, 140
TM, WG register 5 G1TM5, G1PO5 139, 140
TM, WG register 6 G1TM6, G1PO6 139, 140
TM, WG register 7 G1TM7, G1PO7 139, 140
WG control register 0 G1POCR0 139
WG control register 1 G1POCR1 139
WG control register 2 G1POCR2 139
WG control register 3 G1POCR3 139
WG control register 4 G1POCR4 139
WG control register 5 G1POCR5 139
WG control register 6 G1POCR6 139
WG control register 7 G1POCR7 139
TM control register 0 G1TMCR0 138
TM control register 1 G1TMCR1 138
TM control register 2 G1TMCR2 138
TM control register 3 G1TMCR3 138
TM control register 4 G1TMCR4 138
TM control register 5 G1TMCR5 138
TM control register 6 G1TMCR6 138
TM control register 7 G1TMCR7 138
Base timer register G1BT 134
Base timer control register 0 G1BCR0 134
Base timer control register 1 G1BCR1 136
TM prescale register 6 G1TPR6 138
TM prescale register 7 G1TPR7 138
Function enable register G1FE 141
Function select register G1FS 141
Base timer reset register G1BTRR 137
Divider register G1DV 135
Interrupt request register G1IR 142
Interrupt enable register 0 G1IE0 143
Interrupt enable register 1 G1IE1 143
NMI digital debounce register NDDR 320
P17 digital debounce register P17DDR 320

B-6
Note : The blank areas are reserved and cannot be accessed by users.
03C0 16
03C1 16
03C2 16
03C3 16
03C4 16
03C5 16
03C6 16
03C7 16
03C8 16
03C9 16
03CA 16
03CB 16
03CC 16
03CD 16
03CE 16
03CF 16
03D0 16
03D1 16
03D2 16
03D3 16
03D4 16
03D5 16
03D6 16
03D7 16
03D8 16
03D9 16
03DA 16
03DB 16
03DC 16
03DD 16
03DE 16
03DF 16
03E0 16
03E1 16
03E2 16
03E3 16
03E4 16
03E5 16
03E6 16
03E7 16
03E8 16
03E9 16
03EA 16
03EB 16
03EC 16
03ED 16
03EE 16
03EF 16
03F0 16
03F1 16
03F2 16
03F3 16
03F4 16
03F5 16
03F6 16
03F7 16
03F8 16
03F9 16
03FA 16
03FB 16
03FC 16
03FD 16
03FE 16
03FF 16
A/D register 0 AD0 218
A/D register 1 AD1 218
A/D register 2 AD2 218
A/D register 3 AD3 218
A/D register 4 AD4 218
A/D register 5 AD5 218
A/D register 6 AD6 218
A/D register 7 AD7 218
A/D trigger control register ADTRGCON 217
A/D convert status register 0 ADSTAT0 218
A/D control register 2 ADCON2 216
A/D control register 0 ADCON0 216
A/D control register 1 ADCON1 216
Port P0 register P0 317
Port P1 register P1 317
Port P0 direction register PD0 316
Port P1 direction register PD1 316
Port P2 register P2 317
Port P3 register P3 317
Port P2 direction register PD2 316
Port P3 direction register PD3 316
Port P6 register P6 317
Port P7 register P7 317
Port P6 direction register PD6 316
Port P7 direction register PD7 316
Port P8 register P8 317
Port P9 register P9 317
Port P8 direction register PD8 316
Port P9 direction register PD9 316
Port P10 register P10 317
Port P10 direction register PD10 316
Pull-up control register 0 PUR0 318
Pull-up control register 1 PUR1 318
Pull-up control register 2 PUR2 318
Port control register PCR 319
Address
Register Symbol Page
0380 16
0381 16
0382 16
0383 16
0384 16
0385 16
0386 16
0387 16
0388 16
0389 16
038A 16
038B 16
038C 16
038D 16
038E 16
038F 16
0390 16
0391 16
0392 16
0393 16
0394 16
0395 16
0396 16
0397 16
0398 16
0399 16
039A 16
039B 16
039C 16
039D 16
039E 16
039F 16
03A0 16
03A1 16
03A2 16
03A3 16
03A4 16
03A5 16
03A6 16
03A7 16
03A8 16
03A9 16
03AA 16
03AB 16
03AC 16
03AD 16
03AE 16
03AF 16
03B0 16
03B1 16
03B2 16
03B3 16
03B4 16
03B5 16
03B6 16
03B7 16
03B8 16
03B9 16
03BA 16
03BB 16
03BC 16
03BD 16
03BE 16
03BF 16
Count start flag TABSR
Clock prescaler reset flag CPSRF
One-shot start flag ONSF 97
Trigger select register TRGSR 97, 124
Up-down flag UDF 96
Timer A0 register TA0 96
Timer A1 register TA1 96, 122
Timer A2 register TA2 96, 122
Timer A3 register TA3 96
Timer A4 register TA4 96, 122
Timer B0 register TB0 110
Timer B1 register TB1 110
Timer B2 register TB2 110,124
Timer A0 mode register TA0MR 95
Timer A1 mode register TA1MR 95, 125
Timer A2 mode register TA2MR 95, 125
Timer A3 mode register TA3MR 95
Timer A4 mode register TA4MR 95, 125
Timer B0 mode register TB0MR 109
Timer B1 mode register TB1MR 109
Timer B2 mode register TB2MR 109,125
Timer B2 special mode register TB2SC 116,123
UART0 transmit/receive mode register U0MR 168
UART0 bit rate generator U0BRG 167
UART0 transmit buffer register U0TB 167
UART0 transmit/receive control register 0 U0C0 169
UART0 transmit/receive control register 1 U0C1 170
UART0 receive buffer register U0RB 167
UART1 transmit/receive mode register U1MR 168
UART1 bit rate generator U1BRG 167
UART1 transmit buffer register U1TB 167
UART1 transmit/receive control register 0 U1C0 169
UART1 transmit/receive control register 1 U1C1 170
UART1 receive buffer register U1RB 167
UART transmit/receive control register 2 UCON 169
CRC snoop address register CRCSAR 307
CRC mode register CRCMR 307
DMA0 request cause select register DM0SL 85
DMA1 request cause select register DM1SL 86
CRC data register CRCD 307
CRC input register CRCIN 307
99, 110,
124
97, 110
Address
Register Symbol Page
Quick Reference to Pages Classified by Address