Renesas RC32012A User manual

Evaluation Kit Manual
R31UH0010EU0102 Rev.1.02 Page 1
Apr 20, 2022 © 2021-2022 Renesas Electronics
The RC32012A evaluation board allows customers to
evaluate Renesas ClockMatrix devices (e.g.,
RC32012A, QFN-72). This document discusses the
following:
▪ The board’s design, its power supply, and jumper
settings
▪ The input and output connectors for normal
operation
▪ How to bring up the board using the Timing
Commander software GUI
▪ How to configure and program the board to
generate standard-compliant frequencies
Kit Contents
The RC32012A EVK ships with the following:
▪ RC32012A Evaluation Board
▪ USB Type-A cable
PC Requirements
▪ Renesas Timing Commander Software installed
▪ ClockMatrix GUI
▪ USB 2.0 or USB 3.0 interface
▪ Windows XP SP3, or later
▪ Processor: Minimum 1GHz
▪ Memory: Minimum 512MB; recommended 1GB
▪ Available Disk Space: Minimum 600MB (1.5GB,
64-bit); recommended 1GB (2GB, 64-bit)
▪ Network access during installation if the .NET
framework is not currently installed on the system
Figure 1. RC32012A Evaluation Board
RC32012A
Evaluation Kit

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Contents
1. Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Board Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Voltage Selection Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 GPIO Switches, LEDs, and Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 USB Jack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 I2C between FTDI, ClockMatrix Device, and On-board EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. Working with Timing Commander for Programing/Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Default Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Using Timing Commander to Control the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Output Terminations and Rework to Take 1PPS Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Appendix A. How to Upgrade the Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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1. Board Design
The following diagram identifies the various components of the evaluation board: input and output SMA
connectors, power supply jacks, and some jumper settings necessary for the board operations. Detailed
descriptions are included below.
Figure 2. RC32012A Evaluation Board – Detailed
▪Input SMA connectors – There are five differential inputs labeled CLK0/nCLK0 - CLK4/nCLK4. Each input
clock can be configured differentially (LVDS, PECL 2.5V, and PECL 3.3V) or in single-ended format (CMOS).
▪Output SMA connectors – There are 12 outputs labeled as Q0/nQ0 - Q11/nQ11. Each output clock can be
configured differentially (LVDS, LVPECL, or user-defined amplitude) or in single-ended format (LVCMOS – in-
phase or out-of-phase).
▪GPIO switch, LEDs, and Test points – There are seven GPIOs available. Each GPIO can be set a “low” or
“high” level (if input) or displayed with an LED (if output). Some GPIOs are used to set the chip in a certain
working condition on power-up. For more information, see “Table 18. GPIO Pin Usage at Start-Up” in the
RC32012A Datasheet.
▪USB connector – A USB mini connector connects the evaluation board to a PC for GUI communications. No
power is consumed from the USB connector other than to power the FTDI USB device.
▪VDDQx voltage selection jumpers – Each output voltage can be individually supplied with 1.8V, 2.5V, or 3.3V.
These jumpers are used to select the voltage for the output voltages.
▪Reset button: A small button is used to reset the board.
▪OSCI Input connector – An SMA connector, J45, is provided to optionally supply a clock signal to overdrive
the crystal.
▪OCXO/TCXO Reference (Optional) – An OCXO/TCXO footprint, output at J82. It can be connected to J46
(below) as the reference for System DPLL.

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▪SysDPLL Input (Optional) – An SMA connector, J46, is provided to supply a local OCXO/TCXO reference as
an optional reference for System DPLL.
▪Crystal: A crystal of various frequencies must be present for board operations. A 3225 footprint is provided for
SMT crystals. For easy plug-in of a canned crystal, two through-holes are also available.
▪EEPROM – An SO-8 socket is provided to hold an EEPROM device of compatible package. EEROM is used to
store firmware and customer configuration data, if needed.
1.1 Board Power Supply
The evaluation board uses a single +5V supply for its power supplies. When running the board, please set the
bench power supply at 5V/2A. The red jack (J1) is positive; the black jack (J2) is the ground.
Multiple LDOs are used to generate 3.3V, 2.5V, and 1.8V from the +5V supply.
1.2 Voltage Selection Jumpers
There are eight headers/jumpers for selecting different voltages for different functional blocks of the device. Each
header has Pin 1 and 3 labeled in silkscreen – jumping pin 1 and pin 2 will select 3.3V; jumping pin 2 and pin 3 will
select 2.5V. No jumper will have 1.8V.
Please see the following example for JP4 and JP9 – JP4 will select 2.5V, JP9 will select 3.3V.
Figure 3. Example of Voltage Jumpers
The following list shows which head/jumper is used to select a specific voltage:
▪ JP1 – VDDD
▪ JP2 – VDDA
▪ JP3 – VCC_GPIO_DC
▪ JP4 – VDDO_Q8_3_5
▪ JP5 – VDDO_Q2_4_11
▪ JP6 – VDDO_1_10_7
▪ JP7 – VDD_CLK0
▪ JP9 – VDDO_Q0_9_6

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Note: VDD_FOD voltage is selected by resistor R908 and R909. In order to prevent damage to the device, both
R908 and R909 should not be stuffed, in which case VDD_FOD = 1.8V.
1.3 GPIO Switches, LEDs, and Test Points
An 8-bit, 3-position dip switch is used to set the logic levels for seven GPIOs (GPIO0-5, GPIO9). The GPIO levels
for each setting and the corresponding LED state are listed in the following table (see picture and labels in
Figure 4).
When the GPIOs are configured as outputs (such as User-Controlled or LOL indicator), the dip switch for the
corresponding GPIO should be placed in the Center position. The LED will indicate the state of the GPIO.
Figure 4. GPIO Setting and Status Display Area
1.4 USB Jack
This is a USB mini connector to the board. The other end of the USB cable is a USB Type A connector going to a
PC.
Table 1. GPIO Settings
Dip Switch Position GPIO Logic Level LED
Left Low On
Center High if GPIO is configured as Input
High or Low according to the GPIO output setting
High if GPIO is configured as Input
High or Low according to the GPIO output setting
Right High Off

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1.5 I2C between FTDI, ClockMatrix Device, and On-board EEPROM
One of the major differences between the QFN-72 ClockMatrix device and its BGA-144 counterpart is that there is
only one serial bus on the QFN-72 device. The I2C bus between the FTDI chip and ClockMatrix device is the
same bus between the ClockMatrix device and the on-board EEPROM. The on-board EEPROM is used to store
device firmware and/or customer’s configuration data. JP12 and JP13 must be jumped between Pin 1 and 2 to
enable the I2C connections.
2. Working with Timing Commander for Programing/Configuration
The following sections are best cross-referenced with the ClockMatrix GUI Step-by-Step User Guide that is
available on the ClockMatrix Timing Solutions page and various ClockMatrix device product pages.
2.1 Default Operation
The evaluation board can be operated off EEPROM, which has stored all information including firmware and a
default configuration data. A default operation provides a sanity check on the board before running the board
through the Timing Commander tool. Please set the board to the following default conditions (for jumper and
switch positions, see Figure 5):
▪ Set all the GPIOs to the Center position. This will ensure that GPIO9 is high and that the serial port is
configured for I2C 1-byte addressing.
▪ VDDA = 3.3V, VDD_GPIO_FOD = 1.8V, VDD0_Qx = 3.3V
▪ Crystal frequency 50MHz
▪ CLK0 = 25MHz
▪ FTDI, ClockMatrix device, and EEPROM share the same I2C bus by jumping Pin 1 and 2 of JP12 and JP13
With the above default conditions ready, connect the evaluation board to the PC using a USB cable (type A on the
PC side and mini-type on the board side), and power up the board using a single +5V supply. On power-up, the
ClockMatrix device will read its firmware and configuration data from EEPROM and update all the registers. When
this process completes, the following frequencies are available:
▪ Q0 = 122.88MHz
▪ Q1 = 122.88MHz
Table 2. EEPROM I2C Connections
JP12/JP13 JP12/JP13
Jumper position Pin 1 and 2 Pin 2 and 3
I2C Path FDTI and CM chip;
CM chip and EEPROM
N/A

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Figure 5. Board Setting for Default Operation
Note: In order to set GPIO9 to “High”, the switch for GPIO9 must be set either to the “+” (high) position or the
center position.
Before proceeding to communicate to the ClockMatrix device using the Timing Commander GUI, two I2C
connection methods are introduced:
1. Using the on-board FTDI circuit – The evaluation board has on-board FTDI circuitry to translate Timing
Commander access activities from USB to the I2C port of the ClockMatrix device. This is to connect the PC to
the board through the Type-B connector.
2. Using FTDI dongle (C232HM-DDHSL-0 cable) – The dongle has the same FTDI circuit as this board built in it
(see Figure 6). The benefit of using this dongle is to connect to the customer’s board and still enjoy the
debugging capabilities that Timing Commander has to offer.

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Figure 6. FTDI Dongle: USB Type-A at PC end and 10 Free-wires at the other end
The free wires are color-coded and numerically indexed as displayed in the following picture.
When using with Timing Commander, only four wires are used. When connecting to a customer board, connect
the Orange wire to SCL; tie the Yellow wire and Green wire together and connect to SDA; then, importantly,
connect the Black ground wire to the customer’s board GND. Assuming there is a pull-up resistor for SCL and
SDA, respectively, on customer board.
By using FTDI dongle, we can connect to a customer board and use the Timing Commander GUI just like working
on a ClockMatrix evaluation board. When using the FTDI dongle to connect to a customer board, in Timing
Commander “Connection Settings” window, “On-board USB (SPI)” is selected in Connection Interface box (see
Figure 10), same as connecting to a Renesas evaluation board.
Color Pin Number Name Type Description
Orange 2 SCL Output Serial Clock
Yellow 3 SDA Input/Output Serial data signal shorted together to
create bidirectional data (both yellow
and green wires must be shorted
together)
Green 4

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2.2 Using Timing Commander to Control the Board
Once the default operation is successful, complete the following steps using Timing Commander to configure and
program the ClockMatrix device as per your application requirements.
1. Power up the board and set the main serial port in I2C mode by GPIO9 = “high”. See Figure 5 for the GPIO9
position. Connect the board to PC.
2. Start the Timing Commander software.
You will see options of “New Setting File” and “Open Setting file”. For a new configuration, select “New Setting
File”
Figure 7. Starting Up Timing Commander GUI

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3. After selecting “New Settings File”, a device selection window will appear. In the window, choose the intended
device in the list (RC32012A is selected in this example).
Click the button at the lower right corner of the window (red circle) to browse and select the correct personality
file (in this example, personality Version 10.0.1 is selected), then click OK.
Figure 8. Selecting RC32012A using Personality File Version 10.0.1

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4. The GUI window with the RC32012A block diagram will open for configurations; or if “Open Settings File” is
selected in Step 5 above, you will be prompted to browse and select an existing .tcs file and the personality file.
When the configuration file is open, all configured values will be displayed as in Figure 9.
Figure 9. Timing Commander GUI with a Settings File Opened
5. In order to connect the board with Timing Commander (PC), click the button (red circle) at the up-right corner
of the GUI to set up the communication protocols (see Figure 9). After I2C and one-byte addressing are
selected, click OK to close the window (see Figure 10).
Figure 10. Setting I2C for Connecting the Board with GUI

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6. Click the chip symbol at the up-right corner to initiate the connection. The connection is made with a green band
appearing at the up-right corner of the window, as shown below.
Figure 11. Green Band Appears when a Valid Connection is Made
7. If ClockMatrix device’s firmware, or the firmware loaded from EEPROM, has a different version from that in the
Personality file, a firmware version mismatch warning message will appear. Click “Close” button to close the
message window and a connection is made.
Figure 12. Firmware Version Mismatch Warning Message

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8. Once the connection is made, the firmware version can be read within the GUI. Click the “Firmware Utility”
button to bring up the Firmware Utility window, as shown below.
Figure 13. Reading Firmware Version
9. Within Firmware Utility window, click the “Get Firmware Version” button will read the firmware version.
Figure 14. Read Firmware Version of ClockMatrix Chip
10. In the case where the firmware version mismatches each other, a firmware upgrade is required to update the
device’s firmware. To update the device’s firmware, complete the Firmware Version Update steps in
Appendix A. How to Upgrade the Firmware.

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2.3 Output Terminations and Rework to Take 1PPS Input
All outputs are terminated by a 100-ohm resistor across the output pair. This is the recommended termination
regardless of the Voffset and Vswing settings. Since the outputs are DC-coupled, they will support a 1PPS output
without any need for rework.
Note: When connecting the outputs to measurement equipment, use a DC-block to ensure that the output
operates at its intended Voffset; otherwise, the equipment may load the output down and cause degraded
performance.
The following rework must be implemented in order to support a 1PPS input clock. All input clocks for the
evaluation board are AC-coupled and terminated as in Figure 15.
Figure 15. Input Clock’s AC-coupling and Terminations
For a 1PPS input, a single-ended input with DC-coupling is recommended. As such, the populated AC-coupling
capacitor must be removed and the input must be configured as LVCMOS, not differential. In Figure 15, to make
CLK0 supportive of 1PPS input, first configure CLK0 as LVCMOS in Timing Commander (see Figure 16).
Figure 16. Configuring CLK0 as CMOS to Receive a 1PPS Input
Once in LVCMOS mode, CLK0_P and CLK0_N will be two separate LVCMOS inputs instead of a differential pair.
To make CLK0_P receive a 1PPS input, replace C881 with a 0-ohm resistor, while at the same time, remove R765
and R770.
3. Schematic Diagrams
Schematic diagrams are located at the rear of the document.

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Appendix A. How to Upgrade the Firmware
Upload Firmware to the RAM
1. Connect to the EVB.
2. Power up the EVB with No EEPROM Present. This ensures the FW is 4.0.2.7017.
3. The GUI will indicate that the FW on the Chip does not match the GUI FW. Press “Close”.
4. Open the “Firmware Utility” window.
5. Update the Firmware first, then press “Update RAM to Current FW Only”

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6. In the next dialog, press “Yes” and wait around 4 minutes.
7. Once the FW updates, a dialog will indicate a successful update.
8. Press “Get Firmware Version” to verify that the RAM was updated correctly.

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Upload Firmware to the EEPROM
9. Once the Firmware has been updated to the chip (steps 1 to 8), install the EEPROM on the EVB.
10. Press
a. EEPROM Utility
b. Connect to EEPROM
c. Write Firmware to EEPROM
11. In the Next Dialog, press “Yes”.
12. When asked to “Verify” the EEPROM, press “No”:

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13. In the next window, press “Close” to start the EEPROM write.
14. Wait about 5mins. The EEPROM write will complete with this window below. Press “Close”.
Verify the EEPROM Programming
15. Power cycle the Evaluation Board.
16. Disconnect and reconnect to the chip.
17. Read back the Firmware Version to ensure it’s correct (see steps 3 and 7).
4. Ordering Information
5. Revision History
Part Number Description
RC32012A-EVK RC32012A Evaluation Kit
Revision Date Description
1.02 Apr 20, 2022 Updated schematics; removed embedded files and appended files to the rear of the document.
1.01 Oct 28, 2021 Updated the Schematic Diagrams
1.00 Oct 12, 2021 Initial release

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3
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2
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D D
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B B
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PROJECT NAME
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DESIGN TITLE
DRAWING NUMBER REVISION
RELEASE DATE SHEET
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SILKSCRN:
XO_DPLL
Maximum voltage on pin 7 = 1.8V
Place close to ClockMatrix
8A34005: R9749=0ohm, R9748=DNI
Others : R9749=DNI, R9748=0ohm
VDDO_Q0
VDDO_Q1
VDDO_Q2
VDDO_Q3
VDDO_Q4
VDDO_Q5
VDDO_Q6
VDDO_Q7
VDDO_Q8
VDDO_Q9
VDDO_Q10
VDDO_Q11
VDD_FOD_0
VDD_FOD_2
VDD_FOD_5
VDDA_0
VDDA_1
VDD_FOD_0
VDD_CLK0_0
VDDD
VDDD_0
VDD_FOD
CLK_Q0_P 8
CLK_Q0_N 8
CLK_Q1_P 8
CLK_Q1_N 8
CLK_Q2_P 8
CLK_Q2_N 8
CLK_Q3_P 8
CLK_Q3_N 8
CLK_Q4_P 8
CLK_Q4_N 8
CLK_Q5_P 8
CLK_Q5_N 8
CLK_Q6_P 8
CLK_Q6_N 8
CLK_Q7_P 8
CLK_Q7_N 8
CLK_Q8_P 8
CLK_Q8_N 8
CLK_Q9_P 8
CLK_Q9_N 8
CLK_Q10_P 8
CLK_Q10_N 8
CLK_Q11_P 8
CLK_Q11_N 8
GPIO3 5
GPIO9 5
GPIO1 5
GPIO2 5
GPIO4 5
GPIO5 5
GPIO0 5
CLK_CLK0_P
CLK_CLK0_N
CLK_CLK1_P
CLK_CLK1_N
CLK_CLK2_P
CLK_CLK2_N
CLK_CLK3_P
CLK_CLK3_N
CLK_CLK4_P
CLK_CLK4_N
OSCO
OSCI
PLL_I2C_SCL_SCLK
PLL_I2C_SDA_SDIO
PLL_I2C_SDA_SDI
PLL_I2C_SDA_CSN
JTAG_SEL
TST_CHIP_RST_N_OD
VDD_DIG_16
Title
Size Document Number Rev
Date: Sheet of
C
09/13/2021
Title
Size Document Number Rev
Date: Sheet of
C
09/13/2021
Title
Size Document Number Rev
Date: Sheet of
C
21110
09/13/2021
R3920
C418 2200pF
C694 0.1uF
U409
CM-72QFN-Twist
OSCO
1
OSCI
2
VDDA_PDCP_XTAL
3
VDDA_FB
4
nMR
5
VDD_CLK
6
XO_DPLL
7
CLK0
8
nCLK0
9
CLK1
10
nCLK1
11
CLK2
12
nCLK2
13
CLK3
14
nCLK3
15
VDD_DIG
16
CLK4
17
nCLK4
18
SCLK
19
SDIO
20
SDI_A1
21
CS_A0
22
FILTER
23
VDDA_LC_BG
24
nTEST
25
GPIO3
26
nQ11
27
Q11
28
VDDO_Q11
29
VDD_DIA_FOD_B
30
VDDO_Q7
31
Q7
32
nQ7
33
GPIO9
34
nQ6
35
Q6
36
VDDO_Q6 37
VDDO_Q5 38
Q5 39
nQ5 40
VDDO_Q4 41
Q4 42
nQ4 43
VDDO_Q10 44
Q10 45
nQ10 46
GPIO2 47
VDD_GPIO_FOD 48
GPIO1 49
nQ9 50
Q9 51
VDDO_Q9 52
nQ3 53
Q3 54
VDDO_Q3 55
GPIO5 56
nQ2 57
Q2 58
VDDO_Q2 59
VDDO_Q1 60
Q1 61
nQ1 62
GPIO4 63
nQ0 64
Q0 65
VDDO_Q0 66
VDD_DIA_FOD_A
67
VDDO_Q8 68
Q8 69
nQ8 70
GPIO0 71
cREG_XTAL 72
EPAD
73
R9748
0
R934 0
C695 0.1uF
R910 2.67kDNS
C871 0.1uF
R456
0
R9749
0
R467 2.67kDNS
C762 0.1uF
DNS
C761 10uF
R466 49.9 DNS
C763 0.1uF
DNS
C692 10uF
RK19-03-13
J46
5-1814832-1
C693 0.1uF
OSCI
OSCO
VDD_DIG_16
VDD_DIG_16