Renesas RX Family Installation and operating instructions

Application Note
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RX Family
Hardware Design Guide
Introduction
This application note presents notes on board design and layout examples when using RX Family MCUs.
Target Device
RX Family
Contents
1. Board Configuration.................................................................................................................2
1.1 Block Diagram.........................................................................................................................................2
1.2 Component Layout..................................................................................................................................3
1.3 Layer Structure........................................................................................................................................5
2. Board Design...........................................................................................................................7
2.1 Power Supply Pins ..................................................................................................................................7
2.2 VCL Pin ...................................................................................................................................................9
2.2.1 Two-Layer Board.................................................................................................................................11
2.2.2 Board With Four or More Layers.........................................................................................................13
2.3 Reset Pin...............................................................................................................................................14
2.4 Clock I/O Pins........................................................................................................................................16
2.5 Analog Input Pins ..................................................................................................................................21
2.6 Signal Pins with Large Current Flows ...................................................................................................23
2.7 Signal Pins with Rapid Level Changes .................................................................................................23
3. Board Wiring Pattern Examples.............................................................................................24
3.1 Example Two-Layer Board Wiring Pattern............................................................................................24
3.2 Example Four-Layer Board Wiring Pattern ...........................................................................................27
4. Reference Documents...........................................................................................................31
Revision History............................................................................................................................32

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1. Board Configuration
1.1 Block Diagram
Figure 1.1 shows a block diagram of the board configuration used in the design example.
RX Family
Main crystal
oscillator
Sub crystal
oscillator
Power supply
circuit
Reset circuit
3.3 V
Reset signal
Analog input Analog signal
Main clock
Subclock
External power supply
5 V
Figure 1.1 Block Diagram

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1.2 Component Layout
Figure 1.2 and Figure 1.3 show component layout examples. Note that the board thickness is typically
1.6 mm.
The feedback resistor (R2) and damping resistors (R3 and R5) are usually unnecessary. (In Figure 1.2 no
feedback resistors are mounted.) If the oscillator manufacturer stipulates that external feedback resistors or
damping resistors should be added, mount them according to the manufacturer’s specification.
In some cases 0 Ω damping resistors (R3 and R5) or wiring pattern connection can be used.
Analog input
Subclock
Reset circuit
DC jack
Power
supply circuit
RX Family
Main clock
Figure 1.2 Component Layout (Front Side)

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Figure 1.3 Component Layout (Back Side)

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1.3 Layer Structure
Figure 1.4 shows layer structure examples.
Second-layer wiring pattern
GND, signal, and analog GND
First-layer wiring pattern
Power supply, signal, and
analog power supply
Fourth-layer wiring pattern
Signal and analog GND
Third-layer wiring pattern
Solid power layer
Second-layer wiring pattern
Solid GND layer
First-layer wiring pattern
Signal and analog power supply
Two-layer board
Four-layer board
Figure 1.4 Layer Structure Examples

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Figure 1.5 shows an example wiring pattern for a two-layer board.
GND
GND
+3.3 V
+5 V
+3.3 V
+3.3 V
Power IC
RX Family
Reset IC
Main clock
Subclock Analog
GND
Analog power
supply
Single-point
connection to
analog GND
Red: +3.3 V route
Green: GND route
Arrange the paths of the power and GND traces from the power supply
circuit to VCC/VSS as a pair. A typical route is shown as an example.
Also, in this example the paths on the first and second layers are
superimposed on one another to form a pair.
Figure 1.5 Example Wiring Pattern for Two-Layer Board

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2. Board Design
2.1 Power Supply Pins
Connect the power supply pins to GND via a bypass capacitor (decoupling capacitor). Use a capacitor with
good frequency characteristics, such as a ceramic capacitor. The wiring length between each power supply
pin and the bypass capacitor must be equal and as short as possible. In addition, pair the appropriate power
supply pins. For example, the VCC pin, AVCC pin, and VREFH pin should be paired with the VSS pin, AVSS
pin, and VREFL pin, respectively. Refer to the User’s Manual: Hardware of the product used for more details
on pairing pins. The traces for the power supply pins must be wider than traces for other signal lines and
must be connected to the power supply and GND via a bypass capacitor. Figure 2.1 shows example
connections of power supply pins and bypass capacitors.
CC
Bad power supply wiring pattern Good power supply wiring pattern
CCapacitor
Through hole
Wiring trace
VSS
VCC
VSS
VCC
RX Family RX Family
Connections between pins, capacitor, and
through hole are as short as possible.
Not appropriate because the power
supply pins are connected to GND
without an intervening capacitor.
Appropriate because the power
supply pins are connected to GND
via a capacitor.
Digital GND
Digital GND
Digital power
supply
Digital power
supply
Figure 2.1 Example Connections of Power Supply Pins and Bypass Capacitors
Refer to the application notes below for details of the analog power-supply pins. The latest versions and
guides to new products can be downloaded from the Renesas Electronics website.
•RX610 Group: Notes on Analog Power Supply Printed Circuit Board Patterns (R01AN0271EJ)
•RX62N Group, RX621 Group: Notes on Analog Power Supply Printed Circuit Board Patterns
(R01AN0269EJ)
•RX62T Group: Notes on Analog Power Supply Printed Circuit Board Patterns (R01AN0638EJ)
Board design hint
A bypass capacitor connected to the power supply pins can be placed so as to route noise to GND
during MCU operation.

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Figure 2.2 shows an example power supply pin circuit configuration, and Figure 2.3 shows an example
power supply pin wiring pattern
VCC
VSS
RX Family MCU
Connection to
power supply
Figure 2.2 Example Power Supply Pin Circuit Configuration
+3.3 V
GND
Bypass
capacitor Make connection to through
hole via a capacitor.
VSS pin
VCC pin
Figure 2.3 Example Power Supply Pin Wiring Pattern

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2.2 VCL Pin
Connect the VCL pin to GND via a capacitor with a rated capacitance matching that specified in the user’s
manual of the device used. The wiring length between the VCL pin and the capacitor should be 8 mm or less
(4 mm or less if possible).
Note that GND wiring patterns vary depending on the number of board layers. Section 2.2.1 describes two-
layer boards, and section 2.2.2 describes boards with four or more layers.
Board design hint
If the wiring length between the VCL pin and capacitor is longer than 8 mm, the parasitic resistance
increases, decreasing the effectiveness of the capacitor and possibly causing noise from the VCC
pin. When the wiring length between the VCL pin and capacitor is longer than 8 mm, the wiring
pattern should be designed so that the parasitic resistance is less than 1 Ω. Figure 2.4 shows a
formula for calculating the parasitic resistance.
w
lt
Wiring on printed circuit board
Parasitic resistance = R + 2pfL (Ω) < 1 (Ω)
R = lσwt
/(Ω)
f = 20 (MHz) (internal fluctuation in MCU when power is supplied)
L = 0.2l ln
[2l (w+t)
/
{}]
+0.5 (µH)
ωL = 2pfL(Ω)
Figure 2.4 Formula for Calculating Parasitic Resistance
In the following example, the formula shown in Figure 2.4 is used to calculate the parasitic resistance.
Example:
Wiring length (l): 0.008 m (8 mm)
Wiring width (w): 0.00025 m (0.25 mm)
Wiring thickness (t): 0.000035 m (0.035 mm)
Resistivity of copper (ρ= 1 / σ): 0.0000000169 Ω•m
Parasitic resistance = R + 2pfL
= (l / σwt) + 2 p20 (0.2 l (loge (2 l / (w + t)) +0.5))
= 0.01545 + 2 3.1416 20 0.00724
0.9253 (Ω)

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Figure 2.5 shows an example circuit configuration for the VCL pin.
VCL
VSS
RX Family MCU
Refer to the user’s manual of the device
used regarding the rated capacitance of
the capacitor connected to the VCL pin.
Figure 2.5 Example VCL Pin Circuit Configuration

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2.2.1 Two-Layer Board
•Use the GND wiring pattern to form a guard for the portion of the back side between the VCL pin and the
capacitor.
•Make connections to GND via at least four through holes.
•Make the GND wiring traces as wide as possible.
Figure 2.6 shows an example VCL pin wiring pattern on a two-layer board.
C
Capacitor
VCL
VSS
CFront side
wiring pattern Back side
wiring pattern
a
baand b≤ 8 mm (4 mm if
possible)
When aand b> 8 mm,
ensure parasitic resistance
for aand bis less than 1 Ω.
Through hole
VBAT
Layer under
VCL is GND.
Four or more
through holes
Figure 2.6 Example VCL Pin Wiring Pattern on Two-Layer Board

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Figure 2.7 shows an example VCL pin wiring pattern (two-layer board).
GND
GND
Four or more GND
through holes
Four or more GND
through holes
VCL
capacitor GND under
VCL signal
VCL pin
VBAT pin
VSS pin
Figure 2.7 Example VCL Pin Wiring Pattern (Two-Layer Board)

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2.2.2 Board With Four or More Layers
Figure 2.8 shows an example VCL pin wiring pattern (board with four or more layers).
GND
GND
Four or more GND
through holes
Four or more GND
through holes
VCL
capacitor
GND under
VCL signal
Make a slit to allow
coupling of the VCL
capacitor and VSS pin.
Make a slit to allow
coupling of the
subclock GND
guard and VSS pin.
VCL pin
VBAT pin
VSS pin
Figure 2.8 Example VCL Pin Wiring Pattern (Board With Four or More Layers)

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2.3 Reset Pin
When directly connecting the reset pin to the reset IC, position the reset IC as close as possible. Noise can
also be reduced by inserting a low-pass filter. Do not run the trace for the reset pin parallel to other traces
(traces with large current flows or rapid level changes). If no low-pass filter is used, shield the trace for the
reset pin with the GND trace. The GND traces used for shielding should be at least 0.3 mm wide and there
should be a space of 0.3 mm to 2.0 mm between them and adjacent traces.
Board design hint
The pulse width input to the reset pin is specified in the timing requirements. If the noise input to the
reset pin has a shorter width than the specified pulse width, a reset condition may be released before
the MCU’s internal initialization has completed, possibly causing program runaway.
Figure 2.9 shows an example reset pin circuit configuration, and Figure 2.10 shows an example reset pin
wiring pattern (multilayer board).
RES#
VSS
RX Family MCU
Reset IC
(RNA51957)
OUT
GND
Figure 2.9 Example Reset Pin Circuit Configuration (With Low-Pass Filter)
Through hole
Front side
wiring pattern RResistor
Capacitor
R
R
C
RES#
C
VSS
RX Family
Back side
wiring pattern
OUT
Reset IC
GND
VCC
To +3.3 V
To GND
To GND
Run the wiring traces on the
front side if it will not affect the
peripheral circuits.
If at all possible place the filter
circuit on the MCU side to avoid
affecting the peripheral circuits.
Depending on the specifications
of the reset IC, a pull-up resistor
may be necessary.
Figure 2.10 Example Reset Pin Wiring Pattern

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Figure 2.11 shows an example reset pin wiring pattern.
RX Family
Reset IC
Filter circuit
Reset signal RES# pin
VSS pin
Figure 2.11 Example Reset Pin Wiring Pattern

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2.4 Clock I/O Pins
The wiring traces for the clock I/O pins (EXATL, XTAL, XCIN, and XCOUT) should be as short as possible,
including peripheral circuits. Shield the wiring pattern for the clock I/O pins with the GND pattern and do not
arrange the traces for the clock I/O pins in parallel with or across other traces (traces with large current flows
or rapid level changes). The GND traces used for shielding should be at least 0.3 mm wide and there should
be a space of 0.3 mm to 2.0 mm between them and adjacent traces. In addition, do not place the GND wiring
pattern and power supply wiring pattern in layers under a peripheral circuit incorporating a crystal oscillator.
Refer to the application notes below for information on crystal oscillators with low load capacitance (low-CL
crystal oscillators). The latest versions and guides to new products can be downloaded from the Renesas
Electronics website.
•RX200 Series: Design Guide for Sub-Clock Circuits (R01AN1012EJ)
•RX600, RX700 Series: Design Guide for Sub-Clock Circuits (R01AN1187EJ)
Board design hint
If noise impinges on the clock I/O pins, the clock waveforms may become distorted, possibly causing
an MCU malfunction or program runaway. In addition, accurate clock signals cannot be input to the
MCU if there is a potential difference between the VSS inputs to the MCU and oscillators.
Figure 2.12 shows an example clock I/O pin circuit configuration.
RX Family MCU
Contact the oscillator
manufacturer for information
on load capacitance.
XTAL
XCIN
EXTAL
XCOUT
VSS
Figure 2.12 Example Clock I/O Pin Circuit Configuration

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Figure 2.13, Figure 2.14, and Figure 2.15 show example clock I/O pin wiring patterns.
Back side wiring pattern
Through hole
Front side wiring pattern Resistor Capacitor
R
XCIN
RX Family
XCOUT
XTAL
EXTAL
VSS
RC
CC
R
R
C
C
The inner layers must have no wiring
traces in the areas enclosed by the
yellow borders, which is used for the
GND wiring pattern on the back side.
Also, the back side GND wiring
traces should be at least 0.1 mm
wider than the front side GND wiring
traces. However, there must be no
wiring traces on the back side if the
board thickness is less than 1.2 mm.
Strengthen the GND guard
between the front side and
back side with optimal
placement of through
holes. In particular, ensure
that both edges of the
guard do not form an
antenna.
Crystal
oscillator
Crystal
oscillator
Figure 2.13 Example Clock I/O Pin Wiring Pattern

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Through hole
Front side wiring pattern Resistor Capacitor
R
XCIN
RX Family
XCOUT
XTAL
EXTAL
VSS
RC
CC
R
R
C
C
The front side GND
shielding width should be
at least 0.3 mm.
Through hole for VSS coupling
Crystal
oscillator
Crystal
oscillator
Figure 2.14 Example Clock I/O Pin Wiring Pattern (Front Side)

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Back side wiring pattern
Through hole
Through hole for VSS coupling
The back side GND wiring
pattern is divided into three
“islands” as indicated by the
yellow borders, one for each
crystal oscillator. The wiring
pattern also allows for VSS
coupling.
Figure 2.15 Example Clock I/O Pin Wiring Pattern (Back Side)

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Figure 2.16 shows an example clock I/O pin wiring pattern.
GND guard
Crystal oscillator
Feedback resistor
Crystal oscillator
Limiting resistor
Limiting resistor
GND guard
XCIN
XCOUT
XTAL
VSS
EXTAL
Figure 2.16 Example Clock I/O Pin Wiring