Renesas uPD60620 User manual

All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Technology Corp.
website (http://www.renesas.com).
www.renesas.com
Industrial Ethernet PHY
Dual PHY ASSP
uPD60620
uPD60620A
uPD60621A
R19UH0083ED0100
March 19, 2013
User Manual

R19UH0083ED0100
User Manual 2
Notice
1. All information included in this document is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice.
Before purchasing or using any Renesas Electronics products listed herein, please confirm the
latest product information with a Renesas Electronics sales office. Also, please pay regular and
careful attention to additional and different information to be disclosed by Renesas Electronics
such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents,
copyrights, or other intellectual property rights of third parties by or arising from the use of
Renesas Electronics products or technical information described in this document. No license,
express, implied or otherwise, is granted hereby under any patents, copyrights or other
intellectual property rights of Renesas Electronics or others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas
Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this
document are provided only to illustrate the operation of semiconductor products and application
examples. You are fully responsible for the incorporation of these circuits, software, and
information in the design of your equipment. Renesas Electronics assumes no responsibility for
any losses incurred by you or third parties arising from the use of these circuits, software, or
information.
5. When exporting the products or technology described in this document, you
should comply with the applicable export control laws and regulations and follow the procedures
required by such laws and regulations. You should not use Renesas Electronics products or the
technology described in this document for any purpose relating to military applications or use by
the military, including but not limited to the development of weapons of mass destruction.
Renesas Electronics products and technology may not be used for or incorporated into any
products or systems whose manufacture, use, or sale is prohibited under any applicable
domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable care in preparing the information
included in this document, but Renesas Electronics does not warrant that such information is
error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by
you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified according to the following three
quality grades: “Standard”, “High Quality”, and “Specific”. The recommended applications for
each Renesas Electronics product depends on the product’s quality grade, as indicated below.
You must check the quality grade of each Renesas Electronics product before using it in a
particular application. You may not use any Renesas Electronics product for any application
categorized as “Specific”without the prior written consent of Renesas Electronics. Further, you
may not use any Renesas Electronics product for any application for which it is not intended
without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in
any way liable for any damages or losses incurred by you or third parties arising from the use of
any Renesas Electronics product for an application categorized as “Specific” or for which the
product is not intended where you have failed to obtain the prior written consent of Renesas
Electronics.

R19UH0083ED0100
User Manual 3
The quality grade of each Renesas Electronics product is “Standard” unless otherwise
expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”: Computers; office equipment; communications equipment; test and
measurement equipment; audio and visual equipment; home electronic
appliances; machine tools; personal electronic equipment; and industrial
robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control
systems; anti-disaster systems; anti- crime systems; safety equipment; and
medical equipment not specifically designed for life support.
“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor
control systems;medical equipment or systems for life support (e.g. artificial
life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes
that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document
within the range specified by Renesas Electronics, especially with respect to the maximum
rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no
liability for malfunctions or damages arising out of the use of Renesas Electronics products
beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability
of its products, semiconductor products have specific characteristics such as the occurrence of
failure at a certain rate and malfunctions under certain use conditions. Further, Renesas
Electronics products are not subject to radiation resistance design. Please be sure to
implement safety measures to guard them against the possibility of physical injury, and injury or
damage caused by fire in the event of the failure of a Renesas Electronics product, such as
safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other appropriate
measures. Because the evaluation of microcomputer software alone is very difficult, please
evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to
environmental matters such as the environmental compatibility of each Renesas Electronics
product. Please use Renesas Electronics products in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without
limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or
losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or
in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions
regarding the information contained in this document or Renesas Electronics products, or if you
have any other inquiries.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics
Corporation and also includes its majority- owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured
by or for Renesas Electronics.

R19UH0083ED0100
User Manual 4
General Precautions in the Handling of ASSP Products
The following usage notes are applicable to all ASSP products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions
under General Precautions in the Handling of ASSP Products and in the body of the manual differ from
each other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation with
an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
LSI, an associated shoot-through current flows internally, and malfunctions occur due to the
false recognition of the pin state as an input signal become possible. Unused pins should be
handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register settings and
pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins
are not guaranteed from the moment when power is supplied until the reset process is
completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power reaches
the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do not
access these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock signal
has stabilized.
When the clock signal is generated with an external resonator (or from an external oscillator)
during a reset, ensure that the reset line is only released after full stabilization of the clock
signal. Moreover, when switching to a clock signal produced with an external resonator (or by
an external oscillator) while program execution is in progress, wait until the target clock signal is
stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm that
the change will not lead to problems.
The characteristics of ASSP in the same group but having different part numbers may differ
because of the differences in internal memory capacity and layout pattern. When changing to
products of different part numbers, implement a system-evaluation test for each of the products.
6. Patent for IEEE1588
A number of patents exist for systems related to IEEE1588. Renesas would request that
customers ensure they comply with the relevant rights for these patents. Renesas does not accept
any responsibility for infringement of any patent rights by the customer.

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User Manual 5
How to Use This Manual
(1) Purpose and Target Readers
This manual is designed to provide the user with an understanding of the
hardware functions and electrical characteristics of the PHY. It is intended for
users designing application systems incorporating the PHY. A basic knowledge of
electric circuits, logical circuits, and PHYs is necessary in order to use this
manual. The manual comprises an overview of the product; descriptions of the
PHY, system control functions, peripheral functions, and electrical characteristics;
and usage notes.
Particular attention should be paid to the precautionary notes when using the
manual. These notes occur within the body of the text, at the end of each section,
and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does
not list all revisions. Refer to the text of the manual for details.
The following documents apply to the Ethernet PHY products . Make sure to
refer to the latest versions of these documents. The newest versions of the
documents listed may be obtained from the Renesas Electronics Web site.
Document
Type
Description
Document Title
Document No.
User’s
manual for
Hardware
Hardware specifications
(pin assignments,
memory maps,
peripheral function
specifications, electrical
characteristics, timing
charts) and operation
description.
Note: Refer to the
application notes for
details on using
peripheral functions.
User’s manual
Industrial
Ethernet
PHY
Dual PHY ASSP
This User’s manual
R19UH0083ED0100
Application
Note
Information on using
peripheral functions and
application examples.
Sample programs.
Information on writing
programs in assembly
language and C.
Application Note
industrial
Ethernet
Dual PHY
ASSP Layout
recommendation
and design rule
R19AN0015ED0100
Renesas
Technical
Update
Product specifications,
updates on documents,
etc.
Customer
Notification
Ethernet PHY
Operating
Precautions
R19TU0004ED0100

R19UH0083ED0100
User Manual 6
(2) Notation of Numbers and Symbols
Abbreviation
Full Form
Register p.n
Register n at PHY address p
Register p.n.b
Bit ‘b’ in register address n at PHY address p
Register PHY.n
PHY stands for PHY address “0” or “1” so this would mean
register n in any of the two PHYs, can by PHY address 0 or
PHY address 1.
(3) Register Notation
Abbreviation
Full Form
RW
Readable or writeable
SC
Self Clearing
RO
Read Only
WO
Write Only
LH
Latch High, when the device sets the register it stays high until
actively written to 0 even if the condition that set it disappears
LL
Latch Low, the register stays low until actively written to 1
WC
Cleared by hardware after writing
RC
Cleared after reading by hardware
NASR
Not affected by software reset

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User Manual 7
(4) List of Abbreviations and Acronyms
Abbreviation
Full Form
ACIA
Asynchronous Communication Interface Adapter
bps
bits per second
CRC
Cyclic Redundancy Check
DMA
Direct Memory Access
DMAC
Direct Memory Access Controller
GSM
Global System for Mobile Communications
Hi-Z
High Impedance
IEBus
Inter Equipment Bus
I/O
Input/Output
IrDA
Infrared Data Association
LSB
Least Significant Bit
MSB
Most Significant Bit
NC
Non-Connect
PLL
Phase Locked Loop
PU
Pull Up
PD
Pull Down
PWM
Pulse Width Modulation
SFR
Special Function Register
SIM
Subscriber Identity Module
UART
Universal Asynchronous Receiver/Transmitter
PTP
Precision Timer Protocol
VCO
Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective
owners.

R19UH0083ED0100
User Manual 8
Table of Contents
General Description .......................................................... 12
1.1 Overview of product features .......................................................................12
1.2 Special product features...............................................................................13
1.3 Applications ...................................................................................................13
Pin Functions..................................................................... 14
2.1 Pin-out Information .......................................................................................14
2.1.1 Pin Layout ........................................................................................................................14
2.1.2 Port Pins ...........................................................................................................................15
System Diagram ................................................................ 17
3.1 Device block diagram....................................................................................18
Global Hardware Description ........................................... 19
4.1 Register Access.............................................................................................19
4.2 General SMI Control Register 7.31...............................................................20
4.3 Power Control Register 7.30.........................................................................21
4.4 PHY Status Register 7.28..............................................................................22
4.5 Strap option Register 7.27 ............................................................................22
4.6 PHY LED Status Register 7.24......................................................................23
4.7 Interrupt Status register 7.20........................................................................24
4.8 Interrupt Mask register 7.21..........................................................................25
4.9 GPIO ...............................................................................................................26
4.9.1 GPIO_CONFIG_0 Register 7.0 ........................................................................................26
4.9.2 GPIO_CONFIG_1 Register 7.1 ........................................................................................27
4.9.3 GPIO_CONFIG_2 Register 7.2 ........................................................................................28
4.9.4 GPIO_CONFIG_3 Register 7.3 ........................................................................................28
4.9.5 GPIO_CONFIG_4 Register 7.4 ........................................................................................29
4.10 Strap Options .............................................................................................30
PHY..................................................................................... 32
5.1 General Description ......................................................................................32
5.2 Clock Generator PLL.....................................................................................33
5.3 Analog Frontend............................................................................................33
5.3.1 Adaptive Equalizing ........................................................................................................33
5.3.2 100Base TX Receiver ADC..............................................................................................33
5.4 Digital Signal Handling .................................................................................33
5.4.1 DSP ...................................................................................................................................33
5.4.2 Baseline Wander Correction ..........................................................................................33
5.4.3 NRZI/MLT-3 Encoding / Decoding..................................................................................34

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User Manual 9
5.4.4 Scrambler / Descrambler ................................................................................................34
5.4.5 5B/4B Encoding / Decoding............................................................................................34
5.5 Functional Description..................................................................................36
5.5.1 Collision detection ..........................................................................................................36
5.5.2 Carrier Sense detection ..................................................................................................36
5.5.3 Auto Crossover (MDI/MDI-X) ..........................................................................................36
5.5.4 Auto-Polarity ....................................................................................................................37
5.5.5 Auto-Negotiation..............................................................................................................37
5.5.6 Bad Line recognition .......................................................................................................40
5.5.7 Latency .............................................................................................................................45
5.5.8 Special Isolation Mode....................................................................................................45
5.5.9 Repeater / Media converter.............................................................................................46
5.6 PHY Register List ..........................................................................................47
5.6.1Register PHY.0 - Basic Control ......................................................................................47
5.6.2 Register PHY.1 - Basic Control ......................................................................................48
5.6.3 Register PHY.2 - PHY Identifier ......................................................................................48
5.6.4 Register PHY.3 - PHY Identifier ......................................................................................49
5.6.5 Register PHY.4 - Auto-Negotiation Advertisement ......................................................49
5.6.6 Register PHY.5 - Auto-Negotiation Link Partner Ability (Base Page) ........................50
5.6.7 Register PHY.5 - Auto-Negotiation Link Partner Ability (Next Page) .........................51
5.6.8 Register PHY.6 - Auto-Negotiation Expansion .............................................................51
5.6.9 Register PHY.7 - Auto-Negotiation Next Page Transmit .............................................52
5.6.10 Register PHY.16 - Silicon Revision ...........................................................................52
5.6.11 Register PHY.17 - Mode Control/Status ....................................................................53
5.6.12 Register PHY.18 - Special Modes ..............................................................................55
5.6.13 Register PHY.19 - Elastic Buffer Status register (Loopback Mode only) ..............55
5.6.14 Register PHY.20 –Reserved ......................................................................................56
5.6.15 Register PHY.21 –Reserved ......................................................................................56
5.6.16 Register PHY.22 –Reserved (TSTREAD2 / TSTWRT)..............................................56
5.6.17 Register PHY.23 –BER Counter ................................................................................57
5.6.18 Register PHY.24 –FEQ monitor Register .................................................................58
5.6.19 Register PHY.25 –Diagnosis Control/Status Register............................................59
5.6.20 Register PHY.26 –Diagnosis Counter Register .......................................................60
5.6.21 Register PHY.27 - Special Control/Status Indications.............................................60
5.6.22 Register PHY.28 - Reserved .......................................................................................61
5.6.23 Register PHY.29 - Interrupt Source Flags.................................................................61
5.6.24 Register PHY.30 - Interrupt Enable............................................................................61
5.6.25 Register PHY.31 - PHY Special Control/Status ........................................................62
External Components ....................................................... 63
6.1 Clock...............................................................................................................63
6.2 Internal Switching Regulator ........................................................................63
6.2.1 Power-Up Sequence........................................................................................................63
Support of IEEE1588 (uPD60621A only) .......................... 64
7.1 IEEE1588 ........................................................................................................64
7.2 Register access to PTP .................................................................................65

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User Manual 10
7.3 1588 Clock Control ........................................................................................65
7.3.1 CLOCK_STATUS Register 6.0 ........................................................................................66
7.3.2 CLOCK_READ Register 6.1 ...........................................................................................66
7.3.3 CLOCK_WRITE Register 6.2...........................................................................................66
7.3.4 CLOCK_OFFSET Register 6.3 ........................................................................................67
7.3.5 CLOCK_DRIFT Register 6.4............................................................................................68
7.4 Frame Handling Unit .....................................................................................68
7.4.1 One step mode.................................................................................................................69
7.4.2 Two step mode.................................................................................................................69
7.4.3 Transparent Clock Mode.................................................................................................69
7.4.4 Timestamp Status Register 6.6 ......................................................................................71
7.4.5 Timestamp Config Register 6.7......................................................................................72
7.4.1 TIMESTAMP_LINE_EVENT Register 6.8........................................................................72
7.4.2 PTP_CONFIG_n Register 6.9 / 6.13 ................................................................................74
7.4.3 PHY_DELAY_TX_n Register 6.11 / 6.15.........................................................................76
7.4.4 PHY_DELAY_RX_n Register 6.12 / 6.16 ........................................................................76
7.5 Input Capture Unit .........................................................................................78
7.5.1 Input Event Control Register 7.12..................................................................................79
7.5.2 Input Capture Pin Control register 7.8 ..........................................................................80
7.5.3 Input Capture Pin Control register 7.9 ..........................................................................81
7.5.4 Input Capture Pin Control register 7.10.........................................................................82
7.5.5 INPUT_EVENT_DATA_READ_WORD Register 7.15.....................................................83
7.5.6 INPUT_EVENT_DATA_BLOCK_READ Register 7.14 ...................................................84
7.5.7 INPUT_CAPTURE_DATA_POINTER Register 7.13.......................................................84
7.6 Pulse Generator Unit.....................................................................................85
7.6.1 Pulse Output Control Register 7.16 ...............................................................................86
7.6.2 PULSE_STARTTIME Register 7.17.................................................................................87
7.6.3 PULSE_WIDTH Register 7.19 .........................................................................................88
7.6.4 PULSE_INTERVAL Register 7.18 ...................................................................................88
Electrical Characteristics.................................................. 89
8.1 AC Timing.......................................................................................................89
8.1.1 Serial Management Interface (SMI) Timing ...................................................................89
8.1.2 Reset Timing ....................................................................................................................90
8.1.3 Clock Timing ....................................................................................................................91
8.1.4 100Base-TX Timings .......................................................................................................92
8.1.5 10Base-T Timings............................................................................................................94
8.1.6 RMII 10/100Base-TX Timings..........................................................................................96
8.1.7 Sequence for turn on ......................................................................................................98
8.10 DC Characteristics.....................................................................................99
8.10.1 Absolute Maximum Ratings .......................................................................................99
8.10.2 Recommended Operating Conditions.....................................................................100
8.10.3 DC Electrical Characteristics ...................................................................................101
8.10.4 Differential Parameters on Secondary Side of Transformer.................................101
8.10.5 100Base-FX Output Characteristics .......................................................................102

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User Manual 11
Physical dimensions ....................................................... 103
Revision history .............................................................. 104

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User Manual 12
General Description
The extended dual-channel 10/100 Ethernet PHYs uPD60620 uPD60620A and
uPD60621A are fully integrated Physical layer devices to connect to standard
IEEE802.3 Ethernet networks. Today’s industrial networking standards often
implement daisy-chain or ring structures, in which a dual-channel PHY
configuration makes a perfect fit.
These devices specifically focus on low latency and low jitter to support today’s
industrial Ethernet standards. In addition, the uPD60621A features hardware
support for IEEE1588 V2. Renesas Electronics’ specific enhanced diagnosis
features allow permanent cable quality monitoring for easy maintenance in
factory automation applications.
The PHY can connect to unshielded twisted-pair (UTP) cable via external
magnetics or to optical fiber via fiber PMD modules. It interfaces to an Ethernet
MAC layer through the IEEE 802.3 Standard Media Independent Interface (MII)
or reduced MII (RMII) interface.
The uPD60621A also includes support for PTP according to IEEE1588 Version 1
and 2. To support this, an 80-bit clock is included in the PHY. Timestamps with a
resolution of as low as 1ns can be taken from received and transmitted frames
and events on external pins. The device also supports one-step and two-step
timestamp insertion and supports transparent mode.
1.1 Overview of product features
Two channel PHY
Fully standard compliant with IEEE 802.3i/802.3u for 100BASE-TX,
100BASE-FX and 10BASE-T
Integrated PMD sub-layer featuring adaptive equalization and baseline
wander correction
IEEE 802.3u auto-negotiation and parallel detection
Full and half duplex operation
Supports automatic polarity detection and correction
Supports automatic MDI/MDI-X crossover
Supports IEEE1588 V1 and V2 (uPD60621A only)
Up to 20 programmable GPIO’s for trigger and capture (uPD60621A only)
2.5V and 3.3V MAC interface
Flexible MAC interface: MII and RMII (uPD60620 only)
Serial management port (MDC/MDIO)
Supports user programmable interrupts

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User Manual 13
Enables software power-up/down and automatic power up/down by energy
detection
Single 3.3 V power supply with optional separated 1.5V
Operating temperature: Tambient = -40 to +85°C (Tjunction from -40 to +125°C)
LQFP80 package (7 mm x 7 mm)
1.2 Special product features
Low latency and low jitter for industrial networking
Fast link-up option in auto-negotiation
Fast link-loss detection
Cable monitoring and error detection
Permanent cable quality tracking
Enhanced system testability (such as bypass, loopback and cable length
measurement by TDR)
1 ns resolution timer for hardware support of IEEE1588 (uPD60621A only)
Timestamping function to timestamp incoming and outgoing frames and pin
activity (uPD60621A only)
Output pins controllable by internal clock (uPD60621A only)
100BASE-TX, 100BASE-FX Repeater (uPD60620A, uPD60621A only)
100BASE-TX to 100BASE-FX Media converter (uPD60620A, uPD60621A
only)
1.3 Applications
Industrial networking such as Profinet, Ethernet/IP, CIPsync, ModbusTCP,
EtherCAT and SercosIII
10/100 Mbps LAN on motherboard (LOM) and network interface card (NIC)
Switches, routers and repeaters with 10/100 Mbps capable ports
Mobile base stations
Test and measurement applications
Home servers, broadband routers, printers, and IP phones
Telecom base stations
Real-time networking

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Pin Functions
2.1 Pin-out Information
2.1.1 Pin Layout

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User Manual 15
2.1.2 Port Pins
Power Supply
Pins
Comment
REGBVDD
70, 71
3.3V voltage regulator input
REGBGND
74, 75
GND for voltage regulator
VDDIO
32, 50, 66
3.3V/2.5V IO power supply
VDD33ESD
20
3,3V input
P1AGND, P0AGND
8, 14
Analog GND for PHY
REGAGND
76
Analog GND for regulator
REGAVDD
77
Analog 3.3V power supply for regulator
GNDIO
31
GND for I/O
GND15
51
GND for digital core
VDD15
30, 52
1.5V Digital VDD
VSSAPLL
9
Analog GND for PLL
VDDAPLL
11
Analog 1.5V power supply for PLL
VDDACB
10
Analog 3.3V power supply (common for
both channels)
P1VDDMEDIA,
P0VDDMEDIA
3, 19
Analog 1.5V power supply for PHY
REGLX
72, 73
Output voltage regulator, connect to
external coil
REGFB
78
Feedback to voltage regulator, connect to
external capacitor
REGOFF
80
Regulator disable,
Hi: Regulator disabled
Low: Regulator enabled
Pin Name
I/O
Function
Alternate
Function
Pin
Number
Comment
RESETB
I
RESET
1
TEST
I
TEST
2
Connect to GND
P1RXN
I
Media
Interface
4
P1RXP
I
5
P1TXN
O
6
P1TXP
O
7
P0RXN
I
18
P0RXP
I
17
P0TXN
O
16
P0TXP
O
15
EXTRES
Resistor
12
Connect to GND
via 12.4kΩresistor
ATP
Test
13
Pull Down (5kΩ)
P0COL
O
P0COL
P0SD/GPIO19
21
P1COL
O
P1COL
P1SD/GPIO18
22

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User Manual 16
P1TXD0
I
PHY1MII
23
P1TXD1
I
24
P1TXD2
I
GPIO17
25
P1TXD3
I
GPIO16
26
P1TXERR
I
GPIO15
27
P1TXEN
I
28
P1TXCLK
O
29
XCLK0
I
XCLK0
50MHz (RMII)
33
Clock input in
external clock
mode
XCLK1
O
XCLK1
34
Open in external
clock mode
P1RXD0
O
PHY1MII
35
P1RXD1
O
36
P1RXD2
O
GPIO14
37
P1RXD3
O
GPIO13
38
P1RXDV
O
P1CRS_DV
39
P1RXERR
O
40
P1RXCLK
O
41
P1CRS
O
GPIO12
42
P0TXD0
I
PHY0MII
43
P0TXD1
I
44
P0TXD2
I
GPIO11
45
P0TXD3
I
GPIO10
46
P0TXERR
I
GPIO9
47
P0TXEN
I
48
P0TXCLK
O
49
P0RXD0
O
PHY0MII
53
P0RXD1
O
54
P0RXD2
O
GPIO8
55
P0RXD3
O
GPIO7
56
P0RXDV
O
P0CRS_DV
57
P0RXERR
O
58
P0RXCLK
O
59
P0CRS
O
GPIO6
60
P1100BTLED
O
LED
GPIO5/INT
61
MDC
I
SMI
62
MDIO
I/O
63
P0100BTLED
O
LED
GPIO4/INT
64
P1ACTLED
O
GPIO3/INT
65
P1LINKLED
O
GPIO2/INT
67
P0ACTLED
O
GPIO1/INT
68
P0LINKLED
O
GPIO0/INT
69
DR
O
Device
Ready
79

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User Manual 17
System Diagram
The picture below shows the system diagram. The PHY is connected to the MAC
through a MII or RMII interface. On the other side it is connected either to a CAT5
cable through magnetics or to a fibre cable.
Renesas
Renesas

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User Manual 18
3.1 Device block diagram
The device consists of two PHY’s each connected to a PTP Framer block used to
de-/encode the PTP frames and timestamp them, a PTP timer block containing
the PTP clock, and an I/O block for general configuration and I/O handling. The
PTP support is only available on the uPD60621A.

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User Manual 19
Global Hardware Description
The device consists of two Ethernet PHYs combined in a single package. In
addition it includes a control block which is used to control shared resources such
as LED outputs, interrupts, and low-power modes. All are accessible through a
two wire bidirectional Serial Management Interface.
4.1 Register Access
All registers can be accessed through the MII / SMI interface. The SMI is a serial
interface defined in IEEE802.3 for access to PHY registers. The following picture
shows a typical access using the SMI interface:
MDC
MDIO ...
32 1's 0 1 10 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
Write Cycle
Preamble Start of
Frame
OP
Code PHY Address Register Address Turn
Around
Data
D15 D14 D1 D0
...
MDC
MDIO ...
32 1's 0 1 1 0 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 D15 D14 D1 D0
Read Cycle
Preamble Start of
Frame
OP
Code PHY Address Register Address Turn
Around Data
...
The PHY address denotes the address of the PHY, while the register address is
the address of the register within the addressed PHY. The device uses the PHY
addresses to support access to the PTP block and the Global Configuration
registers. The address table is as follows:
PHY Address (Binary)
Ressource
Comments
NM000
PHY0
NM001
PHY1
NM010
reserved
NM011
Reserved
NM100
Reserved
NM101
Reserved
NM110
PTP
uPD60621A only
NM111
GLOBAL_CONFIG
PTP
The values of the bits N and M can be configured as a strap option.

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User Manual 20
4.2 General SMI Control Register 7.31
The following register is used for configuration of the SMI:
Bit
Name
Description
Mode
Reset
15
RESET
1: Initiates a hardware reset of the
complete device (stays active until
cleared by software)
0: Release Reset
W
0
14
SMI_SHORT
_PREAMBLE
1: Enable short preamble support.
0: Short Preamble mode for SMI
interface not enabled
RW
0
13:9
Reserved
Write as 0
RW
0
8
Reserved
Write as 0
RW
1
7:2
Reserved
Write as 0
RW
0
1
PHY1_
DISREGARD
_ADDRESS
1: PHY 1 ignores the PHY address
when the device is being written
0: The PHY checks for the PHY
address
RW
0
0
PHY0_
DISREGARD
_ADDRESS
1: PHY 0 ignores the PHY address
when the device is being written
0: The PHY checks for the PHY
address
RW
0